JPH09205U - Camera viewfinder display - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a display device in a finder in which the display in the finder does not flicker. In a camera having at least two sets of light emitting diodes D1 to D4 and D5 to D8 in a finder, a photoelectric conversion circuit 4 for continuously measuring the brightness in the finder, and a finder measured by the photoelectric conversion circuit 4 Digital hysteresis comparator circuit 10 for comparing internal luminance with a predetermined value, and the light emitting diodes D1 to D4 and D5 to D
8 is selectively turned on with different brightness, and a display circuit 13 that switches a set of display elements that are turned on according to the comparison result of the digital hysteresis comparator circuit 10 is provided. Has hysteresis.

Description

[Detailed description of the invention]

[0001]

[Technical field of invention]

 The present invention relates to a camera display device having means for electrically displaying various information in a viewfinder of a camera.

[0002]

[Prior art and its problems]

 When a light emitting element such as an LED (light emitting diode) is used for display in the viewfinder of the camera, the brightness in the viewfinder changes according to the brightness of the subject. Therefore, if the brightness of the light emitting element is constant, the display is easy to see when the viewfinder is dark, but it is difficult to see when the viewfinder is bright. For this reason, the brightness of the display is changed continuously or stepwise according to the brightness in the viewfinder, and the brightness of the display is changed so that the display is bright when the viewfinder is bright and the display is dark when the viewfinder is dark. It may be changed according to the internal brightness (hereinafter referred to as brightness modulation). However, when the brightness of the display element is changed stepwise in the brightness modulation, the brightness in the viewfinder changes to the brightness change point of the display element. When it is near, the brightness of the display element changes drastically with a slight change in the brightness in the finder or the subject, and the display in the viewfinder flickers, making it very difficult to see.

[0003]

[Purpose of the invention]

 The present invention has been made in view of the problems of the above-described conventional in-viewfinder display device, and an object thereof is to provide an in-finder display device in which the display in the viewfinder does not flicker.

[0004]

[Outline of the invention]

 The present invention which achieves this object, in a camera having at least two sets of display elements in the finder, includes an in-finder brightness measuring device for continuously measuring the brightness in the finder and an in-finder brightness measuring means. A set of a comparison means for comparing the measured in-view luminosity with a predetermined value, and a display element that selectively turns on the plurality of sets of display elements with different brightness and turns on according to the comparison result of the comparison means. It is characterized in that the display circuit for switching between and the comparator circuit includes a comparator circuit for giving a hysteresis to the predetermined value.

[0005]

[Embodiment of the invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a display circuit having intensity modulation with hysteresis in the viewfinder display of the camera of the present invention, and FIG. 2 is a circuit diagram thereof. In the above circuit diagram, the oscillation circuit 1 oscillates a clock pulse signal of 65.536 KHz (hereinafter referred to as "signal a"), and the signal a is input to the timing pulse generation circuit 2 and the timing pulse generation circuit 2 outputs the signal. The signals b, c, d, e and f necessary for each circuit block are generated based on a. The 8-bit binary up counter 8 which operates at the falling edge of the signal c (16.384 KHz) is composed of flip-flops F3 to F10, the signal b is input to its ￣R terminal, and the ￣R terminal input is "L". "all output ¯Q ₀ ~¯Q ₇ when the level is at" H ". It should be noted that, "¯R" to have your herein, such as "¯Q ₀ ~¯Q _7", the symbol "¯" which was given in front of the sign shows the top bar, means that the active low or inverted, ing.

The outputs Q _{0 to} Q ₇ are connected to a digital-analog conversion circuit 7 (hereinafter referred to as “D / A conversion circuit”) and a finder brightness information register 9 (hereinafter referred to as “Bv register”). It The D / A conversion circuit 7 converts the input 8-bit digital signal into a corresponding analog voltage (hereinafter referred to as “Aout voltage”), and its Aout voltage output is connected to the comparator 5.

The photoelectric conversion circuit 4 measures the in-finder brightness by a light receiving element and converts it into an analog voltage, and the analog voltage output is connected to the comparator 5 together with the Aout voltage. The comparator 5 compares the two inputs and inputs the result to the latch pulse circuit 6.

The latch pulse circuit 6 is composed of inverters G1, G5, NAND gates G2, G3, G4, G6 and flip-flops F1, F2. Output to Q. The Q and Q outputs of the flip-flops F1 and F2 are set to Q = “L” and Q = “H” when the R terminal is “L” regardless of the logic of other input terminals. The signals a, b and d and the output of the comparator 5 are input to the latch pulse circuit 6, and the NAND gate G6 outputs a latch pulse. The latch pulse is connected to the Bv register 9.

The Bv register 9 is connected to the binary up counter 8 and inputs the output values Q _{0 to} Q ₇ of the counter 8 when the CL terminal is at the “L” level and at the “H” level. To latch. The outputs D3 to D7 of the Bv register 9 are connected to the digital Hilteresis comparator circuit 10. Digital Hilteresis Comparator circuit 10 is divided into a comparator section 10-a and a latch section 10-b. The comparator section 10-a includes inverters G7, G8, G20, NAND gates G9, G10, AND gates G11, G12, G13, And NOR gate G14, and the latch section 10-b is composed of inverters G15 and G25 and NAND gates G16, G17, G18 and G19. The comparator section 10-a outputs a comparator output from the NOR gate G14, and the comparator output is input to the latch section 10-b. The latch unit 10-b also receives the output signal b of the timing pulse generation circuit 2. The latch unit 10-b outputs a latch output from the NAND gate G18, and the latch output is input to the display circuit 13 and the comparator unit 10-a.

A central processing unit (hereinafter referred to as “CPU”) 3 inputs all necessary information such as camera aperture information, shutter speed information, film sensitivity information, subject brightness information, and uses those information. Is a circuit for calculating display information, shutter speed value, aperture value, etc. In FIGS. 1 and 2, only Bv register information (subject luminance information) is entered as an input, and only display information is entered as an output.

The display information register 11 receives the display information data from the CPU 3 and the signal f of the timing pulse generation circuit 2. The signal f is a display data output switching signal of the display information register 11. The display information decoder circuit 12 is connected to the output from the display information register 11. The display circuit 13 inputs the output of the digital hilterisis comparator circuit 10 and the signal f of the timing pulse generation circuit 2 and is connected to the output of the display information decoder circuit 12. The display circuit 13 includes a NAND gate G21, AND gates G22, G23, an inverter G24, current limiting resistors R1 to R6, NPN transistors QA and QB, and light emitting diodes D1 to D8, and light emitting diodes D1 to D4, Each of D5 to D8 is dynamically driven.

The circuit operation of this embodiment will be described below. Signal a of 65.536KH _Z of the oscillating circuit 1 is input to the timing pulse generating circuit 2, a timing pulse generating circuit 2 to the result signal b, c, d, e, f are produced. The signals a, b, and c are shown at 3-1, 3-3, and 3-2 in FIG. Signal c is 16.384KH _Z, a clock pulse that is twice the peripheral at the rising edge of signal a. The signals b and c are input to the 8-bit binary up counter 8, and when the signal b is "L", the circuit is reset, and when the signal b is "H", the counting operation is performed at the falling edge of the signal c. Output ¯Q ₇ ~¯Q ₀ of 8-bit binary up-counter 8, "11111111", "11111110", "11111101", changes from "11111100""00010000".

The D / A conversion circuit 7 inputs the outputs Q _{7 to} Q ₀ and generates a stepwise voltage waveform (Aout voltage) 3-4 in FIG. Assuming that the analog voltage of the photoelectric conversion circuit 4 has the relationship of FIG. 3 relative to the Aout voltage shown in 3-4 of FIG. 3, when the photoelectric conversion analog voltage becomes higher than the Aout voltage, the comparator 5 It inverts and outputs the waveform of 3-6. The Bv register 9 latches the output values of the 8-bit binary up counter 8 Q _{0 to} Q ₇ when the comparator 5 is inverted, and the latched data is a digital value corresponding to the brightness in the finder. .

The latch operation will be described in detail below. FIG. 4 is an enlarged view of a part of the timing chart of FIG. 4-1 is signal a (65.536KHz), 4-2 is signal c (16.384KHz), 4-3 is signal b, 4-4 is Aout voltage, 4-5 is photoelectric conversion analog voltage, 4-6 is comparator. 5 output, 4-7 is the output signal d of the timing pulse generating circuit 2, 4-8, 4-9, 4-10 and 4-11 are the output of the NAND gate G4 in the latch pulse circuit 6 and the flip, respectively. The Q output of the flop F1, the Q output of the flip-flop F2, ^{and the} output of the NAND gate G6 are shown.

At the start of the operation of the circuit, the signal b (_RESET) becomes “L” to reset each flip-flop, and the state A in FIG. 4, that is, G4 = “L”, F1Q = “L”, F2_Q = “H” and G6 = “H”. When the comparator 5 is inverted and becomes "L", the state B is set. Here, when the signal d becomes "H" (state C in FIG. 4), all the inputs to the NAND gate G2 become "H", so G2 = "L" and G4 = "H". The inputs of the NAND gate G3 (signal b and NAND gate G14) are all "H" in the flip-flop composed of the NAND gates G3 and G4, so that the output state of the comparator 5 is kept as long as the signal b is "H". Regardless of the value, the values of G3 = "L" and G4 = "H" are latched. Since the flip-flops F1 and F2 output the D input logic to the terminal Q at the falling edge of the CL terminal, F1Q = “H” at the rising edge of the signal a and F2−Q = “L” at the next falling edge. . These are the states D and E in FIG.

In state D, the inputs of the NAND gate G6 are all “H”, so the NAND gate G6 outputs the pulse 4-11 of “L” by the pulse width of the signal a. The output of the NAND gate G6 is connected to the CL terminals of the latches L0 to L7 of the Bv register 9. The Bv register 9 outputs the binary up counter 8 when the output 4-11 of the NAND gate G6 is "L". Latch ￣ Q _{0 to} ￣ Q ₇ .

As described above, the Bv register 9 latches the digital value corresponding to the in-finder brightness. The digital value is updated once every 15.625 ms as shown in Figure 5. In FIG. 5, 5-1 is a signal c, 5-2 is a signal b, 5-3 is an Aout voltage, 5-4 is a photoelectric conversion analog voltage, 5-5 is a comparator output, 5-6 is an output of the NAND gate G6. Is shown.

The value of the Bv register 9 is, for example, the value shown in D7 to D3 of Table 1, and the value on the left side of Table 1 is the decimal conversion value of the value of the Bv register 9, the larger the value, the larger the brightness in the finder. It corresponds to one.

[Table 1] The value of the Bv register 9 is input to the comparator unit 10-a, but its output logic is

[Equation 1] It is. Here, if G18 = “H” or G18 = “L”, the logical expression is

[Equation 2]

(Equation 3) Becomes The output logic is shown in Table 1.

The output from the NOR gate G14 of the comparator section 10-a is passed through the NAND gates G16 and G17 to the flip-flop formed by the NAND gates G18 and G19 when the signal b of the timing pulse generation circuit 2 is “L”. Latched. That is, the result of the comparator corresponding to the brightness in the viewfinder is latched every 15.625 ms. When the brightness in the finder is sufficiently large and the value of the Bv register 9 is 22 or more, G14 = "L" (G14 = "O") regardless of the output of the NAND gate G18 and the signal b = "L". When it becomes, G18 = "L" is confirmed.

A case where the value of the Bv register 9 changes from 22, 21 and 20 from this state will be described. When the value of the Bv register 9 is 21, G18 = "L" and G14 = "O" (G14 = "L") as shown in Table 1, the output of the NAND gate G18 is L even if the signal b becomes L. G18 = “L” remains unchanged.

Next, assuming that the value of the Bv register 9 becomes 20, the output of the NOR gate G14 becomes "H" regardless of the output of the NAND gate G18, so that when the signal b becomes "L", G18 = “H”. Further, when the value of the Bv register 9 changes to 20, 21, 22 as described above, when the value of the Bv register 9 is 20, when the signal b = "L", G14 = "1" (G14 = "" H ”), when the value of the Bv register 9 is 21, G14 =“ 1 ”(G14 =“ H ”), and when the value of the Bv register 9 is 22, G14 =“ 0 ”(G14 =“ L ”) and G = It becomes "L".

On the both sides of the brightness modulation level, the brightness of the finder screen changes from bright to dark when the value of the Bv register 9 changes to 22, 21, and 20, and the value of the Bv register 9 changes from 21 to 20. When it changes, the output of the NOR gate G14 changes from "L" to "H". When the brightness of the finder screen changes from dark to bright, it corresponds to when the value of the Bv register changes to 20, 21, and 22, and when the value of the Bv register 9 changes from 21 to 22, the NOR gate G14. Output changes from "H" to "L". Since the value difference 1 of the Bv register 9 corresponds to the finder luminance change 1Ev, the output of the NAND gate G18 is compared with the in-finder luminance value with a hysteresis width of 1Ev.

The display information register 11 receives a plurality of display data from the CPU 3 and stores it in memory. The output of the display information register 11 is switched by the signal f. When f = “H”, the display data of the light emitting diodes D1 to D4 is displayed, and when f = “L”, the display data of the light emitting diodes D5 to D8 is displayed. The signal is transmitted to the display information decoder circuit 12, decoded into display data, and outputs "H" when the light emitting diode is on and outputs "L" when it is off, to Si to Sn.

On the other hand, the output of the NAND gate G18, the signal e, and the signal f, which are input signals in the display circuit 13, correspond to 6-1, 6-3, and 6-2 in FIG. 6, respectively. The output logics of the AND gates G21, G22, and G23 at this time are shown in 6-4, 6-5, and 6-6. Here, when 6-5 (G22) is "H", a base current flows to the transistor QA through the resistor Ri and the transistor QA is turned on. At this time, the light emitting diodes D5 to D8 are selected. At the same time, the display data of the light emitting diodes D5 to D8 is output from the display information decoder circuit 12 by the signal f, and the display is performed by the light emitting diodes D5 to D8. Similarly, when 6-6 (G23) is "H", the transistor QB is turned on and the light emitting diodes D1 to D4 display.

Referring to 6-5 (G22) and 6-6 (G23) in FIG. 6, the light emitting diodes D1 to D4 and D5 to D8 are alternately selected and lighted. Further, when G18 = "H", the lighting time of the light emitting diode is 25% of the whole, and when G18 = "L", it is 50%. Therefore, the display of the light emitting diode is according to "H" and "L" of G18. When G18 = “H”, the brightness is dark, and when G18 = “L”, the brightness is bright and the brightness of the light emitting diode is set in two steps corresponding to the brightness in the viewfinder. The output of the NAND gate G18 has a hillteresis of 1Ev before and after the value of the Bv register 9 is 21 with respect to the change of the brightness in the finder, so the change point of the brightness of the light emitting diode also changes with a hysteresis. To do.

In the present embodiment, the luminance modulation has a hillteresis width of 1 Ev, but it does not have to be 1 Ev, and it is sufficient if the hillteryth width is such that the display does not flicker due to the luminance modulation. The brightness of brightness modulation has two levels, but it may be higher.

[0027]

[Effect of the invention]

 As described above, according to the present invention, various displays are performed by using a light emitting element such as an LED in the viewfinder of a camera, and the brightness of the light emitting element is changed stepwise by making the brightness of the display correspond to the brightness in the viewfinder. When the brightness in the viewfinder when using the method is near the change point of the brightness of the light emitting element, the brightness of the light emitting element changes drastically in response to a slight change in the brightness of the viewfinder screen and the display flickers. The problem of being difficult to see is solved, and a viewfinder display that is easy to see is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of the same embodiment.

FIG. 3 is a diagram showing waveforms of respective parts such as a clock and a D / A conversion circuit of the embodiment.

FIG. 4 is a diagram showing waveforms of respective parts such as a comparator and a timing pulse generation circuit of the embodiment.

FIG. 5 is a diagram showing waveforms of respective parts such as a D / A conversion circuit and a comparator of the same embodiment.

FIG. 6 is a diagram showing waveforms of respective parts such as a digital hysteresis comparator circuit and a display circuit of the same embodiment. 1 Oscillation Circuit 2 Timing Pulse Generation Circuit 3 CPU (Central Processing Unit) 4 Photoelectric Conversion Circuit 5 Comparator 6 Latch Pulse Circuit 7 Digital / Analog Conversion Circuit (D / A Conversion Circuit) 8 8-bit Binary Up Counter 9 Bv Register 10 Digital Hysteresis Comparator circuit 11 Display information register 12 Display information decoder circuit 13 Display circuit

Claims (2)

[Utility model registration claims] 1. A camera having at least two sets of display elements in a finder, and an in-viewfinder luminance measuring device for continuously measuring the in-finder luminance, and an in-finder luminance measured by the in-finder luminance measuring means. Comparing means for comparing with a predetermined value, and a display circuit for selectively lighting the plurality of sets of display elements with different brightness, and switching the set of display elements to be turned on according to the comparison result of the comparing means, The in-viewfinder display device of a camera, wherein the comparison means includes a comparator circuit that gives the predetermined value hysteresis. 2. The display device in a viewfinder of a camera according to claim 1, wherein the display elements are two sets, and the display circuit alternately lights the two sets of display elements.