JPH09212432A - Data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce error occurrence by selecting fetch data which is free of a parity error between 1st and 2nd latch data as effective data by checking the parity. SOLUTION: A data latch circuit 3 outputs a latch data signal 12 and a latch data parity signal 14 and inputs them to a parity check circuit 5. Further, a data latch circuit 4 outputs a latch data signal 13 and a latch data parity signal 15 to a parity check circuit 6. Then the parity check circuits 5 and 6 hold error information signals 16 and 17 at high level if detecting data errors as a result of their parity checks to inform a latch data selector circuit 7 of the data errors, and effective latch data between the latch data signals 12 and 13 is selected according to the error information signals 16 and 17. Therefore, error occurrence is reducible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system, and more particularly to a data transfer system on a bus in an information processing device.

[0002]

2. Description of the Related Art In data transfer, a technique for reducing data errors during the transfer is important. For example, in the data transfer method disclosed in Japanese Unexamined Patent Publication No. 5-173816, in addition to the conventional vertical and horizontal parity checks, a data bus for transferring data between a channel and an input / output device is used. By adding a redundant code for data error detection, the data error detection capability is improved and the data error detection can be performed even when there is a data error of a plurality of bits.

[0003]

The first problem is that the above-mentioned method can detect and correct a data failure of a plurality of bits, but data transfer including a redundant code for data error detection is also possible. In some cases, it is impossible to detect and correct a data error normally.

The reason is that the load capacity increases due to the increase in the number of agents on the bus and the extension of the bus line, and the timing margin cannot be secured, so that normal data cannot be guaranteed on the data receiving side.

The second problem is that the above-mentioned method increases the amount of hardware for detecting a data error.

The reason is that a dedicated circuit and a dedicated check circuit for generating the redundant code are required.

The present invention has been made in view of the above points, and in data transfer on a data bus, highly reliable data transfer is achieved by reducing the occurrence of errors due to failures caused by external factors. To aim.

[0008]

In order to achieve the above object, the present invention provides a clock doubling circuit for doubling a bus clock frequency, two systems of a data latch circuit and a parity check circuit, and a parity check. And a latch data selector circuit for selecting a data signal from the data latch circuit based on a check result by the circuit.

[0009]

Since the two latch timing signals output from the clock doubling circuit have different timings from each other, the timing of receiving data from the bus is different for each data latch circuit. The connected parity check circuit checks each data for an error (data error).
Therefore, even if an error is detected in one of the data latch circuits, if there is no error in the data of the other data latch circuit, it is regarded as valid data, and error-free data transfer is possible.

[0010]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a hardware configuration showing an embodiment of a data transfer system according to the present invention.

In this embodiment, a clock doubling circuit 2 that receives a bus clock 8 from a bus 1 and doubles its frequency, and a data latch that latches a data signal 9 and a data parity signal 10 from the bus 1 are used. Circuits 3 and 4
A parity check circuit 5 for inputting a latch data signal 12 and a latch parity signal 14 which are output signals from the data latch circuit 3 to perform a parity check; a latch data signal 13 which is an output signal from the data latch circuit 4; A parity check circuit 6 for inputting a latch parity signal 15 to perform a parity check, an error report signal 16 from the parity check circuit 5 and an error report signal 17 from the parity check circuit 6 are input to latch data signals 12 and 13. Of these, a latch data selector circuit 7 for selecting valid data.

Next, the operation will be described.

The clock doubling circuit 2 receives the bus clock 8 from the bus 1 and generates latch timing signals 18 and 19 synchronized with the bus clock 8. The latch timing signal 18 is connected to the data latch circuit 3, and the latch timing signal 19 is connected to the data latch circuit 4. Since the latch timing signals 18 and 19 have different timings, the data latch circuits 3 and 4 latch the data signal 9 and the data parity signal 10 on the bus 1 at different timings.

The data latch circuit 3 receives the latch data signal 1
2 and the latch data parity signal 14 are output to the parity check circuit 5. The parity check circuit 5 performs a parity check on the basis of the input latch data signal 12 and the latch data parity signal 14, and notifies the presence / absence of a data error by an error report signal 16. Similarly, the data latch circuit 4 outputs the latch data signal 13 and the latch data parity signal 15 and inputs them to the parity check circuit 6. The parity check circuit 6 performs a parity check on the basis of the input latch data signal 13 and latch data parity signal 15, and notifies the presence / absence of a data error by an error report signal 17.

The error report signals 16 and 17 are input to the latch data selector circuit 7, and the latch data signal 12 and the data latch circuit 4 which are outputs from the data latch circuit 3 are inputted.
The data having no data error in the latch data signal 13 output from is selected as valid data and output from the latch data selector circuit 7.

In this embodiment, the transfer system using the data signal 9, the data parity signal 10 and the data strobe signal 11 as the signals on the bus 1 as shown in FIG. 1 has been described, but the present invention is not limited to this. However, the present invention is not limited to this, and can be similarly applied to a transfer method using an address signal, an address parity signal, and an address strobe signal.

Further, the transfer system of the present invention can be similarly applied to the case where a parity signal is defined for a plurality of bus control signals. The bus control signal in this case indicates a write access instruction signal, a read access instruction signal, a memory access instruction signal, a burst access instruction signal, and the like.

[0019]

Next, an embodiment of the present invention will be described with reference to FIGS.

FIG. 2 is a time chart showing the timing of each signal in this embodiment.

Referring to FIGS. 1 and 2, in the present embodiment, a data strobe signal 11 which indicates that the data signal 9 and the data parity signal 10 are valid is operated by the bus clock 8 having a bus duty of 50%. It changes in synchronization with the rising edge of the bus clock 8. The data strobe signal 11 indicates that the data signal 9 and the data parity signal 10 are valid when it is at a low level. The data signal 9, the data parity signal 10 and the data strobe signal 11 change with a slight delay with respect to the rising edge of the bus clock 8. Further, in the clock doubling circuit 2, a PLL circuit is used to generate a double clock 20 having a frequency twice that of the bus clock 8.
(See FIG. 2).

The data latch circuits 3 and 4 are latch circuits that hold input data at the rising edges of the data latch timing signals 18 and 19.

The parity check circuits 5 and 6 notify the latch data selector circuit 7 of a data error by setting the error report signals 16 and 17 to a high level when a data error is detected as a result of the parity check. .

The latch data selector circuit 7 receives the latch data signal 12,
Valid latch data out of 13 is selected. If both the error report signals 16 and 17 are at the low level and there is no data error, either one may be selected, but here,
For example, the latch data signal 13 is selected.

Next, the operation of this embodiment will be described.

The clock doubling circuit 2 generates a double clock 20 having a frequency twice that of the clock 8 by an internal PLL circuit, and a data strobe signal 11 indicating that the data signal 9 and the data parity signal 10 are valid. And doubled clock 20 from latch timing signals 18 and 1
9 is output.

The latch timing signal 18 is a signal synchronized with the falling edge of the bus clock 8, and the latch timing signal 19 is a signal synchronized with the rising edge of the bus clock 8. That is, for example, the latch timing signal 18 is synchronized with the odd-numbered rising edges of the double clock 20, and the latch timing signal 19 is synchronized with the even-numbered rising edges of the double clock 20.

The latch timing signal 18 is input to the data latch circuit 3, and the data latch circuit 3 latches the data signal 9 and the data parity signal 10 of the bus 1 at the rising edge of the latch timing signal 18.

On the other hand, the latch timing signal 19 is input to the data latch circuit 4, and the data latch circuit 4 latches the data signal 9 and the data parity signal 10 of the bus 1 at the rising edge of the latch timing signal 19.

Since the latch timing signal 18 and the latch timing signal 19 have different timings, the data latch circuit 3 and the data latch circuit 4 have different timings for the data signal 9 and the data parity signal 10 on the bus 1. It will be latched. For this reason,
Even when the load capacity increases due to the increase in the number of agents on the bus or the extension of the bus line and the timing margin cannot be secured, at least one of the data latch circuit 3 and the data latch circuit 4 correctly latches the data. can do.

The data latch circuit 3 outputs the latch data signal 12 and the latch data parity signal 14 and inputs them to the parity check circuit 5. Parity check circuit 5
Performs a parity check using the input latch data signal 12 and latch data parity signal 14, and if there is a data error, sets the error report signal 16 to the low level to notify the occurrence of the error.

Similarly, the data latch circuit 4 outputs the latch data signal 13 and the latch data parity signal 15 and inputs them to the parity check circuit 6. The parity check circuit 6 performs a parity check using the input latch data signal 13 and latch data parity signal 15, and if there is a data error, sets the error report signal 17 to the low level to notify the occurrence of the error.

The error report signals 16 and 17 are input to the latch data selector circuit 7, and in the latch data selector circuit 7, the latch data signal 12 which is the output from the data latch circuit 3 and the latch which is the output from the data latch circuit 4. The data of the data signal 13 for which no data error has been reported is determined as valid data and output.

FIG. 2 shows a case where a data error occurs in the latch data signal 13 latched by the data latch circuit 4 because the rear end of the data signal 9 is not guaranteed on the bus 1. A high level 17 indicates a data error. On the other hand, error report signal 1
6 becomes a low level, which notifies that the latch data signal 12 latched by the data latch circuit 3 has no data error. Therefore, the latch data selector circuit 7
Latch data signal 12 latched by the data latch circuit 3
Is output as valid data.

[0035]

The first effect is that normal data can be transferred even if the timing margin cannot be secured because the load capacity increases due to an increase in the number of agents on the bus or extension of the bus line.

The reason is that by latching the data on the bus twice at different timings, even if there is a transfer error in either of the latched data, the other valid data can be used. Because.

The second effect is that the amount of hardware is small.

The reason is that the data transmitting side on the bus does not require any special hardware such as generating a redundant code, and the check circuit on the receiving side is duplicated.

The third effect is that the existing bus can be mixed.

The reason for this is that in the data transfer system according to the present invention, the only change from the prior art is the receiving side, and no change is made to the data transfer sequence on the bus.

[Brief description of drawings]

FIG. 1 is a block diagram of a hardware configuration showing an embodiment of a data transfer system according to the present invention.

FIG. 2 is a time chart showing the timing of each signal in the present embodiment.

[Explanation of symbols]

 1 bus 2 clock doubling circuit 3, 4 data latch circuit 5, 6 parity check circuit 7 latch data selector circuit 8 bus clock 9 data signal 10 data parity signal 11 data strobe signal 12, 13 latch data signal 14, 15 latch data parity Signal 16 and 17 Error report signal 18 and 19 Latch timing signal 20 Double clock

Claims (3)

[Claims] 1. A data transfer system for transferring data having parity from a transmission side to a reception side via a bus, wherein the reception side doubles a bus clock on the bus to generate a double clock. Generating a first data latch timing signal synchronized with an odd-numbered rising edge of the double clock and generating a second data latch timing signal synchronized with an even-numbered rising edge of the double clock; The data having the parity is latched from the bus at the timing of the first data latch timing signal to be the first latched data, and the data having the parity is latched from the bus at the timing of the second data latch timing signal. The second latch data and the first latch data and the second latch data.
Of the first latch data and the second latch data, and selects one of the first latch data and the second latch data having no parity error as a result of the parity check as valid data. method. 2. The data transfer system according to claim 1, wherein the data having the parity is address data. 3. The data transfer system according to claim 1, wherein the data having the parity is a bus control signal.