JPH09213009A - Playback device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To stably generate a clock without being affected by temperature changes, changes over time, and the like, and to always realize good equalization characteristics. A reproducing apparatus includes an equalizer for equalizing reproduced data, an oscillator for generating a clock, and a phase difference detector for detecting a phase difference between an output clock of the oscillator and the reproduced data. Frequency detection means for detecting an error between the frequency of the output clock of the oscillation means and a predetermined frequency; equalization control means for controlling the equalization characteristic of the equalization means using the output of the frequency detection means; It comprises an oscillation control means for controlling the oscillation operation of the oscillation means using the output of the phase detection means and the output of the frequency detection means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus and method, and more particularly to reproducing a digital signal.

[0002]

2. Description of the Related Art Conventionally, in a device for transmitting (recording / reproducing) high-speed data such as a digital VTR, when a clock is extracted from a received data string, a phase-locked loop (hereinafter It is known to use a PLL).

In FIG. 14, the phase comparison circuit 501 detects the phase difference between the reproduced data and the clock, and the signal showing the phase error between them is filtered by the LPF 502 and output to the VCO 503. The VCO 503 generates a clock having a frequency corresponding to the voltage of the control signal. The frequency divider 504 divides the clock and divides the clock by the phase comparison circuit 5
Return to 01.

[0004]

However, in the above-mentioned device, since the PLL circuit for generating the clock is composed entirely of analog circuits, the circuit changes due to changes in the surrounding environment such as temperature changes and aging changes. The characteristics of are likely to change, and the clock generation operation becomes unstable.

Further, in the digital VTR, it is required to realize special reproduction functions such as fast-forwarding and slow reproduction like the analog VTR. In such special reproduction, the relative speed between the head and the tape. Changes, and the frequency of the reproduction signal changes accordingly.

Therefore, when the fluctuation of the frequency of the reproduced signal becomes large, the frequency of the reproduced signal deviates from the lock range of the PLL, and the clock cannot be obtained.

Further, in the digital VTR as described above, an equalizer for equalizing the waveform of the reproduction signal is used in order to obtain better data, but the equalization characteristic of the equalizer is the optimum signal waveform during normal reproduction. If the characteristics are set so that they become fixed, the frequency of the playback signal will change during special playback as described above, so the characteristics will not be optimal during special playback, and errors in the playback data will occur. And the reproduced image quality deteriorates.

An object of the present invention is to solve the above-mentioned problems.

Another object of the present application is to stably generate a clock without being affected by temperature changes, changes over time, and the like.
The objective is to always achieve good equalization characteristics.

[0010]

SUMMARY OF THE INVENTION In order to solve the conventional problems and achieve the above object, the present invention comprises an equalizing means for equalizing reproduced data, an oscillating means for generating a clock,
Phase difference detecting means for detecting a phase difference between the output clock of the oscillating means and the reproduced data, frequency detecting means for detecting an error between the frequency of the output clock of the oscillating means and a predetermined frequency, and the frequency detecting means. Equalization control means for controlling the equalization characteristic of the equalization means by using the output of the same, and an oscillation control for controlling the oscillation operation of the oscillation means by using the output of the phase detection means and the output of the frequency detection means. And means.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In this embodiment, the present invention is applied to a digital VTR.
The case of application to is explained. FIG. 1 is a block diagram showing the structure of a reproducing system of such a digital VTR.

In FIG. 1, a signal reproduced from the magnetic tape T by the magnetic head 101 is a head amplifier 103.
Is amplified by and output to the equalizer 105.

In the digital VTR according to the present embodiment, one frame of video signal is recorded on ten helical tracks formed on the tape T, but needless to say, other signals may be recorded.

The equalizer 105 performs so-called integral equalization processing on the reproduced signal. Then, the equalized reproduction signal is output to a VCA (Variable Cntrol Amplifier) 107 and amplified. The VCA 107 is an amplifier whose gain can be controlled, and the gain is controlled by a control signal from the D / A converter 133 as described later.

On the other hand, an adder 117 adds control signals output from the D / A converters 115 and 117 and outputs the added signals to the VCO 119 as described later.

The VCO 119 generates a clock having a frequency corresponding to the voltage of the control signal from the adder 117 and outputs it to the multiplication circuit 121. The multiplication circuit 121 doubles the frequency of the clock from the VCO 119.

In FIG. 1, a portion surrounded by a broken line is composed of a digital circuit and operates with a clock from the multiplication circuit 121 except for the D / A converter 117. The other parts are analog circuits and are configured on the same integrated circuit.

The operation of the digital circuit indicated by the broken line will be described below.

The reproduced signal whose amplitude is controlled by the VCA 107 as described above is sampled by the A / D converter 109 and is converted into a digital signal of one sample plural bits (5 bits in this embodiment).

Here, the signal recorded on the tape T is of course a digital signal, but the reproduction signal is a signal having an analog waveform. Here, the reproduced signal having the analog waveform is A / D-converted to be converted into a signal having a digital waveform again.

The reproduced signal output from the A / D converter 109 is the phase / amplitude detection circuit 111 and the PR4 equalizer 1.
23 and the ATF circuit 139.

Reference numeral 123 denotes a PR4 equalizer, which is a subtractor 12
5, the data output from the A / D converter 109 is subjected to a subtraction process with the data delayed by the latch 123a two clocks before, and PR4 (Partial R
The output signal is given to the Viterbi decoder 135 by giving the characteristics of the response class 4). The Viterbi decoder 135 uses the well-known Viterbi detection method, detects 1-sample 1-bit data from the reproduced data based on the likelihood of the input ternary data, and outputs it to the decoder 137. Decoder 137
Reproduces the reproduction data from the Viterbi decoder 135 and expands the information amount thereof to convert it into the original video signal.

The ATF circuit 139 extracts the pilot signal component in the reproduced data output from the A / D converter 109. Then, based on this pilot signal component, an error signal indicating the tracking deviation between the head 101 and each helical track of the tape T is generated, and the tracking deviation is corrected by controlling the tape drive system that carries the tape. Regarding this ATF circuit, Japanese Patent Application No. 6-2
It is possible to use the one disclosed in 77832.

Further, the phase / amplitude detection circuit 111 detects the phase difference between the reproduction signal output from the equalizer 105 and the clock from the multiplication circuit 121, and the sampling point in the A / D converter 109 (from the multiplication circuit 121). VCA10 at output clock timing)
The amplitude of the output signal from 7 is detected. Then, the phase detection output is output to the loop filter 113, and
The amplitude detection output is output to the subtractor 127.

Now, the phase / amplitude detection circuit 111 will be described.

FIG. 2 is a block diagram showing the configuration of the phase / amplitude detection circuit 111.

In FIG. 2, 203 to 209 are delay circuits for delaying the digital signal output from the A / D converter 109 for each clock, and 215 are data from the input terminal 201 and outputs from the delay circuits 203 to 209. It is a decoder including a logical operation circuit that detects a specific pattern.

Further, 213 is a sign inverting circuit for inverting the output of the subtractor 211, 217 and 219 are switches for switching between the input and output of the sign inverting circuit 213 and outputting, and 221 is the decoder 215 for the output of the switch 217.
A latch circuit 225 which samples and holds with the signal ph output from the output and outputs as a phase detection output is a switch 2
It is a latch circuit that samples and holds the output of 19 with the signal ah output from the decoder 215 and outputs it as an amplitude detection output.

In such a configuration, the reproduced signal that has been A / D converted is input to 201, and each of the delay circuits 203 to 2
It is sequentially delayed by 09. The outputs of the delay circuits 203 and 207 are output to the subtractor 211, which outputs PR4 signals.

Here, input data and each delay circuit 203
The MSBs of the 5-bit output data of ~ 209 are a, b, c,
d and e. Further, when the reproduction signal is A / D converted, if the average value of the reproduction signal is set to be in the center of the A / D conversion range, a, b, c, d, and e are integrated with the reproduction data. It is binarized and becomes binary data. This data string is input to the decoder 415, a specific pattern is detected by a logical operation described later, and signals s, ph and ah are obtained.

The signal s controls the switch 217 to selectively output the output of the subtracter 211 and the signal obtained by inverting the sign of this output by the sign inverting circuit 213. Further, by supplying the signal ph to the terminal E of the latch circuit 221, the latch circuit 223 is controlled and the output of the switch 417 is changed to the signal ph.
Sample hold at the timing of.

First, the phase detection operation by the signals s and ph will be described.

FIG. 3 is a diagram showing an eye pattern of a signal subjected to PR4 equalization. This eye pattern takes three values at the data detection point. Looking at the zero-cross point of this eye pattern, it can be seen that the signal passing through the zero-cross point has a slope proportional to the phase difference between the data and the detection point.

However, this slope has both positive and negative values. Therefore, the decoder 215 detects the specific pattern in the reproduced signal by determining whether the signal s is positive or negative, and performing a predetermined logical operation so as to determine that the signal ph is at the zero cross point. Therefore, the phase detection output 223 has a value whose average level is proportional to the phase difference between the data detection point and the clock.

As a method of obtaining the signals s and ph as described above, in this embodiment, a specific pattern is detected from the reproduced data by a logical operation and the signals s and ph are output.
FIG. 4 shows an example of a truth table of the signals s and ph.

In FIG. 4, bd, that is, the output of the subtracter 411 and the logics of the signals s and ph with respect to the reproduction data abcde are shown. s is positive or negative of bd, ph is b
-D indicates whether it is a zero-cross point, that is, whether data of a specific pattern has been input. From this truth table, it can be seen that the signals s and ph can be represented by a simple logical operation. For example,

[0038]

[Outside 1] Can be expressed as

This logic is based on the data abc which is integrated and equalized.
This is true when there is no error in de. As the phase of the data and the clock deviates, a value proportional to the deviation amount is detected as the detection output 223. As a result, the A / D converter 109 also performs sampling at an incorrect timing, but as will be described later, the detection output 223 is output to the VCO 119 via the loop filter 113 so that the clock is synchronized with the reproduction signal. Become.

Next, the amplitude detection operation will be described.

The PR4 data output from the subtracter 211 in FIG. 2 has the eye pattern shown in FIG. 3 as described above. Of the three values at the data detection point, the two values other than the zero-cross point indicate the amplitude of the reproduction data.

In this embodiment, the decoder 215 detects a specific pattern, and when the output of the subtractor 211 is other than the zero-cross point, the sample-hold is performed to accurately detect the amplitude of the reproduction data at the detection point.

Here, in order to detect that the output of the subtractor 211 is other than the zero-cross point, the same method as described in the above-mentioned phase detection operation may be used. That is,
The decoder 215 detects a specific pattern when the output of the subtractor 211 is other than the zero-cross point, and outputs the signal ah to the latch circuit 225. The latch circuit 225 latches and outputs the output data from the switch 219 at the timing when the signal ah is input.

FIG. 4 shows the logic of the signal ah as ah.
The latch circuit 225 operates at the timing when ah is 0.
MS of output of delay circuit 203 and output of delay circuit 207
If B is b and d,

[0045]

[Outside 2] You can see that

The switch 219 is switched by PR
Although it is possible to use the code (MSB) of 4 data (data in the center of b-d in FIG. 2), it is understood from the sign of FIG. 4 that inverted data of d or b may be used.

As described above, in this embodiment, since the phase detection output is directly obtained by the digital circuit from the A / D converted data, the clock phase automatically follows the data sampling point. However, the data can be accurately detected.

Since the specific pattern in the case where the PR4 data represents the amplitude is detected from the reproduced data and the PR4 data is sampled and held based on the detected output, the amplitude of the reproduced signal is detected. , When the phase is accurately maintained, that is, when the PLL is locked, it is possible to faithfully detect the amplitude value of the sampling point instead of the envelope of the reproduction signal.

That is, when reproducing data is detected from PR4 data as described later, the amplitude at the data detection point can be accurately detected.

In this way, the amplitude detection output detected by the phase / amplitude detection circuit 111 is output to the subtractor 127. A register 129 is provided at the other terminal of the subtractor 127.
The target value of the amplitude is given from, and the subtraction result is output to the loop filter 131 as an amplitude error. The loop filter 131 averages the amplitude error data and outputs it to the D / A converter 133. The D / A converter 133 converts the amplitude error data into an analog value and feeds it back to the VCA 107 to control the gain of the VCA 107.

The phase detection output detected by the phase / detection circuit 111 is output to the loop filter 113.

The loop filter 113 is a circuit for performing PLL and AFC operations based on the phase detection output, and its configuration is shown in FIG.

First, the PLL operation will be described. FIG.
In 311, the phase detection output from the phase / amplitude detection circuit 111 is input to 311 and the clock from the multiplication circuit 121 is supplied to 317. The phase detection output input from 301 is filtered by the loop filter 303, and output from the terminal 305 to the D / A converter 115. The D / A converter 115 converts the phase detection output into an analog signal and outputs it to the VCO 119 via the adder 117 to control the clock frequency. In this way, the phase / amplitude detection circuit 111 to the loop filter 1
A feedback loop composed of 13-adder 117-VCO 119-multiplier circuit 121 constitutes a basic PLL loop for generating a clock synchronized with the reproduced data.

Next, the operation of so-called AFC, in which the PLL loop is always kept at the center of the lock range and the oscillation frequency is automatically controlled to follow changes in temperature, changes over time, etc., will be described.

The output of the loop filter 303 is the LPF 30.
7 is output. The LPF 307 averages the input data by integrating it during a period in which the head traces one track (hereinafter referred to as Ttr), and outputs the average value to the register 309. The register 309 stores the data from the LPF 307 in FIG.
It holds at the timing of Ttr shown in (b), and outputs the result to the positive input terminal of the subtractor 311.

Here, the signal indicating Ttr is obtained by the timing signal forming circuit 141 in FIG. In FIG. 1, a timing signal forming circuit 141 forms a timing signal indicating Ttr based on a PG signal obtained by a PG head that detects the rotation phase of a rotary drum (not shown), and outputs this. In FIG. 6, (a) shows the head 1.
Shows the envelope of the signal reproduced by 01,
(B) shows the state of the timing signal output from the timing signal forming circuit 141.

The clock output from the multiplication circuit 121 is input to the counter 319. Counter 319
Counts the number of clocks supplied during the Ttr period,
The result is output to the positive input terminal of the subtractor 321. The subtractor 321 detects the error between the target frequency and the clock frequency by obtaining the difference between the target value set in the register 323 and the count value of the counter 319, and outputs the result to the coefficient unit 325.

Therefore, if the target frequency for the register 323 is Fcent, then Fcent × Ttr
By setting this value, the error between the target frequency and the clock frequency can be obtained as the output of the subtractor 321.

The level of the frequency error signal output from the subtractor 321 is adjusted by the coefficient unit 325 and output to the negative input terminal of the subtractor 311. Subtractor 311 is register 2
09 output to subtract the output of the coefficient multiplier 325 to obtain an integrator 3
13 is output.

The integrator 313 is constructed as shown in FIG. 7, and the adder 401 inputs the input data and the register 40 while the integrated value is within a predetermined limit range.
It operates so as to add and integrate the data of 5.
Further, the limiter 403 restricts the integrated value from exceeding the limit value. The register 405 is similar to the register 309 described above in the timing signal forming circuit 1.
The signal indicating the Ttr period from 41 is supplied, and 1
Hold the integrated value once for the track.

The output of the integrator 313 is output to the D / A converter 117 via the terminal 315, and the D / A converter 117 converts this integrated value into an analog signal and outputs it to the adder 117 and the equalizer 105. .

Thus, in this embodiment, for example,
When the oscillation frequency of the VCO 119 tries to decrease due to some external factor, the frequency of the clock supplied to the phase / amplitude detection circuit 111 via the multiplication circuit 121 also decreases, and the phase / amplitude detection circuit 111 outputs a signal indicating a phase difference. can get. In response to this, the voltage of the control signal output from the D / A converter 115 fluctuates, the oscillation frequency of the VCO 119 is increased, and the clock frequency follows the fluctuation.

However, when the clock frequency is also changed in accordance with the phase fluctuation as described above, the output data of the loop filter 303 is also increased (decreased) and deviates from the center of the lock range of the PLL. It's gone. Therefore, even if an attempt is made to correct the phase error between the reproduced data and the clock from such a state, the VCO 119 becomes difficult to follow, and the PLL loop is easily deviated with respect to the phase fluctuation.

Therefore, in this embodiment, the LPF 30 is used.
7-register 309-integrator 313-D / A converter 11
7 to the pass of the adder 117, the loop filter 303
The deviation of the output data of is detected, integrated, and added by the adder 117 with the output of the D / A converter 115,
The output data of the loop filter 303 can be biased to the integrator 313 with a time constant slower than that of the PLL loop described above, and the output data of the loop filter 303 is always kept near the center of the PLL lock range. It becomes possible to do.

Next, the control of the equalization characteristic of the equalizer in this embodiment will be described.

FIG. 8 is a block diagram showing the structure of the equalizer 105. In FIG. 8, R ₁ , R ₂ , R ₃ , L ₁
And amplifier 1 for primary filter 1, R ₄ , L ₂ , C ₂ and amplifier for secondary filter 2, R ₅ , L ₃ , C ₃ and amplifier 3
To form a quadratic filter 3, and these three filters form an equalizer.

FIG. 9 is a diagram showing the structure of the VCO 119. In FIG. 9, VC is set by L ₄ , C ₄ and the amplifier 4.
A secondary filter 4 that determines the oscillation frequency of O is configured,
The oscillation output is obtained by feeding back the output of this filter to the current source.

Next, the operation will be described. In the present embodiment, the gyrator as similar circuit form on an integrated circuit, L, which is the equivalent inductor using gyrator made of mask construction _{1, L 2, L 3,} L 4 is substantially the same inductance A load capacitor C ₀ (Fig. 1
(Shown in 0) are equally selected.

FIG. 10 is a diagram showing a configuration example of a gyrator as an equivalent inductor.

In FIG. 10, the relationship between the current i ₁ flowing between the terminals A and A ′ and the voltage V ₁ between both terminals is given by the following equation.

V ₁ = jωC ₀ · R ₀₁ · R ₀₂ · (I ₃ / I ₁ ) · I ₁ where I ₁ and I ₃ are direct currents, and i ₁ is alternating current

From this, L = C ₀ · R ₀₁ · R ₀₂ · (I ₃ / I ₁ ) and the inductor can be realized on the integrated circuit by using R and C. Then, if I ₃ is fixed and I ₁ is varied, the L value can be changed.

Now, regarding the frequency characteristics of each of the filter 1, the filter 2, and the filter 3, when the gyrator and the reference current are the central values, the cutoff frequency, Q, as shown in FIGS. 11 (a), (b), and (c), The resistor and capacitor values are selected so that

Here, the transmission band of the reproduction equalizer is about 1/2 of the signal transmission speed (reproduction clock frequency) fb that satisfies the Nyquist criterion known as signal transmission theory.

On the other hand, the frequency characteristic of the filter 4 which determines the oscillation frequency of the VCO 119 has a sharp peak at fb / 2 as shown in FIG. 12 when the reference current of the gyrator is at the center value, so that it is centered at fb / 2. It turns out that it oscillates as a frequency.

Next, the case where the digital VTR is normally reproduced will be described.

When the reproducing operation is started, first, the above-mentioned AF
The frequency of the clock is adjusted to the frequency of the reproduced data by the C loop and put in the lock range of the PLL. After that, the phase / amplitude detection circuit 111 detects the phase difference between the reproduction data equalized by the equalizer output 105 and the clock, and outputs the phase detection signal to the loop filter 113, D / A.
Since negative feedback is performed to the VCO 119 via the converter 115 and the adder 117, the oscillation frequency of the VCO 119 determined by the cutoff frequency of the filter 4 is automatically adjusted to fb / 2.

If the values of the capacitors (C ₃ and C ₄ ) used in the filters 3 and 4 are the same, the cutoff frequency of the filter 3 including the stray capacitance of the gyrator is always fb / 2. Capacitor (C ₂ ) handled by filter 2 with reference to this filter 3
Can be easily obtained.

In the present embodiment, the equivalent inductances of the gyrators formed in the same circuit form by the filter forming the equalizer and the filter forming the VCO are used, and these gyrators are controlled by the same reference current for controlling the VCO 119. Since the cut-off frequency is controlled by the cutoff frequency, the equalization characteristic of the equalizer can be automatically controlled according to the fluctuation of the clock.

Further, as described above, the frequency of the reproduction signal changes during the special reproduction, but in the present embodiment, the VCO 119 is changed by changing the set value of the register 223.
It is possible to move the frequency of the output clock of the multiplication circuit 121 to the vicinity of the frequency of the reproduction signal by changing the oscillation frequency of. Then, if the loop of the PLL follows this in this state, the integrator 213 absorbs the bias of the phase detection output so that the output of the loop filter 203 becomes near the center of the lock range. At this time, the characteristic of the equalizer 105 is controlled by the output of the D / A converter 117 that determines the center frequency of the VCO 119, so that the equalizer characteristic of the equalizer difference is changed according to the frequency fluctuation of the reproduction signal as shown in FIG. Can be automatically controlled so as to have an optimum equalization characteristic.

Further, in this embodiment, the VCO 119 is controlled by the addition output of the D / A converters 115 and 117, but the equalizer 105 is controlled only by the output of the D / A converter 117. It is carried out.

The frequency of the signal output from the D / A converter 115 is usually several kHz, and if this signal is supplied to the gyrator of the equalizer 105 as it is, noise may be mixed in the reproduced data.

Therefore, in this embodiment, the D / A converter 117 having a relatively low frequency (the frequency of the signal indicating the Ttr period output from the timing signal forming circuit 141 is 300 Hz because it is 10 tracks per frame). By controlling the equalizer 105 gyrator with the output signal, such noise mixing is prevented.

As described above, in the present embodiment, V
The CO and the equalizer are integrated on the same integrated circuit by using a gyrator having the same circuit type and mask structure,
The equalizer is controlled by the signal obtained by integrating the phase detection output, and VC is obtained by the output obtained by adding the phase detection output and the integration output.
O is controlled.

Therefore, it is possible to always keep the loop of the PLL at the center of the lock range and to compensate the fluctuation of the clock due to the temperature change, the time change and the like.

Further, the characteristics of the equalizer are controlled by the AFC loop, and the VC is controlled by the AFC loop and the PLL loop.
Since O is controlled, the equalization characteristic of the equalizer can be controlled by making the frequency of the clock follow the fluctuation of the frequency of the reproduction signal, and further, the equalizer and VCO can be controlled.
It is possible to absorb the variation due to the temperature and lot of the analog integrated circuit in which the and are integrated and always optimize the equalization characteristics.

The LPF 307 to the integrator 313 and the counter 319 to the coefficient unit 325 shown in FIG. 5 can achieve the same functions with a microcomputer.

Further, in FIG. 1, the D / A converter 11
5 and 117, the outputs of the loop filter 303 and the integrator 313 in FIG. 3 were converted into analog signals and then added, but the adder 117 is a digital adder and the outputs of the loop filter 303 and the integrator 313 are A configuration is also possible in which the respective signals are added in the state of digital signals, converted into analog signals and output to the VCO 119.

Although the characteristics of the equalizer are controlled by oscillating the VCO 119 at a desired frequency, other circuits can be controlled as long as they are constructed on the same integrated circuit in the same circuit form. .

Further, although the case where the present invention is applied to the digital VTR has been described in the above-mentioned embodiment, the present invention is not limited to this, and a system for transmitting / recording / reproducing a digital signal, for example, an electric wave or optical It is also applicable to communication by means of the like, optical disks, etc., and has the same operation and effect.

[0091]

As is apparent from the above description, in the present invention, the equalization characteristic is controlled by using the frequency error between the reproduced data and the clock, and the frequency error and the phase error between the reproduced data and the clock are controlled. Since the oscillation operation is controlled by using, the equalization characteristic can be optimally controlled according to the fluctuation of the clock.

In another invention of the present application, the equalization characteristic is controlled by using the detection result of the tendency of the phase difference between the reproduced data and the clock, and the tendency and the phase error between the reproduced data and the clock are used. Since the oscillation operation is controlled by
The equalization characteristic can be controlled according to the fluctuation of the clock.

Furthermore, since the response speed of the equalization characteristic control can be made slower than the response speed of the oscillation operation control, it becomes possible to prevent noise from being mixed into the reproduced data.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital VTR as an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a phase / amplitude detection circuit in FIG.

FIG. 3 is a diagram for explaining the operation of the circuit of FIG.

FIG. 4 is a diagram for explaining the operation of the circuit of FIG. 2;

5 is a block diagram showing a configuration of a loop filter in FIG.

FIG. 6 is a diagram for explaining the operation of the circuit of FIG.

7 is a diagram showing a configuration of an integrator in the circuit of FIG.

FIG. 8 is a diagram showing a configuration of the equalizer in FIG.

9 is a diagram showing a configuration of a VCO in FIG.

10 is a diagram showing a configuration of a gyrator as an equivalent inductor in FIGS. 8 and 9. FIG.

FIG. 11 is a diagram showing characteristics of the circuit of FIG.

FIG. 12 is a diagram showing characteristics of the circuit of FIG. 9.

13 is a diagram showing characteristics of the circuit of FIG.

FIG. 14 is a diagram showing a configuration of a conventional PLL circuit.

[Explanation of symbols]

 105 Equalizer 111 Phase / amplitude detection circuit 113 Loop filter 119 VCO

Claims (16)

[Claims] 1. An equalizing means for equalizing reproduced data, an oscillating means for generating a clock, a phase difference detecting means for detecting a phase difference between an output clock of the oscillating means and the reproduced data, and the oscillating means. Frequency detecting means for detecting an error between the frequency of the output clock and a predetermined frequency, equalizing control means for controlling the equalizing characteristic of the equalizing means using the output of the frequency detecting means, and the phase detecting means. And an oscillation control means for controlling the oscillating operation of the oscillating means by using the output of the above and the output of the frequency detecting means. 2. The equalization control means, counting means for counting the output clock of the oscillating means, holding means for holding a comparison value according to the predetermined frequency, output of the counting means and the comparison value. The reproduction apparatus according to claim 1, further comprising: an error detection unit that obtains a difference between the error detection unit and the error detection unit, and the equalization characteristic is controlled by using an output of the error detection unit. 3. The equalization control means further has an integration means for integrating the output of the error detection means, and controls the equalization characteristic using the output of the integration detection means. Item 2. The reproducing device according to item 2. 4. A reproducing means for reproducing the reproduction data from a recording medium, wherein the comparison value is a value corresponding to a frequency of the reproduction data reproduced from the recording medium.
A playback device according to claim 1. 5. A conversion means for sampling the data output from the equalization means in accordance with the clock and outputting digital data of one sample multi-bit, the phase detection means and the frequency detection means, respectively. The reproducing apparatus according to claim 1, wherein the phase difference and the frequency error are output as digital data. 6. A first D / which converts the digital data output from the phase difference detecting means into analog data.
A conversion means, second D / A conversion means for converting the digital data output from the frequency detection means into analog data, output data from the first D / A conversion means, and the second
6. The adding means for adding the output data from the D / A converting means of the above, and the oscillation control means controls the oscillation operation by using the output of the adding means. Playback device. 7. The equalizing means and the oscillating means are configured by using filters of the same circuit type, and the equalizing control means and the oscillation controlling means are equivalent to the filter of the equalizing means and the oscillating means. The reproducing apparatus according to claim 1, wherein the characteristic is controlled. 8. A conversion means for sampling the data output from the equalization means in accordance with the clock and converting the data into digital data, wherein the phase detection means includes a specific pattern in the digital data from the conversion means. A pattern detecting means for detecting the phase difference, an extracting means for extracting a part of the digital data at a timing according to the output of the pattern detecting means, and a means for detecting the phase difference according to the output of the extracting means The reproducing apparatus according to claim 1, wherein 9. A clock generation means for generating a clock synchronized with the reproduction data equalized by an equalizer, and a first control means for controlling the clock generation means based on a phase difference between the reproduction data and the clock. A reproducing apparatus comprising: second control means for controlling the equalizer based on a frequency error between the frequency of the clock and a desired frequency. 10. An equalizing means for equalizing reproduced data, an oscillating means for generating a clock, a phase difference detecting means for detecting a phase difference between an output clock of the oscillating means and the reproduced data, and the phase difference. Detection means for detecting the tendency of the output of the detection means, first control means for controlling the equalization characteristic of the equalization means using the output of the detection means, output of the phase difference detection means and the detection means And a second control means for controlling the oscillation operation of the oscillation means by using. 11. A loop filter for inputting the output of the phase difference detecting means, the detecting means averaging means for averaging the output of the loop filter, and latch means for latching the output of the averaging means. 11. The reproducing apparatus according to claim 10, further comprising: and an integrating unit that integrates an output of the latching unit, wherein the first control unit controls the equalization characteristic by using an output of the integrating unit. apparatus. 12. A conversion means for sampling the reproduction data equalized by the equalization means according to the clock and converting it to digital data, wherein the phase difference detection means outputs the phase difference as digital data. The reproducing apparatus according to claim 11, wherein the reproducing apparatus is a reproducing apparatus. 13. The integration means outputs the integration result as digital data, and the detection means further includes first D / A conversion means for converting the digital data output from the integration means into analog data. 13. The reproducing apparatus according to claim 12, further comprising: the first control unit controls the equalization characteristic by using an output of the D / A conversion unit. 14. A second D / A conversion means for converting output digital data from the loop filter into analog data, wherein the second control means outputs the output of the first D / A conversion means. 14. The reproducing apparatus according to claim 13, further comprising adding means for adding the output of the second D / A converting means, and controlling the oscillation operation using the output of the adding means. 15. An equalizer for equalizing reproduced data, a generator for generating a clock, a phase difference detector for detecting a phase difference between the reproduced data and the clock, and a high frequency for the phase difference detector. A reproducing apparatus comprising: first control means for controlling the generating means using a component and a low frequency component; and first control means for controlling the equalizing means using the low frequency component of the phase difference detecting means. 16. The first control means has an integration means for integrating the output of the loop filter, and the second control means adds the output of the loop filter and the output of the integration means. The reproducing apparatus according to claim 15, further comprising: