JPH09213906A - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

Kind Code: A1 Abstract: Even if a DRAM memory cell is miniaturized, a defective shape of a tunnel-shaped storage electrode does not occur. A sidewall of a first line pattern is formed, and at the same time, the first line patterns are separated in a self-aligned manner, and then a photoresist 43 of a second line pattern intersecting the first line pattern is formed. The polycrystalline silicon films 12 and 42 are removed as a mask. Then, the silicon oxide film surrounded by the polycrystalline silicon films 9, 12, and 42 is removed by wet etching to form the tunnel-shaped cavity 14. Further, the remaining polycrystalline silicon films 12 and 9 are removed using the photoresist 43 as a mask to form a tunnel-shaped storage electrode at the intersection of the two line patterns.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a DRAM (Dynamic Random Access Memory) in which the shape of a storage electrode is processed into a tunnel shape (cylindrical shape) or the like to increase the capacitor storage capacity.
And the like, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in a semiconductor memory device such as a DRAM, the occupied area per memory cell has become smaller as the storage capacity has been increased and the integration has been increased. Therefore, for example, a 1-transistor / 1-capacitor type DRAM
In the memory cell, it is known that the capacitor has a stack type and one electrode of the capacitor has a cylindrical (crown) type or a fin type so as to secure a capacitor capacity necessary for holding a memory.

On the other hand, in order to process the capacitor into a cylindrical type or a fin type, many steps must be performed, which requires a long time for production and increases the production cost. Therefore, as a DRAM having a large capacitor capacity that can be manufactured by a relatively small number of steps, a DRAM having a storage electrode processed into a tunnel shape has been proposed, as described in, for example, Japanese Patent Application Laid-Open No. 4-298074.

This DRAM will be described with reference to FIG. In FIG. 27, the silicon substrate 101 is LO
The element isolation is performed by the field oxide film 102 formed by the COS method, and in the active region surrounded by the field oxide film 102, a MOS having a gate electrode 103 and a pair of impurity diffusion layers 104 and 105 serving as a source / drain.
A transistor is formed. A bit line 106 is connected to the impurity diffusion layer 104, and a flattened insulating film 107 made of a BPSG film covers the entire surface. Further, a contact hole reaching the impurity diffusion layer 105 is filled with a pillar electrode of the polycrystalline silicon film 108.

A polycrystal silicon film 1 is formed on the insulating film 107.
A polycrystalline silicon film 109 connected to the column electrode of No. 08 is formed, and the polycrystalline silicon film 109 and the polycrystalline silicon film 112 form a tunnel portion of the storage electrode. The surfaces of the polycrystalline silicon films 109 and 112 are covered with a capacitor dielectric film 115, and the polycrystalline silicon films 109 and 112 that face the polycrystalline silicon films 109 and 112 via the capacitor dielectric film 115 are used as cell plate electrodes. 116 is patterned. In this way, the DRA in which the storage electrode has the tunnel portion
In M, charges can be stored in the tunnel portion, and the capacitance of the capacitor is large.

In the DRAM manufacturing method according to the above publication,
A silicon oxide film is formed in a line pattern on the polycrystalline silicon film 109, and a polycrystalline silicon film 112 is formed on the entire surface of the silicon oxide film. Then, a photoresist having a storage electrode pattern for each memory cell is formed on the polycrystalline silicon film 112, and only the polycrystalline silicon film 112 is first etched away by using the photoresist as a mask to remove the polycrystalline silicon film 109 on the polycrystalline silicon film 109. Partially expose the silicon oxide film. Then, the silicon oxide film is removed by wet etching to form a cavity in the polycrystalline silicon films 109 and 112, the polycrystalline silicon film 109 is removed with the photoresist, and a storage electrode is provided for each memory cell. Divide into.

[0007]

However, the method of manufacturing a DRAM having the above-mentioned tunnel-shaped storage electrode has the following problems.

As described above, the DRAM according to the above publication
In the manufacturing method of 1., a photoresist for forming a line pattern of the silicon oxide film formed on the polycrystalline silicon film 109 (hereinafter, referred to as “first photoresist”)
Photolithography process, and a photoresist having a storage electrode pattern for each memory cell (hereinafter,
Two photolithography steps are required, a photolithography step for patterning the “second photoresist”).

Therefore, considering the misalignment margin between the patterns of the first and second photoresists, the pattern of the first photoresist must be made sufficiently smaller than the pattern of the second photoresist. In that case, a large cavity cannot be formed in the tunnel portion, and the capacitance of the capacitor cannot be significantly increased. Therefore, when the miniaturization of the memory cell progresses, it becomes impossible to obtain a capacitor capacity that can endure a soft error, and there is a problem that the reliability of the DRAM deteriorates.

On the other hand, if the misalignment margin between the patterns of the first and second photoresists is reduced and a large cavity is formed in order to increase the capacitance of the capacitor, a defective shape of the storage electrode may occur. Will be very high. This point will be described with reference to FIGS. 28 and 29. 28A and 28B and FIG. 29, the pattern of the second photoresist 113 is the first pattern.
9A and 9B are a cross-sectional view and a plan view showing a state in which the storage electrode is misaligned with respect to the photoresist pattern in a direction intersecting the word line direction and a defective shape occurs. In addition,
A sectional view taken along line XX of FIG. 29 corresponds to FIG.

As shown in these figures, the pattern of the second photoresist 113 deviates from the pattern of the first photoresist (the same pattern as the silicon oxide film 110) in the direction orthogonal to the word line direction by a certain amount or more. And the storage electrode is not formed in a tunnel shape (ie,
Cavity 114a is not completely surrounded by polycrystalline silicon film 109 and polycrystalline silicon film 112). When such a defective shape of the storage electrode occurs, the amount of electric charge accumulated in the storage electrode decreases, and as a result, the capacitance of the capacitor cannot be significantly increased in this case as well.

That is, depending on the method of manufacturing a DRAM having a storage electrode having a relatively large amount of charge storage as described above, for example, a tunnel shape, it is impossible to achieve both miniaturization of a memory cell and securing of sufficient capacitor capacity. There was a problem.

Therefore, an object of the present invention is, for example, in a semiconductor memory device such as a DRAM having a storage electrode having a tunnel shape or the like, a semiconductor memory device in which the shape of the storage electrode does not occur even when the memory cell is miniaturized. And a method for manufacturing the same.

[0014]

In order to achieve the above object, in a method of manufacturing a semiconductor memory device according to claim 1 of the present application, a memory cell is composed of a transistor and a capacitor, and the storage electrode of the capacitor is In a method of manufacturing a semiconductor memory device formed in a tunnel shape, a step of forming the transistor on a semiconductor substrate, a step of forming a first insulating film on an upper layer of the transistor,
Forming a first conductive film connected to one of a source and a drain of the transistor on the first insulating film; and forming a first insulating film on the first conductive film. Forming a second insulating film and a second conductive film made of different materials, and at least the second conductive film of the first conductive film, the second insulating film, and the second conductive film.
By processing the insulating film and the second conductive film into a first line pattern, forming a third conductive film on the entire surface, and etching back the third conductive film to obtain at least the A step of forming a sidewall pattern of the third conductive film on a side surface of the second conductive film and the second insulating film, and an etching mask having a second line pattern intersecting the first line pattern, By removing the second conductive film by etching until the second insulating film is exposed between the second line patterns, and performing isotropic etching using the first insulating film as an etching protection film. A step of removing the second insulating film processed into the first line pattern, and using an etching mask of the second line pattern between the second line patterns. Removing the existing first and third conductive films by etching, and removing the first, second and third conductive films remaining at the intersections of the first line pattern and the second line pattern. Covering the surface of the tunnel-shaped storage electrode with a capacitor dielectric film, and a fourth step as a cell plate electrode facing the storage electrode via the capacitor dielectric film.
Patterning the conductive film.

According to another aspect of the semiconductor memory device of the present application, a first conductive film having a substantially polygonal planar shape, and a second conductive film provided at a position facing the first conductive film. Each side of the polygon has a third conductive film connected to the first conductive film and the second conductive film, and the first conductive film and the second conductive film are connected to each other. A storage electrode of the capacitor having an opening formed at a position corresponding to at least one apex of the polygon in the enclosed region and in the vicinity thereof, a capacitor dielectric film covering a surface of the storage electrode, and the capacitor. The cell plate electrode is opposed to the storage electrode via the dielectric film.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor memory device, the step of forming the transistor on the semiconductor substrate, the step of forming a first insulating film on the upper layer of the transistor, and the step of forming the first insulating film A first source connected to one of a source and a drain of the transistor on the first insulating film;
And a step of forming a conductive film of
A step of forming a second insulating film and a second conductive film made of a material different from that of the first insulating film, and a step of forming the first conductive film, the second insulating film and the second conductive film. At least the second conductive film and the second insulating film,
For each memory cell, at least a step of processing a storage electrode pattern having a substantially polygonal planar shape, a step of forming a third conductive film on the entire surface, and a step of etching back the third conductive film Forming a side wall pattern of the third conductive film on the side surfaces of the second conductive film and the second insulating film, and at a position corresponding to at least one apex of the polygon and in the vicinity thereof. Etching away the second conductive film and the third conductive film until the second insulating film is exposed, using an etching mask that exposes the conductive film and the third conductive film. Isotropic etching is performed by using the first insulating film as an etching protection film to remove the second insulating film and the remaining first, second and third layers.
Surface of the storage electrode, which is made of the conductive film described above and has an opening formed at a position corresponding to at least one apex of the polygon in a region surrounded by the first, second and third conductive films and in the vicinity thereof. With a capacitor dielectric film, and patterning a fourth conductive film as a cell plate electrode facing the storage electrode via the capacitor dielectric film.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor memory device, the step of forming the transistor on a semiconductor substrate, the step of forming a first insulating film on the upper layer of the transistor, and the step of forming the first insulating film A first source connected to one of a source and a drain of the transistor on the first insulating film;
And a step of forming a conductive film of
A step of forming a second insulating film and a second conductive film made of a material different from that of the first insulating film, and a step of forming the first conductive film, the second insulating film and the second conductive film. At least the second conductive film and the second insulating film,
For each memory cell, at least a step of processing a storage electrode pattern having a substantially polygonal planar shape, a step of forming a third conductive film on the entire surface, and a step of etching back the third conductive film A step of forming a sidewall pattern of the third conductive film on the side surfaces of the second conductive film and the second insulating film, and a position corresponding to at least one apex of the polygon without using an etching mask. And a step of etching away the second conductive film and the third conductive film until the second insulating film is exposed in the vicinity thereof, and isotropic etching using the first insulating film as an etching protection film. By removing the second insulating film and the remaining first, second and third conductive films, and surrounded by the first, second and third conductive films. region Covering the surface of the storage electrode having an opening formed at a position corresponding to at least one apex of the polygon and in the vicinity thereof with a capacitor dielectric film, and facing the storage electrode via the capacitor dielectric film. And forming a fourth conductive film as a cell plate electrode.

In one aspect of the present invention, the polygon has at least one vertex of a right angle or an acute angle.

In one aspect of the present invention, a third insulating film made of a material different from that of the first insulating film is formed between the first insulating film and the first conductive film, The second
In the step of removing the insulating film, the third insulating film is removed at the same time.

In one aspect of the present invention, the openings are provided at positions corresponding to all the vertices of the polygon and in the vicinity thereof.

In one aspect of the present invention, a bit line connected to the other of the source and the drain of the transistor is formed between the step of forming the transistor and the step of forming the first insulating film. It further has a process.

In one aspect of the present invention, in the step of forming the second insulating film and the second conductive film, two or more laminated structures of the second insulating film and the second conductive film are formed. To do.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device comprising: a first step of forming a first insulating film on a semiconductor substrate; and a first insulating film on the first conductive film. A second step of forming a second insulating film made of a material having an etching rate different from that of, a third step of forming a second conductive film on the second insulating film, and a second conductivity. A fourth step of patterning a film, the second insulating film, and the first conductive film; a fifth step of forming a third conductive film on the patterned semiconductor substrate; and an etching method. By etching the third conductive film by
A sixth step of forming a third sidewall insulating film formed of the third conductive film remaining on the sidewalls of the second conductive film, the second insulating film, and the first conductive film, and the like. And a seventh step of forming an upper or lower electrode of the capacitor made of the first, second, and third conductive films by removing the second insulating film by a isotropic etching method.

In one aspect of the present invention, after the seventh step, an eighth step of forming a dielectric film on the first, second and third conductive films, and on the dielectric film. And a ninth step of forming a fourth conductive film.

In one aspect of the present invention, the fifth step includes at least the second conductive film and the second conductive film among the first conductive film, the second insulating film and the second conductive film.
The step of forming a pattern having a substantially polygonal plane shape is included in the insulating film.

In one aspect of the present invention, the second conductive film is provided at a position corresponding to at least one apex of the polygon and in the vicinity thereof after the sixth step and before the seventh step. And a step of etching and removing the second conductive film and the third conductive film until the second insulating film is exposed using an etching mask that exposes the third conductive film.

In one aspect of the present invention, a position corresponding to at least one apex of the polygon and its vicinity are provided without using an etching mask between after the sixth step and before the seventh step. In, the method further includes a step of etching and removing the second conductive film and the third conductive film until the second insulating film is exposed.

In one aspect of the present invention, the polygon has at least one of right-angled and acute-angled vertices.

In one aspect of the present invention, in the step of forming the second insulating film and the second conductive film, two or more laminated structures of the second insulating film and the second conductive film are formed. Form.

According to the method of manufacturing a semiconductor memory device of the first aspect, the side wall made of the third conductive film is formed in the first line pattern, and the second insulating film is surrounded by the conductive film.
After that, by performing etching with an etching mask of a second line pattern that intersects the first line pattern, a tunnel-shaped storage electrode can be formed at the intersection of the two line patterns. For this reason,
Even if the second line pattern deviates from the first line pattern, the storage electrode can always be formed in a tunnel shape, and the storage electrode does not have a defective shape. Note that the first conductive film between the first line patterns is removed by using the same etching mask after processing the second insulating film and the second conductive film into the first line pattern. It may be performed, or may be performed in a self-aligned manner in the etching process when forming the sidewall pattern of the third conductive film.

According to another aspect of the semiconductor memory device of the present invention, a pair of conductive films, a first conductive film and a second conductive film, which are opposed to each other, are provided on each side of the storage electrode having a substantially polygonal planar shape. Since it is connected to the third conductive film which is a conductive film, the storage charge capacity in the storage electrode can be increased.

According to the method of manufacturing a semiconductor memory device of claim 3, the second insulating film is surrounded by a conductive film forming a storage electrode having a substantially polygonal planar shape, and then at least one of the polygonal shapes is formed. At least one opening is formed in the conductive film surrounding the second insulating film by etching with an etching mask which exposes the second conductive film and the third conductive film at a position corresponding to one vertex and in the vicinity thereof. To do. Then, isotropic etching is performed using this opening to remove the second insulating film, whereby a storage electrode having a hollow region can be formed. Since the pattern of this hollow area is determined by one etching,
The storage electrode does not have a defective shape due to misalignment of etching. The removal of the first conductive film in the region other than the region where the storage electrode is formed is performed by processing the second insulating film and the second conductive film into the pattern of the storage electrode and subsequently by using the same etching mask. May be used, or it may be performed in a self-aligned manner in the etching step when forming the sidewall pattern of the third conductive film.

In addition, the shape of the storage electrode is the etching for processing the second insulating film and the second conductive film into the pattern of the storage electrode, and the etching for forming the sidewall pattern of the third conductive film. The size between the storage electrodes can be reduced to a minimum, and the surface area of the storage electrodes can be increased.

According to the method of manufacturing a semiconductor memory device of the fourth aspect, the second insulating film is surrounded by a conductive film forming a storage electrode having a substantially polygonal planar shape, and thereafter, without using an etching mask. , At a position corresponding to at least one vertex of the polygon and in the vicinity thereof,
By etching until the insulating film of is exposed,
At least one opening is formed in the conductive film surrounding the second insulating film. Then, isotropic etching is performed using this opening to remove the second insulating film, whereby a storage electrode having a hollow region can be formed. Since the pattern of this hollow region is determined by one-time etching, the shape defect of the storage electrode due to misalignment of etching does not occur.

Further, since the etching mask is not used to form the opening, the step of applying a photoresist or the like as an etching mask and patterning by photolithography or the like becomes unnecessary, so that the number of manufacturing steps can be reduced. You can

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment in which the present invention is applied to manufacture of a DRAM having a tunnel-shaped storage electrode will be described with reference to FIGS.

1 to 4 are sectional views showing a method of manufacturing a DRAM according to the first embodiment of the present invention in the order of steps, and FIGS. 5 to 7 are plan views of the same. In these figures, FIG. 1 (a) is shown in FIG. 5 (a) and FIG. 2 (a) is shown in FIG.
2B is shown in FIG. 6A, FIG. 3A is shown in FIG. 6B, FIG. 3B is shown in FIG. 7A, and FIG.
It corresponds to the cross-sectional views taken along the line AA and the line BB in (b), and the left side in each of FIGS. 1 to 4 is AA.
The right side is a cross-sectional view taken along line BB. Also, FIG.
FIG. 7 is a perspective view of one storage electrode at the stage of FIGS. 3B and 6B.

First, as shown in FIGS. 1A and 5A, LOCOS is formed on the element isolation region of the silicon substrate 1.
After the field oxide film 2 is formed by the method, an active region surrounded by the field oxide film 2 has a gate electrode 3 and a pair of impurity diffusion layers 4 and 5 serving as a source / drain.
An OS transistor is formed. In FIG. 1 (a),
Two adjacent MOS transistors share one impurity diffusion layer 4. Further, after forming a silicon oxide film having a film thickness of about 100 nm by the CVD method, the impurity diffusion layer 4 is formed.
After forming the bit line 6 connected to, a BPSG film having a film thickness of about 500 nm is formed on the entire surface. Then, heat treatment is performed for about 30 minutes to flatten the surface of the insulating film 7 made of the silicon oxide film and the BPSG film.

Then, a silicon nitride film 41 having a film thickness of about 20 to 100 nm is formed on the entire surface by the CVD method, and then a contact hole reaching the impurity diffusion layer 5 is formed. After that, a polycrystalline silicon film 8 having a film thickness of about 500 to 1000 nm and containing phosphorus or arsenic at about 2 × 10 ^{20 to} 6 × 10 ²⁰ atoms / cm ³ is embedded in the CV so as to fill the contact hole.
After being formed by the D method, etching is performed so that the polycrystalline silicon film 8 remains only in the contact hole. As a result, the contact hole is filled with the pillar electrode of the polycrystalline silicon film 8.

Thereafter, phosphorus or arsenic is added at 2 × 10 ²⁰ to
Film thickness of 50-100n containing about 6 × 10 ²⁰ atoms / cm ³
Polycrystalline silicon film 9 of about m, film thickness 300 to 800 nm
Silicon oxide film 10 and phosphorus or arsenic 2
Film thickness 50 containing about 10 × 10 ^{20 to} 6 × 10 ²⁰ atoms / cm ³
A polycrystalline silicon film 42 of about 100 nm is sequentially formed on the entire surface by the CVD method. At this time, the polycrystalline silicon film 4
The film thickness of 2 is made larger than that of the polycrystalline silicon film 9. In addition, the contact hole is formed by the polycrystalline silicon film 8
The step of burying with the pillar electrodes of
Alternatively, the contact hole may be directly embedded.

After that, a photoresist 11 is applied on the entire surface. Then, the photoresist 11 is processed by photolithography into a line pattern (first line pattern) in the extending direction of the gate electrode 3 (hereinafter, referred to as “word line direction”). At this time, the line pattern of the photoresist 11 is left above the impurity diffusion layer 5. Then, using the photoresist 11 as a mask, the polycrystalline silicon film 42 and the silicon oxide film 10 are selectively removed by anisotropic dry etching. As a result, the polycrystalline silicon film 4 is formed on the pillar electrode of the polycrystalline silicon film 8.
2 and the line pattern of the silicon oxide film 10 remains. In this step, the polycrystalline silicon film 9 may be selectively removed by performing etching using the photoresist 11 as a mask.

In this embodiment, in order to maximize the surface area of the storage electrode and thus the capacitance of the capacitor, the line pattern interval of the photoresist 11 is set to the minimum processing dimension by photolithography.

Next, as shown in FIG. 1B, after removing the photoresist 11, phosphorus or arsenic is added at 2 × 10 ^20.
~ 6 × 10 ²⁰ atoms / cm ³ film thickness 200-60
A polycrystalline silicon film 12 having a thickness of about 0 nm is formed on the entire surface by the CVD method.

Next, as shown in FIGS. 2A and 5B, the polycrystalline silicon film 12 is anisotropically etched until the silicon nitride film 41 is exposed, whereby the silicon oxide film 10 and the polycrystalline silicon film 12 are removed. The sidewall spacers of the polycrystalline silicon film 12 are left on the side surfaces of the crystalline silicon film 42. As a result, the silicon oxide film 10 becomes the polycrystalline silicon films 9 and 1.
Surrounded by 2, 42. That is, the polycrystalline silicon films 9, 12, 42 containing the silicon oxide film 10 are included.
This means that a tunnel-shaped tube consisting of was formed.

At this time, the distance between the line patterns in the state where the sidewall spacers of the polycrystalline silicon film 12 are present is smaller than the minimum processing dimension by twice the width of the sidewall spacers. As a result, the plane area of the storage electrode of the capacitor to be completed later is increased by the side wall spacer of the polycrystalline silicon film 12.

Next, as shown in FIGS. 2B and 6A, a photoresist 43 is applied on the entire surface. Then, the photoresist 43 is processed into a line pattern (second line pattern) in a direction orthogonal to the word line direction by photolithography. At this time, by setting the line pattern interval of the photoresist 43 to the minimum processing dimension by photolithography, the surface area of the storage electrode and thus the capacitor capacitance can be maximized.

Thereafter, using the photoresist 43 as a mask, the polycrystalline silicon films 42 and 12 are removed by anisotropic dry etching until the silicon oxide film 10 is exposed.
As a result, the photoresist 43 adjacent in the word line direction is formed.
The silicon oxide film 10 is exposed between the line patterns.

Next, as shown in FIGS. 3A and 6B, isotropic wet (or dry) etching is performed to remove the silicon oxide film 10. At this time, not only the silicon oxide film 10 in the region not covered with the photoresist 43 but also the polycrystalline silicon films 9, 1
The silicon oxide film 10 in the tunnel-shaped region surrounded by 2, 42 is also removed. As a result, the tunnel-shaped region surrounded by the polycrystalline silicon films 9, 12, 42 becomes the cavity 14. During this etching, the insulating film 7 such as the underlying BPSG film is not etched because of the silicon nitride film 41 as the etching protection film.

Next, FIG. 3B, FIG. 6B and FIG.
As shown in FIG. 4, the photoresist 43 is used as a mask to remove the polycrystalline silicon films 9 and 12 between the line patterns of the photoresist 43 by etching, and then the photoresist 4 is removed.
3 is removed by ashing. As a result, the pattern made of the polycrystalline silicon films 9, 12, 42 is divided in a direction orthogonal to the word line direction, and a tunnel is formed for each memory cell at the intersection of the two line patterns defined by the photoresists 11, 43. The storage electrode of the capacitor is formed having a cavity 14 in the shape.

Next, as shown in FIGS. 4 and 7B, the polycrystalline silicon films 9, 12 including the inner surface of the cavity 14 are formed.
The surface of the storage electrode consisting of 42 has a film thickness of 3 to 10 nm.
After forming a silicon nitride film by CVD for about 30 minutes, a heat treatment is performed at 900 ° C. for about 30 minutes in an oxygen atmosphere to form a capacitor dielectric film 15 covering the storage electrode. Thereafter, the polycrystalline silicon films 9, 12, and 42 are opposed to each other through the capacitor dielectric film 15 and phosphorus or arsenic is added at 2 × 10 ^{20 to} 6 × 10 ²⁰ atoms / cm 3.
A polycrystalline silicon film 16 containing about ³ and having a film thickness of about 20 to 60 nm is formed on the entire surface as a cell plate electrode of a capacitor and patterned into a predetermined shape. At this time, the cavity 14 is filled with the polycrystalline silicon film 16. After that, by performing a known process such as forming an interlayer insulating film (not shown) and then forming a protective film, a storage electrode having a tunnel shape is formed, and charges can be stored in this tunnel portion. Large capacitor capacity D
RAM can be manufactured.

As described above, in the present embodiment, when the sidewall spacer is formed in the first line pattern defined by the photoresist 11 and the silicon oxide film 10 is surrounded by the polycrystalline silicon films 9, 12, 42. At the same time, the first line patterns are separated in a self-aligned manner, and thereafter, the polycrystalline silicon films 12, 42 are defined by an etching mask of a second line pattern defined by the photoresist 43 and orthogonal to the first line pattern. , 9 to form a tunnel-shaped storage electrode at the intersection of two line patterns.

Therefore, even when the pattern intervals of the photoresists 11 and 43 are formed to the minimum processing dimension in each of the word line direction and the direction orthogonal to this as in the present embodiment, the storage electrode is always formed. Can be formed into a tunnel shape, and the storage electrode will not be defective in shape.

When the polycrystalline silicon films 12, 42, 9 are etched with the second line pattern etching mask, the polycrystalline silicon films 12, 42 are first etched to expose the silicon oxide film 10. Since the silicon oxide film 10 is removed by wet etching, it is not necessary to use another pattern to remove the silicon oxide film 10 formed in the first line pattern. Therefore, it is possible to execute the process with a relatively small number of steps.

The silicon nitride film 41 is formed on the insulating film 7.
Since this is used as a protective film when the silicon oxide film 10 is wet-etched, the insulating film 7 is unnecessarily etched and the gate electrode 3 and the bit line 6 of the MOS transistor are exposed. Can be prevented.

Next, regarding the second embodiment of the present invention,
This will be described with reference to FIG.

The present embodiment differs from the first embodiment in the bit line formation position and order. In the present embodiment, as shown in FIG. 9, the interlayer insulating film 45 is formed after the polycrystalline silicon film 16 serving as the cell plate electrode is patterned so as to be divided above the impurity diffusion layer 4. Then, a contact hole reaching the impurity diffusion layer 4 is opened in the interlayer insulating film 45, the insulating film 7, etc., and then the bit line 46 connected to the impurity diffusion layer 4 is formed.

In this embodiment, since the bit line 46 is formed above the capacitor, it is necessary to make the distance between the two storage electrodes facing each other with the impurity diffusion layer 4 in between, larger than in the first embodiment. . In other words, in the first embodiment described above, since the bit line 6 is formed below the capacitor, the distance between the two storage electrodes facing each other with the impurity diffusion layer 4 in between is made as small as the minimum processing size. It is possible to increase the capacitance of the capacitor.

Next, regarding the third embodiment of the present invention,
This will be described with reference to FIGS. 10 and 25.

The present embodiment differs from the first embodiment in the tunnel-shaped structure of the storage electrode. In this embodiment, as shown in FIG. 25, which is a perspective view corresponding to FIG. 8, a tunnel-shaped cavity portion is formed in a two-step structure. In order to form such a structure, as shown in FIG.
In the step shown in FIG. 3, two layers of the silicon oxide film 10 and the polycrystalline silicon film 42 are alternately formed. That is, two laminated structures of the silicon oxide film 10 and the polycrystalline silicon film 42 are formed. The other steps are the same as those described in the first embodiment. It is also possible to form three or more stacked structures of the silicon oxide film 10 and the polycrystalline silicon film 42 so that the tunnel-shaped cavity has a structure of three or more steps.

As described above, in this embodiment, by forming the tunnel-shaped cavity portion in the two-step structure, it becomes possible to accumulate more charges in the storage electrode in the same occupied area.

In the above-described first to third embodiments, the MOS transistor is formed, then the insulating film 7 is flattened, and the capacitor is formed on the insulating film 7. The capacitor may be formed without flattening the insulating film formed above. Further, the first line pattern and the second line pattern are not limited to being linear, and may have a meandering shape according to the design of the memory cell array, and the thickness thereof may be changed depending on the place. Further, even if the first line pattern and the second line pattern are not orthogonal to each other, they may be intersected so that a tunnel-shaped storage electrode can be formed.

Next, a fourth embodiment of the present invention will be described with reference to FIGS.

11 to 14 are sectional views showing a method of manufacturing the DRAM of the fourth embodiment of the present invention in the order of steps, and FIGS. 15 to 17 are plan views of the same. In addition, in these figures, FIG. 11B corresponds to FIG.
2 (a) is shown in FIG. 15 (b), and FIG. 12 (b) is shown in FIG.
FIG. 13A is a diagram of FIG. 17A and FIG.
Corresponds to the cross-sectional view taken along the line AA of FIG. 17 (b), and FIG. 13 (a) (b) shows the cross-sectional view taken along the line BB of FIG. 17 (a) (b). It is also shown on the right side. In addition, FIG. 14A is a cross-sectional view taken along line CC of FIG. 16A, FIG. 14B is FIG. 16B, and FIG. 14C is FIG. 17A. It corresponds. FIG.
(A), (b) and (c) are perspective views of one storage electrode at each stage of FIGS. 16 (a), (b) and 17 (a), respectively.

First, as shown in FIG. 11A, after forming the field oxide film 2 on the element isolation region of the silicon substrate 1 by the LOCOS method, the gate electrode is formed in the active region surrounded by the field oxide film 2. A MOS transistor having a pair of impurity diffusion layers 4 and 5 serving as a source / drain is formed. In FIG. 11A, two adjacent MOS transistors share one impurity diffusion layer 4. Further, after forming a silicon oxide film with a film thickness of about 100 nm by a CVD method and then forming a bit line 6 connected to the impurity diffusion layer 4, a BPSG with a film thickness of about 500 nm is formed.
A film is formed on the entire surface. After that, the temperature is 800-900 ℃
Then, heat treatment is performed for about 30 minutes to flatten the surface of the insulating film 7 made of the silicon oxide film and the BPSG film.

Then, a silicon nitride film 28 having a film thickness of about 20 to 100 nm is formed on the entire surface by a CVD method, and a silicon oxide film 29 having a film thickness of about 50 to 300 nm is formed on the entire surface by a CVD method, and then impurity diffusion is performed. A contact hole reaching layer 5 is formed. Then, 2 × 10 ^{20 to} 6 × 10 ²⁰ atm of phosphorus or arsenic is filled to fill the contact hole.
A polycrystalline silicon film 27 containing about oms / cm ³ and having a film thickness of about 500 to 1000 nm is formed by a CVD method, and then etching is performed so that the polycrystalline silicon film 27 remains only in the contact hole. As a result, the contact hole is filled with the pillar electrode of the polycrystalline silicon film 27.

Thereafter, phosphorus or arsenic is added at 2 × 10 ²⁰ to
Film thickness of 50-100n containing about 6 × 10 ²⁰ atoms / cm ³
Polycrystalline silicon film 31 of about m, thickness 300-800n
A silicon oxide film 32 of about m and a film thickness of 5 containing phosphorus or arsenic of about 2 × 10 ^{20 to} 6 × 10 ²⁰ atoms / cm ³
The polycrystalline silicon film 33 having a thickness of 0 to 100 nm is formed by CVD.
Are sequentially formed on the entire surface by the method. At this time, the thickness of the polycrystalline silicon film 33 is made larger than that of the polycrystalline silicon film 31.

Next, as shown in FIGS. 11B and 15A, a photoresist 34 is applied on the entire surface. Then, this photoresist 34 is divided by photolithography into memory cell patterns each having a quadrangular (rectangular) planar shape for each memory cell. At this time,
The pattern of the photoresist 34 is left on the impurity diffusion layer 5.

Next, as shown in FIG. 11C, the polycrystalline silicon film 33 and the silicon oxide film 32 are selectively removed by anisotropic dry etching using the photoresist 34 as a mask, and then the photoresist is removed. 34 is removed by ashing. As a result, the polycrystalline silicon film 27
The storage electrode-shaped pattern of the polycrystalline silicon film 33 and the silicon oxide film 32 divided for each memory cell remains above the column electrodes of the. In this step, the polycrystalline silicon film 31 may be selectively removed by performing subsequent etching using the photoresist 34 as a mask.

In this embodiment, in order to maximize the surface area of the storage electrode and thus the capacitance of the capacitor, the pattern interval between the adjacent photoresists 34 is set to the minimum processing dimension by photolithography.

Next, as shown in FIGS. 12 (a) and 15 (b), phosphorus or arsenic is added in an amount of 2 × 10 ^{20 to} 6 × 10 ^20.
A polycrystalline silicon film 35 having a film thickness of about 200 to 600 nm containing about atoms / cm ³ is formed on the entire surface by the CVD method. Then, the polycrystalline silicon film 35 is anisotropically etched until the silicon oxide film 29 is exposed.
Sidewall spacers of the polycrystalline silicon film 35 are left on the side surfaces of the silicon oxide film 32 and the polycrystalline silicon film 33.
As a result, the silicon oxide film 32 becomes the polycrystalline silicon film 3
It is surrounded by 1, 33, and 35. That is, in the DRAM memory cell of the present embodiment, a pair of conductive films, that is, the polycrystalline silicon films 31 and 33 and a sidewall conductive film are formed on each side of the storage electrode having a rectangular planar shape. Connected to the crystalline silicon film 35

At this time, the interval between the adjacent storage electrode patterns in the state where the side wall spacers of the polycrystalline silicon film 35 are present is smaller than the minimum processing size by twice the width of the side wall spacers. As a result, the plane area of the storage electrode of the capacitor to be completed later is reduced to the polycrystalline silicon film 3
5 side wall spacers.

Next, FIG. 12 (b), FIG. 14 (a), and FIG.
As shown in FIG. 6A and FIG. 18A, a photoresist 36 is applied on the entire surface, and the photoresist 36 is
Each memory cell is processed by photolithography into a pattern having openings 37 such that the polycrystalline silicon films 33 and 35 are exposed in the vicinity of four apexes of the rectangular storage electrode pattern. At this time, the opening 37
Need not be formed near all four vertices, but may be formed near at least one vertex.

Next, as shown in FIGS. 14 (b), 16 (b) and 18 (b), using the photoresist 36 as a mask, the silicon oxide film 32 in the region not covered with the photoresist 36 is formed. The polycrystalline silicon films 33, 35 are formed until at least a part of them are exposed and the openings 26 are formed in the vicinity of the positions corresponding to the above-mentioned four vertices in the region surrounded by the polycrystalline silicon films 31, 33, 35. It is removed by anisotropic dry etching, and then the photoresist 36 is removed.

Next, FIG. 13 (a), FIG. 14 (c), and FIG.
As shown in FIG. 7A and FIG. 18C, the silicon oxide film 32 is removed by performing isotropic wet (or dry) etching. As a result, the region surrounded by the polycrystalline silicon films 31, 33, and 35 has the opening 26.
And the polycrystalline silicon film 3 is formed.
A gap 25 is formed between 1 and the silicon nitride film 28. In this etching, since there is the silicon nitride film 28 as an etching protection film, the lower BP is formed.
The insulating film 7 such as the SG film is not etched.

Next, as shown in FIGS. 13B and 17B, the inner surface of the cavity 38 and the polycrystalline silicon film 3 are formed.
1 and the silicon nitride film 28, the surface of the storage electrode composed of the polycrystalline silicon films 31, 33 and 35 including the gap 25 is formed by CVD with a silicon nitride film having a film thickness of about 3 to 10 nm.
After coating by the method, 900 ° C in an oxygen atmosphere, 3
By performing a heat treatment for about 0 minutes, a capacitor dielectric film 39 such as an ONO film covering the storage electrode is formed.
To form Thereafter, it faces the polycrystalline silicon films 31, 33, and 35 via the capacitor dielectric film 39, and contains phosphorus or arsenic at a concentration of about 2 × 10 ^{20 to} 6 × 10 ²⁰ atoms / cm ³ and a thickness of about ²⁰ to 100 nm. Polycrystalline silicon film 40
Is formed on the entire surface as the cell plate electrode of the capacitor,
Pattern into a predetermined shape. At this time, the cavity 38 is filled with the polycrystalline silicon film 40. Thereafter, a known process such as forming an interlayer insulating film (not shown) and then forming a protective film is performed to manufacture the DRAM according to the present embodiment.

As described above, in the DRAM memory cell of the present embodiment, the polycrystalline silicon films 31 and 33, which are a pair of conductive films facing each other, are provided for each side of the storage electrode formed in a substantially rectangular plan shape. Since the polycrystalline silicon film 35, which will be the side wall conductive film, is connected, D of the first embodiment
The storage charge capacity at the storage electrode can be made larger than that at the RAM memory cell.

Further, according to the method of manufacturing the DRAM of the present embodiment, the polycrystalline silicon film 3 forming the storage electrode having a substantially rectangular plan shape around the silicon oxide film 32 is provided.
1, 33, and 35, and thereafter, etching is performed with an etching mask that exposes the polycrystalline silicon films 33 and 35 at a position corresponding to at least one apex of the rectangle and in the vicinity thereof.
At least one opening 26 is formed in the polycrystalline silicon films 31, 33 and 35 surrounding the. Then, isotropic etching is performed using this opening 26 to remove the silicon oxide film 32, whereby a storage electrode having a cavity 38 can be formed. The pattern of this cavity 38 is shown in FIG.
Since it is determined by one-time etching using the photoresist 34 as a mask described in (b) and (c), a shape defect of the storage electrode due to misalignment of etching does not occur.

Since the shape of the storage electrodes is uniquely determined by the etching using the photoresist 34 as a mask and the etching for forming the sidewall spacers of the polycrystalline silicon film 35, the dimension between the storage electrodes is determined. Can be reduced to a minimum and the surface area of the storage electrode can be increased.

The gap 2 between the polycrystalline silicon film 31 and the silicon nitride film 28 is not limited to the inner surface of the cavity 38.
Since the polycrystalline silicon film 31 in the five parts is also used as a part of the capacitor, the capacitance of the capacitor can be further increased.

Further, in this embodiment, the photoresist 3 is used.
The openings 37 of No. 6 are provided at the positions corresponding to all the vertices of the storage electrode pattern having a rectangular planar shape and in the vicinity thereof. One of the openings 37 is located in the
The situation that the opening 26 is not formed in the parts 3 and 35 does not occur. Therefore, the DRAM can be manufactured with high reliability. Further, there is an advantage that the etching progresses rapidly even when the isotropic etching is performed, and the manufacturing can be performed in a short time.

As is clear from FIGS. 15 to 17, the planar shape of the storage electrode finally formed according to the present embodiment is exactly a quadrangle due to the lack of apexes due to an intermediate step. However, in the present specification, description will be given even if such a shape change is made to some extent. Further, in the present embodiment, the planar shape of the storage electrode is substantially quadrangular, but the planar shape of the storage electrode is not limited to this and may be any polygon such as a triangle or a pentagon.

Further, the modified examples of the second and third embodiments described above can be applied to the present embodiment.
That is, a bit line may be formed above the capacitor, or the storage electrode may have a multi-layer structure.

Next, a fifth embodiment of the present invention will be described with reference to FIGS.

19 to 20 are sectional views showing a method of manufacturing the DRAM of the fifth embodiment of the present invention in the order of steps, and FIGS. 21 to 22 are plan views of the same. Note that in these figures, FIG. 19 (a) corresponds to FIG.
9 (b) is shown in FIG. 21 (b), and FIG. 19 (c) is shown in FIG.
19 corresponds to the cross-sectional view taken along the line A in FIG.
21B and 22C, the cross-sectional views taken along the line BB of FIGS. 21B and 22 are also shown on the right side. FIG.
21 (a) is shown in FIG. 21 (a), and FIG. 20 (b) is shown in FIG. 21 (b).
The cross-sectional views taken along line C-C of FIG. Also,
23 (b) and 23 (c) are respectively shown in FIG. 20 (a) and FIG.
FIG. 23B is a perspective view of one storage electrode at each stage of FIG. 23B, and FIG. 23A is the same as FIG. 1 described in the fourth embodiment.
FIG. 16 is a perspective view of one storage electrode at a stage corresponding to 2 (a) and FIG. 15 (b).

First, referring to FIG. 1 described in the fourth embodiment.
By performing the same steps as those in FIGS. 1A to 12A, the silicon oxide film 52 on the silicon oxide film 29 as shown in FIG.
A storage electrode structure surrounded by 53 and 55 and having a quadrangular (rectangular) planar shape is obtained.

Next, FIG. 19 (a), FIG. 20 (a), and FIG.
As shown in FIG. 1A and FIG. 23B, without using an etching mask, the polycrystalline silicon films 53, 55 are formed until the silicon oxide film 52 is exposed in the vicinity of the four vertices of the rectangular storage electrode pattern. Anisotropically etch. As a result, the openings 56 are formed near the four vertices. The etching conditions at this time are, for example, HBr + Cl when a parallel plate type etcher is used.
₂ or SF ₆ + Cl ₂ , pressure 200 to 600 mTorr,
The RF power is 100 to 300 mW and is about 10 to 40 seconds. The openings 56 do not have to be formed in the vicinity of all of the above four vertices, but may be formed in the vicinity of at least one of the vertices.

As described above, by performing the etching in this embodiment without using the etching mask, the silicon oxide film 52 is exposed only in the vicinity of the above-mentioned four vertices while the polycrystalline silicon films 53 and 55 remain. The reason is that the etching action strongly works especially at a protruding portion such as a vertex formed at a right angle or an acute angle, and the etching rate at this portion is high.

Next, FIG. 19 (b), FIG. 20 (b), and FIG.
As shown in FIG. 1B and FIG. 23C, the silicon oxide film 52 is removed by performing isotropic wet (or dry) etching. As a result, the area surrounded by the polycrystalline silicon films 51, 53, 55 is the opening 56.
And the polycrystalline silicon film 5 is formed.
A gap 25 is formed between 1 and the silicon nitride film 28. In this etching, since there is the silicon nitride film 28 as an etching protection film, the lower BP is formed.
The insulating film 7 such as the SG film is not etched.

Next, as shown in FIG. 19C and FIG. 22, polycrystalline silicon films 51, 53 including a gap 25 between the inner surface of the cavity 58 and the polycrystalline silicon film 51 and the silicon nitride film 28. The surface of the storage electrode made of 55 is coated with a silicon nitride film having a film thickness of about 3 to 10 nm by the CVD method, and then heat treatment is performed at 900 ° C. for about 30 minutes in an oxygen atmosphere to cover the storage electrode. A capacitor dielectric film 59 such as an ONO film is formed. Thereafter, it faces the polycrystalline silicon films 51, 53, 55 via the capacitor dielectric film 59 and contains phosphorus or arsenic in an amount of about 2 × 10 ^{20 to} 6 × 10 ²⁰ atoms / cm ³ and a thickness of about ²⁰ to 100 nm. Is formed on the entire surface as a cell plate electrode of a capacitor and patterned into a predetermined shape. At this time, the cavity 58 is filled with the polycrystalline silicon film 60. After that, by performing a known process such as forming an interlayer insulating film (not shown) and then forming a protective film, the D according to the present embodiment can be obtained.
RAM is manufactured.

As described above, in the DRAM memory cell of the present embodiment, the pair of conductive films, that is, the polycrystalline silicon films 51 and 53, which are opposed to each other, are provided on each side of the storage electrode formed in a substantially rectangular planar shape. The DRAM of the fourth embodiment is formed in order to form the opening 56 relatively small while being connected to the polycrystalline silicon film 55 which will be the sidewall conductive film.
The storage charge capacity at the storage electrode can be made larger than that at the memory cell.

Further, according to the method of manufacturing the DRAM of the present embodiment, the polycrystalline silicon film 5 forming the storage electrode having a substantially rectangular planar shape around the silicon oxide film 52.
Then, the polycrystalline silicon film 33, 35 is surrounded by 1, 53, 55, and thereafter, without using an etching mask, until the silicon oxide film 52 is exposed at a position corresponding to at least one apex of the quadrangle and its vicinity. As a result, at least one opening 56 is formed in the polycrystalline silicon films 51, 53, 55 surrounding the silicon oxide film 52. Then, isotropic etching is performed using this opening 56 to remove the silicon oxide film 52, whereby a storage electrode having a cavity 58 can be formed.
The pattern of the cavities 58 is shown in FIG.
Since it is determined by one-time etching using the photoresist 34 as a mask described in 1 (b) and (c), the shape defect of the storage electrode due to misalignment of etching does not occur.

Further, in the present embodiment, since the etching mask is not used to form the opening 56, the step of applying a photoresist or the like as the etching mask and patterning by photolithography or the like becomes unnecessary. The number can be reduced.

Further, the modified examples of the second and third embodiments can be applied to the present embodiment.
That is, a bit line may be formed above the capacitor, or the storage electrode may have a multi-layer structure.

Next, a sixth embodiment in which the planar shape of the storage electrode is modified in the present embodiment will be described with reference to FIG.
This will be described with reference to FIG.

In the fifth embodiment, the silicon oxide film 52 can be exposed by performing etching without using an etching mask because the storage electrode is patterned so that its planar shape is polygonal. Since the polygon has the apex with a smaller angle such as a right angle or an acute angle, the above effect can be exerted more strongly.

Therefore, in the present embodiment, in the fifth embodiment, the polycrystalline silicon film 53 and the silicon oxide film 52 are processed in the step corresponding to FIG. 11B of the fourth embodiment.
The photoresist used to etch the
As shown in FIG. 4, a photoresist 71 patterned in a concave polygonal shape (a concave hexagon in FIG. 24) is used, and at least one vertex 71a having a relatively small angle of about 60 ° is formed in the photoresist 71 (see FIG. 24, 4).

As a result, according to the present embodiment, even when the etching without using the etching mask is performed as in the fifth embodiment, the silicon oxide film 5 is surely formed.
2 can be exposed. In addition, vertex 7
In practice, the angle of 1a is preferably about 30 to 90 °, and practically about 60 ° is most preferable.

The storage electrode formed according to this embodiment will be described with reference to FIG. FIG. 26 is a perspective view showing the storage electrode in each manufacturing step corresponding to FIG.

First, FIGS. 11A to 12 described in the fourth embodiment except that the photoresist 71 is used.
By performing the same process as in (a), the planar shape in which the silicon oxide film 82 is surrounded by the polycrystalline silicon films 81, 83, 85 on the silicon oxide film 29 as shown in FIG. A concave hexagonal storage electrode structure is obtained.

Next, as shown in FIG. 26B, the silicon oxide film 82 is exposed in the vicinity of four apexes of the concave hexagonal storage electrode pattern having an apex of about 60 ° without using an etching mask. Until that, the polycrystalline silicon films 83 and 85 are anisotropically etched. As a result, the openings 86 are formed near the four vertices. The etching conditions at this time are the same as those in the fifth embodiment.

Next, as shown in FIG. 26C, the silicon oxide film 82 is removed by performing isotropic wet (or dry) etching. As a result, a cavity having an opening 86 is formed in a region surrounded by the polycrystalline silicon films 81, 83, 85. Hereinafter, the DRAM of the present embodiment is formed by performing the same steps as those in the fifth embodiment.

[0103]

According to the present invention, in manufacturing a semiconductor memory device such as a DRAM having a storage electrode having a tunnel shape or the like, a defective storage electrode shape does not occur even when a memory cell is miniaturized. Since a capacitor having a large capacity can always be obtained, the soft error resistance of the semiconductor memory device can be greatly improved, and a highly integrated semiconductor memory device with high reliability can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method of manufacturing a DRAM according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing the method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing the method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing the method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 5 is a plan view showing a method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 6 is a plan view showing the method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 7 is a plan view showing the method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 8 is a perspective view showing a DRAM according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating the method of manufacturing the DRAM according to the second embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating the method of manufacturing the DRAM according to the third embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the method of manufacturing the DRAM according to the fourth embodiment of the present invention in the order of steps.

FIG. 12 is a cross-sectional view showing a method of manufacturing a DRAM according to the fourth embodiment of the present invention in the order of steps.

FIG. 13 is a cross-sectional view showing a method of manufacturing a DRAM according to the fourth embodiment of the present invention in the order of steps.

FIG. 14 is a cross-sectional view showing a method of manufacturing a DRAM according to the fourth embodiment of the present invention in the order of steps.

FIG. 15 is a plan view showing a method of manufacturing a DRAM according to the fourth embodiment of the present invention in the order of steps.

FIG. 16 is a plan view showing a method of manufacturing a DRAM according to the fourth embodiment of the present invention in the order of steps.

FIG. 17 is a plan view showing a method of manufacturing a DRAM according to the fourth embodiment of the present invention in the order of steps.

FIG. 18 is a perspective view showing the method of manufacturing the DRAM according to the fourth embodiment of the present invention in the order of steps.

FIG. 19 is a cross-sectional view showing the method of manufacturing the DRAM according to the fifth embodiment of the present invention in the order of steps.

FIG. 20 is a cross-sectional view showing the method of manufacturing the DRAM according to the fifth embodiment of the present invention in the order of steps.

FIG. 21 is a plan view showing a method of manufacturing a DRAM according to the fifth embodiment of the present invention in the order of steps.

FIG. 22 is a plan view showing a method of manufacturing a DRAM according to the fifth embodiment of the present invention in the order of steps.

FIG. 23 is a perspective view showing a method of manufacturing a DRAM according to a fifth embodiment of the present invention in the order of steps.

FIG. 24 is a plan view illustrating the method for manufacturing the DRAM according to the sixth embodiment of the present invention.

FIG. 25 is a perspective view for explaining the third embodiment of the present invention.

FIG. 26 is a perspective view for explaining the sixth embodiment of the present invention.

FIG. 27 is a cross-sectional view showing a conventional DRAM.

FIG. 28 is a cross-sectional view showing a conventional DRAM.

FIG. 29 is a plan view showing a conventional DRAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Field oxide film 3 Gate electrode 4, 5 Impurity diffusion layer 6 Bit line 7 Insulating film 8 Polycrystalline silicon film (first conductive film) 9 Polycrystalline silicon film (first conductive film) 10 Silicon oxide film (Second insulating film) 11, 43 Photoresist 12 Polycrystalline silicon film (third conductive film) 14 Cavity 15 Capacitor dielectric film 16 Polycrystalline silicon film (cell plate electrode) 41 Silicon nitride film (first insulating film) Film) 42 polycrystalline silicon film (second conductive film)

Claims (16)

[Claims] 1. A method of manufacturing a semiconductor memory device, wherein a memory cell is composed of a transistor and a capacitor, and a storage electrode of the capacitor is formed in a tunnel shape, and a step of forming the transistor on a semiconductor substrate. Forming a first insulating film in an upper layer of the transistor, and forming a first conductive film connected to one of a source and a drain of the transistor on the first insulating film, Forming a second insulating film and a second conductive film made of a material different from that of the first insulating film on the first conductive film; and the first conductive film and the second conductive film. Of the insulating film and the second conductive film, a step of processing at least the second insulating film and the second conductive film into a first line pattern, and forming a third conductive film on the entire surface. And a step of forming a sidewall pattern of the third conductive film on at least a side surface of the second conductive film and the second insulating film by etching back the third conductive film. A step of etching the second conductive film using an etching mask of a second line pattern intersecting the first line pattern until the second insulating film is exposed between the second line patterns; A step of removing the second insulating film processed into the first line pattern by performing isotropic etching using the first insulating film as an etching protection film; and an etching mask for the second line pattern. Using
Etching away the first and third conductive films remaining between the second line patterns, and the first remaining at the intersection of the first line pattern and the second line pattern, A step of covering the surface of the tunnel-shaped storage electrode made of the second and third conductive films with a capacitor dielectric film, and a fourth step as a cell plate electrode facing the storage electrode via the capacitor dielectric film. And a step of patterning a conductive film. 2. A first conductive film having a substantially polygonal planar shape, and a second conductive film provided at a position facing the first conductive film.
And a third conductive film connected to the first conductive film and the second conductive film on each side of the polygon, and the first conductive film, the second conductive film, and the third conductive film. No. 3, a storage electrode of the capacitor having an opening formed at a position corresponding to at least one apex of the polygon in a region surrounded by the conductive film, and a capacitor dielectric covering a surface of the storage electrode. A semiconductor memory device comprising: a film; and a cell plate electrode facing the storage electrode via the capacitor dielectric film. 3. A method of manufacturing a semiconductor memory device, comprising: forming the transistor on a semiconductor substrate; forming a first insulating film on the upper layer of the transistor; and forming a first insulating film on the first insulating film. Forming a first conductive film connected to one of a source and a drain of the transistor, and forming a second conductive film on the first conductive film, the second conductive film being made of a material different from that of the first insulating film. Forming an insulating film and a second conductive film, and at least the second conductive film and the second insulating film among the first conductive film, the second insulating film, and the second conductive film Is processed into a storage electrode pattern having a substantially polygonal planar shape for each memory cell, a step of forming a third conductive film on the entire surface, and a step of etching back the third conductive film. At least before Forming a sidewall pattern of the third conductive film on the side surfaces of the second conductive film and the second insulating film, and at a position corresponding to at least one apex of the polygon and in the vicinity thereof, Etching away the second conductive film and the third conductive film until the second insulating film is exposed using an etching mask that exposes the conductive film and the third conductive film; A step of removing the second insulating film by performing isotropic etching using the first insulating film as an etching protection film, and the remaining first, second and third conductive films,
A surface of the storage electrode having an opening formed at a position corresponding to at least one apex of the polygon in a region surrounded by the first, second and third conductive films and in the vicinity thereof is formed of a capacitor dielectric film. A method of manufacturing a semiconductor memory device, comprising: a step of covering; and a step of patterning a fourth conductive film as a cell plate electrode facing the storage electrode via the capacitor dielectric film. 4. A method of manufacturing a semiconductor memory device, comprising: forming the transistor on a semiconductor substrate; forming a first insulating film on the upper layer of the transistor; and forming a first insulating film on the first insulating film. Forming a first conductive film connected to one of a source and a drain of the transistor, and forming a second conductive film on the first conductive film, the second conductive film being made of a material different from that of the first insulating film. Forming an insulating film and a second conductive film, and at least the second conductive film and the second insulating film among the first conductive film, the second insulating film, and the second conductive film Is processed into a storage electrode pattern having a substantially polygonal planar shape for each memory cell, a step of forming a third conductive film on the entire surface, and a step of etching back the third conductive film. At least before A step of forming a sidewall pattern of the third conductive film on the side surfaces of the second conductive film and the second insulating film, and a position corresponding to at least one apex of the polygon without using an etching mask and Etching and removing the second conductive film and the third conductive film until the second insulating film is exposed in the vicinity thereof, and isotropic etching using the first insulating film as an etching protection film. A step of removing the second insulating film by applying, and the remaining first, second and third conductive films,
A surface of the storage electrode having an opening formed at a position corresponding to at least one apex of the polygon in a region surrounded by the first, second and third conductive films and in the vicinity thereof is formed of a capacitor dielectric film. A method of manufacturing a semiconductor memory device, comprising: a step of covering; and a step of patterning a fourth conductive film as a cell plate electrode facing the storage electrode via the capacitor dielectric film. 5. The method of manufacturing a semiconductor memory device according to claim 4, wherein the polygon has at least one vertex of either a right angle or an acute angle. 6. A third insulating film made of a material different from that of the first insulating film, between the first insulating film and the first conductive film.
6. The semiconductor memory device according to claim 3, wherein the third insulating film is removed at the same time in the step of forming the second insulating film and removing the second insulating film. Production method. 7. The method of manufacturing a semiconductor memory device according to claim 3, wherein the openings are provided at positions corresponding to all the vertices of the polygon and in the vicinity thereof. . 8. The method further comprises the step of forming a bit line connected to the other of the source and the drain of the transistor between the step of forming the transistor and the step of forming the first insulating film. 8. The method of manufacturing a semiconductor memory device according to claim 1, wherein the method is a semiconductor memory device. 9. In the step of forming the second insulating film and the second conductive film, two or more stacked structures of the second insulating film and the second conductive film are formed. A method of manufacturing a semiconductor memory device according to claim 1, 3 or 8. 10. A method of manufacturing a capacitor of a semiconductor memory device, comprising: a first step of forming a first insulating film on a semiconductor substrate; and an etching different from the first insulating film on the first conductive film. A second step of forming a second insulating film made of a material having a rate; a third step of forming a second conductive film on the second insulating film; a second conductive film; A second step of patterning the second insulating film and the first conductive film; a fifth step of forming a third conductive film on the patterned semiconductor substrate; and a third step of etching the third conductive film. Etching the conductive film to form a third sidewall insulating film formed of the third conductive film remaining on the sidewalls of the second conductive film, the second insulating film, and the first conductive film. The sixth step of forming and the isotropic etching method And a seventh step of forming an upper or lower electrode of the capacitor composed of the first, second and third conductive films by removing the second insulating film. Device manufacturing method. 11. An eighth step of forming a dielectric film on the first, second, and third conductive films after the seventh step according to claim 10, and on the dielectric film. 9. A method of manufacturing a semiconductor memory device, further comprising: a ninth step of forming a fourth conductive film. 12. The fifth step according to claim 10, wherein at least the second conductive film and the second conductive film are selected from the first conductive film, the second insulating film, and the second conductive film. A method of manufacturing a semiconductor memory device, comprising the step of forming a pattern in which an insulating film has a substantially polygonal planar shape. 13. A position corresponding to at least one apex of the polygon and the vicinity thereof, between after the sixth step and before the seventh step in the method for manufacturing a semiconductor memory device according to claim 12. In, using the etching mask that exposes the second conductive film and the third conductive film, the second conductive film and the third conductive film are removed by etching until the second insulating film is exposed. A method of manufacturing a semiconductor memory device, which further comprises steps. 14. The semiconductor memory device manufacturing method according to claim 12, wherein at least one vertex of the polygon is formed without using an etching mask between after the sixth step and before the seventh step. The method for manufacturing a semiconductor memory device, further comprising: a step of etching and removing the second conductive film and the third conductive film until the second insulating film is exposed at a position corresponding to and in the vicinity thereof. . 15. The method of manufacturing a semiconductor memory device according to claim 12, wherein the polygon has at least one vertex of a right angle or an acute angle. 16. The step of forming the second insulating film and the second conductive film according to claim 10, wherein a stack of the second insulating film and the second conductive film is formed. A method for manufacturing a semiconductor memory device, comprising forming two or more structures.