JPH09213926A - Semiconductor relay - Google Patents

Abstract

(57) [Abstract] (Correction) [Problem] Semiconductor relay with two switching elements DMO
When the S FETs 4 and 5 and the shunt resistor 3 connected to the gates are configured as diffusion resistors on one chip, a parasitic transistor 6 is formed, and acts to bypass the signal input to the gates of the DMOS FETs 4 and 5. The energization amount of the DMOS FETs 4 and 5 is reduced. A semiconductor relay that does not cause such a failure is realized. SOLUTION: A light emitting element 1 that generates an optical signal in response to an input signal, a photodiode array 2 that receives the optical signal and generates a photoelectromotive force, and the photoelectromotive force is applied between a gate and a source. Output MOS that is applied and becomes conductive
In a semiconductor relay having FETs 4 and 5, the output MOS FETs 4 and 5 are lateral high withstand voltage DMOS F
ET, and the shunt resistor 3 connected in parallel between the gate and the source is formed as a thin film resistor on the same chip to prevent the occurrence of a parasitic transistor action.
Prevents a decrease in the current passing through the OS FETs 4 and 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to expansion of a switching current of a semiconductor relay using an optical coupling method for insulation between an input and an output.

[0002]

2. Description of the Related Art A lateral high breakdown voltage DMOS according to a conventional method
It is possible to integrate semiconductor relays using FETs. For example, two switching elements DMOS F on one chip
It is composed of ET and a diffusion resistor inserted between the gate and the source to discharge the charge accumulated in the gate.
However, even if an attempt is made to increase the passing current of the DMOS FET with such a configuration, the action of a transistor (called a parasitic transistor) appears due to the presence of the diffusion resistance. Since this parasitic transistor acts to bypass the signal input to the gate terminal of the DMOS FET, D
The passing current of the MOS FET is reduced. Next, the operation will be described with reference to a circuit diagram. FIG. 3 is a circuit diagram of a conventional semiconductor relay having the above structure. When an input current I _{F is} passed through the LED 1, a constant current I _OS is generated in the photodiode array 2. This current I _OS is the output MOS FE
A current I _C flows to the gate G of T4 and 5
A low impedance state is set between the drain D and the source S of the FETs 4 and 5. At the same time, a current I _S flows through the shunt resistor 3 (diffusion resistor R _S2 ) provided in parallel to discharge the charge accumulated in the gate G. Here, it is assumed that the main current I _D flows from the terminal D ₁ to the direction D ₂ .

Reference numeral 6 is the parasitic transistor described above. When a constant voltage V _BE between the base b and the emitter e of the parasitic transistor 6 is applied, the collector c and the emitter e are electrically connected. When the voltage V _S-D2 generated between the source S and the drain D of the DMOS FET 5 becomes larger than the voltage V _BE , the current I _OS from the photodiode array 2 flows into the parasitic transistor 6 and the gate currents of the FETs 4 and 5 are insufficient. Then, a high impedance state is established between the drain D and the source S of each DMOS FET. As an example, DM
Resistance R between source S and drain D for one OS FET
_{When S-D2} is 220Ω and V _BE = 0.5 V (an example of the conduction start voltage V _BE of the parasitic transistor), the maximum flowing current I _DMAX can be obtained as follows. I _DMAX = V _BE / R _S-D2 = 0.5 V / 220 Ω = 2.3 mA If a current exceeding 2.3 mA flows, the voltage V _BE applied between the base b and the emitter e of the parasitic transistor 6
Exceeds 0.5 V, the current I _OS from the photodiode array 2 flows through the collector c of the parasitic transistor 6 to the emitter e and does not flow to the gate G of the FETs 4 and 5. Therefore, even though the input current I _F is applied to the LED 1, no current flows between the drain D and the source S of the FETs 4 and 5 while maintaining high impedance.

FIG. 4 is a sectional view of a conventional semiconductor relay having a parasitic transistor. Known DMOS FE
Using the T manufacturing technique, N ^{− type} portions 33 and 34 and P type portion 13 are formed, and N ⁺ portion 12 is formed therein by double diffusion. An optical coupling circuit that insulates the input and the output from each other can be provided separately, so the description thereof is omitted. 10 is a P-type silicon substrate, 11 is an insulating film, 12 is an N-type high concentration region, 1
3 is a P-type region, 34 is an N-type region, 23 and 24 are polycrystalline silicon, 29 and 31 are drain electrodes, and 30 and 32.
Is a source electrode, and 25 and 26 are diffusion resistance extraction electrodes. As shown in FIG. 4, the DMOS FET 4 has a gate electrode composed of polycrystalline silicon 23 and a drain electrode 2.
9 and the source electrode 30. Similarly, DMOS
The FET 5 is composed of polycrystalline silicon 24 serving as a gate electrode, a drain electrode 31, and a source electrode 32. The shunt resistor 3 has electrodes 25 and 2 on both ends of the N ^{− type} portion 33.
6 is provided and configured. The gate electrodes 23 and 24 are connected to the gate G, and the source electrodes 30 and 32 are connected to the source S. The shunt resistor extraction electrodes 25 and 26 are connected to the gate G and the source S, respectively, and the DMOS FETs 4 and 5 and the shunt resistor 3 (diffusion resistor) are formed on the same chip. With such a connection relation, the action of one npn-type transistor using the N ⁻ layer 33 as the collector c, the P-type silicon substrate 10 as the base b, and the N ⁻ layer 34 as the emitter e functions as a MOS FET.
Holds inside. This is a parasitic transistor. When this transistor operates, the charging current I _C input to the gate G is bypassed to the drain D ₂ through the collector c and the emitter e, the gate currents of the DMOSFETs 4 and 5 are insufficient, and the DMOS FET has a large passage. Can't pass current.

[0005]

As described above, when two switch elements DMOS FETs and shunt resistors connected to their gates are formed as diffusion resistors on one chip, a parasitic transistor is formed. This parasitic transistor acts so as to bypass the signal input to the gate of the DMOS FET, and thus reduces the energization amount of the DMOS FET. MOS without causing such an obstacle
It is an object of the present invention to realize a semiconductor relay capable of passing a large passing current through an FET.

[0006]

SUMMARY OF THE INVENTION The present invention comprises a light emitting element which generates an optical signal in response to an input signal, a photodiode array which receives the optical signal and generates a photoelectromotive force,
In a semiconductor relay having an output MOS FET in which a source and a drain are in a conductive state when the photovoltaic power of the photodiode array is applied between the gate and the source, the output MOS FE formed on the same chip.
T is a lateral high voltage DMOS FET, and the gate
The shunt resistor connected in parallel between the sources is used as a thin film resistor to prevent the occurrence of parasitic transistor action,
To eliminate the limitation of the rated current of the DMOS FET.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
You. FIG. 1 shows a semiconductor relay circuit according to an embodiment of the present invention.
It is a road map. 1 is an LED. 2 is the light emission of LED1
A photodiode array that receives and operates
High voltage DMOS FETs 4 and 5 gate G and source
It is connected in parallel between S. At the same time, the charge of the gate G
The shunt resistor 3 for discharging is the gate of the FETs 4 and 5.
Are connected in parallel between the source G and the source S. Hereafter
The operation of the example will be described. Input current I to LED1_FTo
When added, a constant current I is applied to the photodiode array 2._{O S}But
Occur. This current I_OSIs an output MOS FET4 and
Current I to gate G of 5_CAs a horizontal type, high withstand voltage DM
There is a pair between the drain D and the source S of the OS FETs 4 and 5.
The corresponding impedance state is set. At the same time, gate G
The capacitors installed in parallel to discharge the charge accumulated in the
Input resistor 3 (thin film resistor R_S1) To the current I _SFlows as.
Shunt resistor 3 is diffused resistor R_S2To thin film resistor R_S1Instead of
Then, the parasitic transistor 6 does not occur. Therefore, the photo
Current I generated in diode array 2_OSSome current I
_CIs D₁To D_TwoRegardless of the magnitude of the current flowing through
Flows into G. Therefore, the output MOS FET4 and
Low impedance between source S and drain D of 5
The state is maintained and the passing current is not limited.

FIG. 2 is a sectional view showing an embodiment of the present invention. Reference numeral 20 is a thin film resistor made of a polycrystalline silicon film in place of the diffusion resistor (corresponding to the shunt resistor 3 · R _S2 in FIG. 3) formed of the N ⁻ layer 33 and the two N ⁺ layers 12 in FIG. This resistance is CVD (Chemical Vapor D
Eposition method or the like. Electrodes 21 and 22 are attached to both ends of the electrode and led out, and are connected in parallel to the gate G and source S electrodes as a shunt resistor (FIG. 1).
3R _S1 ). A silicon oxide film (SiO ₂ ) is formed between the resistor 20 and the silicon substrate 10 made of this polycrystalline silicon film.
Fully insulated by 11. Therefore, in FIG.
Although a diffusion resistance (R _S2 ) composed of the N ⁻ layer 33 and the N ⁺ layer 12 is formed between 5 and 26, in the present invention, the thin film resistor 20 is used between the electrodes 21 and 22, so that Although the respective elements are integrated on one chip, the parasitic transistor is not formed and the intended purpose can be achieved.

[0009]

According to the present invention, the output MOS FET
Since the shunt resistor connected between the gate and the source in order to discharge the gate accumulated charge is formed of polycrystalline silicon instead of the diffusion resistor, a parasitic transistor for bypassing the gate current is not formed. Therefore, a current can flow between the drain terminals D1 and D2 without being limited by the parasitic transistor.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a sectional view showing one embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional example.

FIG. 4 is a sectional view of a conventional example.

[Explanation of symbols]

 1 Light-Emitting Diode 2 Photodiode 3 Shunt Resistor 4 First DMOS FET 5 Second DMOS FET 6 Parasitic Transistor 10 p-type Silicon Substrate 11 Insulating Film 12 N-type High Concentration Region 13 P-type Region 20 Polycrystalline Silicon Resistor 21, 22 Polycrystalline silicon resistance extraction electrode 23/24 Polycrystalline silicon 25/26 Diffusion resistance extraction electrode 29/31 Drain electrode 30/32 Source electrode 33/34 N type low concentration region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H03K 17/78

Claims (1)

[Claims] 1. A light emitting element that generates an optical signal in response to an input signal, a photodiode array that receives the optical signal and generates a photoelectromotive force, and a photoelectromotive force of the photodiode array is a gate. In a semiconductor relay having an output MOS FET, which becomes conductive between the source and the drain when applied between the sources, the output MOS F
A semiconductor relay characterized in that ET is a lateral high-voltage DMOS FET, and a resistor connected in parallel between the gate and source of the high-voltage DMOS FET is a thin-film resistor formed on the same chip.