JPH09213933A - Semiconductor device and power conversion device using the same - Google Patents

Abstract

(57) 【Abstract】 PROBLEM TO BE SOLVED: To provide a semiconductor device having improved breaking capability,
A large-capacity, small-sized, low-priced power conversion device using this is provided. A groove is formed so as to divide an n-type emitter layer on a unit GTO into two, and an insulating layer is provided. Insulating layer 61
Is located in the final concentration region of the main current at turn-off, and thereby divides the final concentration region of the main current at turn-off into two to prevent the temperature rise which is the cause of the breakdown. The cathode electrode 2 is brought into low-resistance contact with the n-type emitter layer 8 divided across the insulating layer 61. [Effect] By increasing the breaking tolerance of the unit GTO, the breaking tolerance of the GTO can be improved, and the peripheral circuits can be reduced without reducing the capacity of the power conversion device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate turn-off thyristor (hereinafter referred to as GTO) capable of controlling conduction / non-conduction of a main current by a control current, or
The present invention relates to a semiconductor device such as a transistor (hereinafter referred to as “TRS”) and a power conversion device using the same, and more particularly to a semiconductor device such as GTO and TRS with improved cut-off resistance and a power conversion device using the same.

[0002]

2. Description of the Related Art In recent years, GTO has been attracting attention as a key device such as a large-capacity power converter for steel and a reactive power compensator for cleaning a power source, and a large-capacity element (6 kV-6 kA) has been developed. Has been done. Generally, GTO
Requires a snubber circuit because of its low breaking capability.

FIG. 13 is a diagram showing an example of a snubber circuit.
In FIG. 13, 130 is an anode terminal, 131 is a cathode terminal, 132 is a gate terminal, 133 is a GTO, 13
4 is a snubber diode, 135 is a snubber capacitor, 1
Reference numeral 36 is a snubber resistor, and 137 is a snubber circuit.

As shown in FIG. 13, the snubber circuit 137 includes a snubber diode 134 and a snubber capacitor 13.
5, the snubber resistor 136, the anode terminal 1
An anode terminal 130 and a cathode terminal 13 of a GTO 133 having 30, a cathode terminal 131, and a gate terminal 132.
It is used by connecting between 1 and 1. Such a snubber circuit 137 operates so as to transfer the current when the GTO 133 is turned off to the snubber capacitor 135.
It is possible to cause 33 to interrupt a large current. When the GTO is turned on, the snubber circuit 137 discharges and consumes the accumulated charge of the snubber capacitor 135 accumulated as described above via the snubber resistor 136.

The consumption type snubber circuit 137 as described above.
If the power converter is composed of a GTO with
As the capacity of O133 increases, the loss due to the snubber circuit 137 increases, which lowers the power conversion efficiency. As a conventional technique capable of preventing the loss due to such a snubber circuit, a method capable of recovering the energy of the snubber capacitor 135 is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 05-205.
It is proposed and known in Japanese Patent Publication No. 227736. However, when the above-mentioned recovery method is adopted, the power conversion device becomes large in size and the price becomes high, and the circuit operation becomes complicated, so that the reliability is lowered. Will end up.

Generally, a GTO is formed by forming a large number of small-capacity elements (hereinafter referred to as a unit GTO) in the same pellet, and connecting these unit GTOs in parallel, so that the unit GTO itself has a low interruption resistance. The fact that it is difficult to equalize the parallel operation between the unit GTOs is a cause of requiring a large snubber circuit.

Therefore, as a conventional technique capable of increasing the breaking resistance of the unit GTO, for example, Japanese Patent Laid-Open No. 59-8 is available.
The technique described in Japanese Patent No. 6262 is known.

Hereinafter, the structure of a general unit GTO and the structure of an improved unit GTO will be described with reference to the drawings.

FIG. 14 is a general unit GT according to the prior art.
FIG. 15 is a cross-sectional view showing an example of the structure of O, FIG. 15 is a top view of the unit GTO shown in FIG. 14, and FIG. 16 is a cross-sectional view showing the structure of a unit GTO according to the prior art with an increased breaking resistance. FIG.
4 to 16, 1 is a semiconductor substrate, 2 is a cathode electrode, 3a and 3b are gate electrodes, 4 is an anode electrode, 5 is a p-type emitter layer (pE), 6 is an n-type base layer (nB),
7 is a p-type base layer (pB), 8 is an n-type emitter layer (n
E), 9 are anode terminals, 10 is a cathode terminal, and 11 is a gate terminal.

A general unit GTO according to the prior art shown in FIGS. 14 and 15 is, in order from the lower main surface of the semiconductor substrate 1,
p-type emitter layer 5, n-type base layer 6, p-type base layer 7,
The cathode electrode 2 is provided on the n-type emitter layer 8 on the upper main surface of the semiconductor substrate 1 on which the n-type emitter layer 8 is formed, and the p-type base layer 7 is provided with the gate electrodes 3a and 3b in low resistance contact. , P-type emitter layer 5 on the lower main surface of the semiconductor substrate 1
The anode electrode 4 is provided in low resistance contact with, and the cathode terminal K10, the gate terminal G11, and the anode terminal A9 are connected to these electrodes.

Although a surface stabilizing material is provided on the exposed surface of the semiconductor substrate 1 other than the portions where the electrodes 2 to 4 are provided in the above description, the surface stabilizing material is omitted in the figure. The description is the same, and the illustration is omitted.

In order to turn off the unit GTO having the above-mentioned structure from the conductive state to the non-conductive state,
It suffices to draw the gate current from the gate terminal 11. At this time, the excess carriers accumulated in the p-type base layer 7 that creates the GTO conduction state are gate electrodes 3a and 3b.
Are sequentially swept from the area close to. Therefore, in the inside of the GTO, the conduction regions are sequentially turned off from the side closer to the gate electrodes 3a and 3b, and the gate currents 12a and 12b having the same magnitude are extracted from both sides of the n-type emitter layer 8. Finally, the conduction region 13 remains in the center of the n-type emitter layer 8 and the current concentrates.

Since there is no excess carrier in the p-type base layer 7 that has finished turning off under the n-type emitter layer 8, the resistance at that portion is in a thermal equilibrium state. Therefore, the resistances 14a and 14b of the gate current path from the gate electrodes 3a and 3b to the conduction region of the p-type base layer 7 in the central portion of the n-type emitter layer 8 become larger than those at the initial stage of turn-off, and the gate current becomes difficult to be extracted. Therefore, in the final current concentration region 13, an excessive temperature rise occurs due to the power loss, and the GTO is thermally destroyed. The reason why the unit GTO has a small breaking resistance is that it is difficult to maintain uniform operation in the longitudinal direction of the unit GTO as described above.

As shown in FIG. 15, the upper surface of the unit GTO has a shape in which the cathode electrode 2 surrounded by the gate electrodes 3a and 3b is arranged on the semiconductor substrate 1. Then, the region 40 shown on the cathode electrode 2 becomes the final concentration region of the main current at turn-off. Since this region is a narrow region within the unit GTO, the characteristic variation of the semiconductor layer and the electrode is small, so that it is located almost at the center of the cathode electrode 2. The circled range 44 is the final current concentration of the unit GTO. This is a simulated representation of a range in which an excessive temperature rise occurs due to power loss and the temperature escapes.

As described above, the GTO having a general structure according to the prior art cannot generate a final concentration region of the main current at the time of turn-off to increase the breaking resistance.

As a conventional technique capable of increasing the breaking tolerance of such a unit GTO, there is a technique of dividing an n-type emitter layer as shown in FIG. 16 is p
The vicinity of the junction between the type base layer 7 and the n-type emitter layer 8 is enlarged.

As shown in FIG. 16, this unit GTO is
The insulating region 130 is placed so that the cathode electrode 2 and the p-type base layer 7 are not short-circuited, and the n-type emitter layer 8 is divided into two.
By connecting the space between them with the cathode electrode 2, the final current concentration region at the time of turn-off is divided into two current concentration regions 60a and 60b to improve the breaking resistance of the unit GTO.

In general, the GTO has a structure in which a large number of unit GTOs having the above-mentioned structure are formed in the same pellet and these are connected in parallel. To improve the breaking resistance of the GTO, the efficiency between the unit GTOs is improved. Good parallel operation is required. Hereinafter, a case where a large number of unit GTOs are connected in parallel will be described.

FIG. 17 shows two unit GTOs connected in parallel.
FIG. In FIG. 17, 20, 21
Is a unit GTO, and other symbols have a and b as their subscripts.
Etc. are attached, but are the same as in the case of FIG. Hereinafter, the parallel operation of the two unit GTOs will be described with reference to FIG.

The first unit GTO in the example shown in FIG.
20 and the second unit GTO 21 respectively include the cathode electrodes 2a and 2b and the gate electrode 3 on the upper main surface of the semiconductor substrate.
a and 3b, 3c and 3d are provided in low resistance contact,
Each of them is connected to a cathode terminal K10 and a gate terminal G11. Anode electrodes 4a and 4b are provided in low resistance contact with the lower main surface of the semiconductor substrate and are connected to the anode terminal A9. The structure of the semiconductor layer is similar to that described with reference to FIG.

In the first unit GTO 20 and the second unit GTO 21 which are connected in parallel as described above, the p-type base layers 7a and 7b of each GTO are different due to variations in manufacturing process (each size, sheet resistance value, etc.). Lateral resistance 22a of
When a difference occurs in the value of 22b, there is a difference in the time for turning off the first unit GTO 20 and the second unit GTO 21 from the conducting state to the non-conducting state. As a result, as shown in FIG. 17, in the GTO in which the unit GTOs are connected in parallel, the main current is concentrated in the unit GTO that is turned off late, and the unit GTO is
In the final current concentration area of, the power loss causes an excessive temperature rise and thermal destruction.

As a conventional technique for solving such a problem, for example, the technique described in Japanese Patent Laid-Open No. 5-30308 is known. In this conventional technique, each unit GTO is provided with a floating gate,
This is to make a short circuit in the unit to make the current between the unit GTOs uniform.

FIG. 18 is a diagram schematically showing two unit GTOs provided with a floating gate in each unit GTO, short-circuiting them in the GTO, and connected in parallel. In FIG. 18, reference numerals 30a and 30b denote floating gate electrodes, and other reference numerals are the same as those in FIG. Hereinafter, the parallel operation of the two unit GTOs will be described with reference to FIG.

First unit GTO 20 and second unit GTO
21 is the first unit GTO 20 and the second unit shown in FIG.
In place of the gate electrodes 3b and 3c with the unit GTO21, the floating gate electrodes 30a and 30b which are not connected to the gate terminal G11 are provided. The GTO is configured by connecting the floating gates of each unit GTO to each other.

In such a GTO, when turned off, the gate terminal G11 makes the GTO conductive.
Excess carriers accumulated in the mold base layers 7a and 7b are sequentially swept out from the regions near the gate electrodes 3a and 3d. Therefore, the conduction regions are sequentially turned off from the side closer to the gate electrodes 3a, 3d, and the final current concentration regions 13a, 13b appear on the side closer to the floating gate electrodes 30a, 30b.

At this time, as shown in FIG. 18, since the floating gate electrodes 30a and 30b are connected to each other, the loop current 32 causes the junction between the p-type base layers 7a and 7b and the n-type emitter layers 8a and 8b. Flow in such a manner that the potentials of the final current concentration regions 33a and 33b near the portions are equalized.
As a result, in the conventional technique shown in FIG. 18, the currents in the current concentration regions 13a and 13b can be made uniform.

However, in the prior art shown in FIG. 18, a large number of unit GTOs are formed in a pellet within a certain size,
When these unit GTOs are operated in parallel, the parallel operation can be made uniform, which is effective. However, it is taken into consideration that a large number of unit GTOs are formed in parallel operation. Since it does not exist, it has the following problems.

That is, in the prior art shown in FIG. 18, the line connecting the floating gate electrodes 30a, 30b becomes longer as the diameter of the pellet becomes larger, and the resistance component 31 of the wiring through which the loop current 32 flows becomes larger. When the loop current 32 flows through the resistance component 31, the p-type base layers 7a and 7b and the n-type emitter layers 8a and 8 are formed.
A potential difference occurs in the final current concentration regions 33a and 33b near the junction with b, and the currents in the current concentration regions 13a and 13b cannot be made uniform. Also, the unit GTO20,
21 and the gate terminal G11 become long, the resistance between the gate electrodes 3a and 3b and the gate terminal G11 becomes large, and the turn-off time becomes different between the unit GTOs, which lowers the interruption resistance of the GTO as a whole. I will let you. In addition, the distribution of variations in manufacturing processes (each size, sheet resistance value, etc.) is not considered.

[0029]

In the prior art capable of increasing the breaking tolerance of the unit GTO described above, the breaking tolerance of the unit GTO can be increased by dividing the final current concentration region at turn-off. It is a thing. However, this prior art does not consider that the connection method of the large diameter GTO is mainly the pressure contact method.
That is, this conventional technique has the first problem that the deformation of the cathode electrode 2 and the insulating region 130 due to the pressure contact and the risk of short circuit due to the deformation are not taken into consideration.

As a means for solving such a problem,
A method of disposing the cathode electrode 2 only on each of the divided n-type emitter layers 8 is, for example, Japanese Patent Publication No. 6-5738.
This method is also described in Japanese Patent Laid-Open Publication No. 2003-242, but in consideration of the blocking efficiency, the width of the n-type emitter layer 8 is narrowed, the width of the electrode becomes narrow, and it is easily deformed by pressure welding. There is a problem that contact efficiency becomes poor.

In addition, the above-mentioned conventional technique has a second problem that it is not possible to obtain a sufficient increase in the breaking resistance because no consideration is given to dividing the final current concentration region into two in good balance. And unit GT
There is a third problem that the pellet structure for increasing the breaking resistance of a large diameter GTO that operates by arranging a large number of O and the variation in the in-plane characteristics of the pellet due to the large diameter are not taken into consideration.

The object of the present invention is to solve the above-mentioned problems of the prior art and to increase the breaking tolerance of the unit GTO.
By providing the above-mentioned element structure and the optimum pellet structure, it is possible to significantly increase the breaking tolerance of the GTO, and to reduce the size and cost of the electrode conversion device using the GTO. And to provide a power conversion device using the same.

[0033]

According to the present invention, the object is to provide at least three semiconductor layers having different conductivity types from each other between a pair of main planes of a semiconductor substrate, and the three semiconductor layers. The first semiconductor layer has a long and narrow shape having a substantially constant width, and the second semiconductor layer includes the first semiconductor layer and the first semiconductor layer so as to surround the first semiconductor layer.
In a semiconductor device exposed on a main plane, a first main electrode is in low resistance contact with the first semiconductor layer, and a control electrode is in low resistance contact with each of the second semiconductor layers, in a width direction center of the first semiconductor layer. An insulating region is provided, and the first main electrode is brought into low resistance contact with two first semiconductor layers divided into two by the insulating region across the insulating region, and the insulating region of the insulating region is also provided. It is achieved by providing a conductive region in a state of being insulated from the first semiconductor layer between the second semiconductor region and the insulating region on the side opposite to the first main electrode.

Further, the object is to form at least three semiconductor layers having different conductivity types from each other between a pair of main planes of a semiconductor substrate, and the first semiconductor layer among the three semiconductor layers is One or more juxtaposed to the first major surface of the semiconductor body, having a substantially constant width, and a second semiconductor layer together with the first semiconductor layer so as to surround the first semiconductor layer; Of the first semiconductor layer, the first main electrode is in low resistance contact with each of the first semiconductor layers, and the control electrode is in low resistance contact with each of the second semiconductor layers as a unit semiconductor element, In a semiconductor device in which a plurality of unit semiconductor elements are connected in parallel and each control electrode of the unit semiconductor element is connected to a control terminal provided on the semiconductor substrate,
As the plurality of unit semiconductor elements, an insulating region is provided in the widthwise center of the first semiconductor layer, and the first main electrode is
A first unit semiconductor element, which is in low resistance contact across the insulating region, and an insulating region are provided in the center in the width direction of the first semiconductor layer, on the two first semiconductor layers divided by the insulating region. This is achieved by mixing the second unit semiconductor element which does not exist.

[0035] Further, the above object is to provide the first unit semiconductor element between the insulating region and the second semiconductor region on the opposite side of the first main electrode across the insulating region of the insulating region.
This is achieved by adopting a structure in which a conductive region is provided while being insulated from the first semiconductor layer.

The object is to dispose the control terminal in the center of a semiconductor substrate having a circular shape and dispose the first unit semiconductor element in the center of the semiconductor substrate around the control element. Achieved by

Further, the above object can be achieved by using the semiconductor device having the above-mentioned structure as a switching element to form a power conversion device.

According to the above-described structure of the present invention, the final current concentration region of the main current at turn-off can be divided into two without being affected by the pressure contact, and the divided final current in the unit semiconductor element can be divided. It is possible to balance the current sharing in the concentrated region.

Furthermore, the final current concentration can be generated in the unit semiconductor element having a large turn-off resistance, and
Since the final current concentration region can be placed in a region in which the characteristic variation in the semiconductor substrate is relatively small, the current sharing among the respective unit semiconductor elements can be made substantially uniform.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device and a power converter using the same according to the present invention will be described below in detail with reference to the drawings by taking a GTO as an example of a semiconductor device.

FIG. 1 is a sectional view showing the structure of a unit GTO according to the first embodiment of the present invention, and FIG. 2 is a unit GT shown in FIG.
It is a top view of O. In FIGS. 1 and 2, reference numeral 61 is an insulating layer, and other reference numerals are the same as those in FIG.

The unit GTO according to the first embodiment of the present invention shown in FIGS. 1 and 2 is provided with an insulating region in the final concentrated region of the main current in order to improve the interruption withstand capability thereof. The structure of the semiconductor layer and the electrode structure are similar to those of the general unit GTO described with reference to FIG. The first embodiment of the present invention is configured so that the insulating layer 61 is provided at the central portion in the longitudinal direction of the n-type emitter layer 8 where the main current is concentrated, and thus the unit GTO shown in FIG. The structure is different from that of FIG. 2 and the insulating layer 61 is provided so as to separate the n-type emitter layer 8. The n-type emitter layer is divided into two by the p-type base layer 7, and the cathode electrode 2 and the p-type This is different from the structure of the unit GTO shown in FIG. 16 in which the insulating region 130 is provided so as not to short-circuit with the base layer 7.

That is, in the first embodiment of the present invention, as shown in FIG. 1, the general unit G described with reference to FIG.
To divide the n-type emitter layer 8 of TO into two, for example,
An insulating layer 61 such as a silicon oxide film is inserted. As described above, the insulating layer 61 is located in a region that becomes a final concentrated region of the main current at turn-off before the insulating layer 61 is inserted, and the position thereof is ½ in the width direction of the n-type emitter layer 8.
Is where The insulating layer 61 is formed so as to be flush with the surface of the n-type emitter layer 8 on the side where the cathode electrode 2 makes low resistance contact with the n-type emitter layer 8.
The temporary surface is formed so as to slightly enter the p-type base layer 7. As a result, the final concentrated region of the main current at turn-off is divided into two, such as final concentrated regions 60a and 60b.

As shown in FIG. 2, the upper surface of the unit GTO according to the above-described embodiment has the gate electrode 3 on the semiconductor substrate 1.
The insulating layer 61 having a shape in which the cathode electrode 2 is arranged surrounded by a and 3b and having the same length as the longitudinal direction of the n-type emitter layer 8 immediately below the cathode electrode 2 is the n-type emitter layer 8.
Is divided into two in the longitudinal direction. Then, the regions 70 and 71 shown on the cathode electrode 2 become the final concentrated region of the main current at turn-off, and the final concentrated region of the main current is divided into two. Since this region is a narrow region within the unit GTO, variations in the characteristics of the semiconductor layer and the electrode are small, so that it is located on both sides of the insulating layer 61 in the substantially center of the cathode electrode 2, and the range surrounded by a semicircle. 72
However, in the final current concentration area of the unit GTO, the temperature is a range where an excessive temperature rise due to power loss escapes.
The number is larger than that described with reference to FIG.

The unit GTO according to the first embodiment of the present invention described above has no risk of deformation and short circuit due to pressure contact, and the contact efficiency with the external electrode is equal to that of the conventional case described with reference to FIG. It is possible to increase the range in which the temperature escapes when an excessive temperature rise occurs due to power loss in the final current concentration region of the GTO.
The interruption resistance of O can be improved, and as a result, GT
It is possible to improve the interruption resistance of the whole O.

FIG. 3 is a characteristic diagram for explaining the experimental result of the breaking tolerance of the unit GTO. Next, referring to FIG.
4, the interruption withstand capability between the general unit GTO described with reference to FIG. 15 and the unit GTO according to the first embodiment of the present invention described with reference to FIGS. 1 and 2 will be described.

FIG. 3 shows the anode-cathode voltage at the turn-off limit on the abscissa and the anode current at the turn-off limit on the ordinate, and the curve 50 shows the characteristic of a general unit GTO. The curve 51 is the first of the present invention.
3 shows characteristics of a unit GTO according to the embodiment of FIG. As can be seen from these characteristics, it can be seen that the breaking tolerance of the unit GTO of the first embodiment of the present invention in which the n-type emitter layer is divided into two is significantly improved.

FIG. 4 is a sectional view showing the structure of a unit GTO according to the second embodiment of the present invention, and FIG. 5 is a unit GT shown in FIG.
It is a top view of O. In FIGS. 4 and 5, reference numeral 66 is a conductive region, and other reference numerals are the same as those in FIGS. 1 and 2.

The unit G according to the second embodiment of the present invention
The TO is p below the insulating region 61 in order to keep the balance of the current in the final divided region of the main current at turn-off in the unit GTO according to the first embodiment of the present invention.
A conductive region 66 is provided between the mold base layer 7 and the mold base layer 7.

FIG. 4 shows a p-type base layer 7 and an n-type emitter layer 8.
The vicinity of the junction (hereinafter referred to as j3 junction) is shown in an enlarged manner, and this unit GTO has, for example, a conduction region 66 such as a p-layer having a high impurity concentration under the insulating region 61. It is added so as not to contact the n-type emitter layer 8.

In the second embodiment of the present invention, n
By providing the insulating layer 61 in the central portion of the type emitter layer 8, the final current concentration region at the time of turn-off is the current concentration region 6
0a and the current concentration region 60b are divided into two, and the interruption resistance can be improved as in the case of the first embodiment of the present invention described above.

At turn-off, the gate electrodes 3a,
3b and current concentration regions 60a and 60b, and resistors 14a and 1b.
If the potentials of the circled parts 67 and 68 near the j3 junction in the current concentration region determined by 4b are the same, the currents concentrated in the current concentration region 60a and the current concentration region 60b are the same, and the unit GTO is the maximum cutoff. Withstand can be obtained. On the contrary, when the resistors 14a and 14b are not equal, the potentials of the circled portions 67 and 68 are different, and the currents concentrated in the current concentration regions 60a and 60b are different from each other. As a result, the breaking tolerance of the unit GTO is determined by the current concentration region where a large amount of current concentrates, and the unit GTO
If the sum of the concentrated currents of the two divided TOs is the same, the unit GTO cannot obtain the maximum interruption withstand capability.

In the second embodiment of the present invention, since the conduction region 66 is provided so as to connect the circled portions 67 and 68 with low resistance, the conduction region 66, the n-type emitter layer 8 and the cathode are provided. A loop current 65 flows through the electrode 2, which makes it possible to make the potentials of the circled points 67 and 68 substantially equal.

Next, the longitudinal balance of the unit GTO according to the second embodiment of the present invention will be described with reference to FIG. Although not shown in FIG. 5, the conduction region 66 is provided below the insulating layer 61 having the same length as the longitudinal direction of the n-type emitter layer 8, and is similar to the unit GTO width direction in the longitudinal direction. Also acts to make the potentials equal. Therefore, as shown in FIG. 5, the final concentrated regions 70 and 71 of the main current at the time of turn-off also spread in the longitudinal direction due to the balance in the longitudinal direction. As a result, in the GTO according to the second embodiment of the present invention, the range where the temperature escapes is the area 7 in FIG.
The range shown by 2 can be increased as compared with the case of the first embodiment of the present invention, and the current concentration per unit area can be further alleviated.

According to the second embodiment of the present invention described above, the concentration of current in the longitudinal direction of the unit GTO can be alleviated and the effect of the first embodiment can be further enhanced, and the width of the unit GTO in the width direction can be increased. Since the potentials can be balanced, the effect according to the first embodiment of the present invention can be efficiently realized.

In the above-described first and second embodiments of the present invention, the semiconductor substrate 1 is p-typed from the anode to the cathode.
Although the description has been made assuming that it is configured by an npn four-layer structure, the present invention may be an npnp four-layer structure in which each layer has an opposite conductivity type. Further, although the above-described respective embodiments have been described as those in which the present invention is applied to the GTO, the present invention is
By making the p-type emitter layer a high impurity concentration n layer,
The TRS according to the present invention can be obtained, and in this case, the same effect can be obtained in the TRS.

The present invention relates to final current concentration near the j3 junction and extraction of excess carriers, and is not limited by the structure on the anode side when the present invention is carried out.

The above-described first and second embodiments of the present invention were related to the structure of the unit GTO.
An embodiment of a pellet structure in which a large number of unit GTOs are formed according to the above-described embodiment will be described. Before that, first, a relationship between the GTO interruption resistance and the gate current will be described.

FIG. 6 shows G at turn-off with time as the horizontal axis.
FIG. 7 is a diagram showing waveforms of a TO cathode current, an anode-cathode voltage, and a gate current. In FIG. 6, 80 is a cathode current, 81 is an anode-cathode voltage, and 82 is a gate current. GT shown
Corresponds to O's IK, VAK, and IG.

In FIG. 6, it is assumed that the GTO starts turn-off at time 0 by the external control circuit. What is focused on in this figure is that the cathode current 80 flows in the negative direction, that is, in the reverse direction during the period 83 of T. This is because the gate current is superposed on the cathode current. The existence of the period T of minus T means that all the excess carriers in the n-type emitter layer forming the GTO are extracted and the GTO is turned off. Means that you have finished.

However, the waveform of this cathode current 80 is
It is the waveform of the whole GTO. Looking at the unit GTO,
Due to variations in characteristics between the unit GTOs and the like, there may be a unit GTO in which the period 83 of T does not exist among the many unit GTOs operating in parallel. GTO
Is a unit GTO connected in parallel, the anode-cathode voltage 81 is common to each unit GTO, and the same applies to the unit GTO in which the period 83 of T does not exist (turn-off is not completed). Therefore, the voltage between the anode and the cathode is applied. As a result, an overcurrent flows in the unit GTO whose turn-off has not ended, and the GTO is destroyed.

The existence of the above-described T period 83 is largely related to the current of the gate current 82 at a time corresponding to the T period 83, which is generally called a gate avalanche current.

FIG. 7 is a diagram for explaining the relationship between the gate avalanche current and the breaking capability (breaking limit current under the same voltage).

This figure shows the experimental results obtained by the inventors using a small capacity GTO to plot the gate avalanche current on the horizontal axis and the breaking capability on the vertical axis. Characteristic curve 8
As can be seen from FIG. 5, the larger the gate avalanche current, the higher the GTO interruption resistance. Actual GTO
The gate avalanche current in is used in a region of the slope of the characteristic curve 85, that is, a portion that is considerably smaller than the boundary line 86 between the slope and the flat portion of the curve 85.
From this figure, it can be seen that the effect of improving the interruption withstand capability due to the increase in the gate avalanche current is remarkable. That is, in order to improve the breaking tolerance of the unit GTO, a gate avalanche current of a certain value or more is required.

FIG. 8 is a plan view illustrating the structure of a GTO pellet to which the third embodiment of the present invention is applied, and FIG. 9 is a plan view illustrating the structure of a GTO pellet according to the third embodiment of the present invention. . In FIGS. 8 and 9, 90 is a GTO pellet, 91 is a gate extraction electrode, and 92 is a unit GTO.
Of the cathode electrode.

The third embodiment of the present invention described below relates to the GTO pellet structure based on the above-mentioned findings, and the main current final concentration region at the time of turn-off is set to G
The TO is located near the gate lead-out electrode 91. Therefore, the unit GTO arranged in that region has the structure according to the above-described first and second embodiments of the present invention.

An example of a GTO pellet 90 to which the third embodiment of the present invention shown in FIG. 8 is applied is a center gate structure having a gate extraction electrode 91 in the center,
The cathode electrodes 92 of the unit GTO are arranged in parallel on the GTO main plane so as to form a plurality of rings. In the example shown in FIG. 8, a 4-ring structure is used for simplification of the drawing, but currently, 10 rings or more and 5,000 or more unit GTOs are arranged.

In FIG. 8, the rings formed by the unit GTO are divided into 1 ring, 2 rings, 3 rings from the inner circumference.
When referred to as a 4-ring, a distance 93 from the unit GTO included in one innermost ring to the gate lead electrode 91 and a distance 94 from the unit GTO included in the outermost four rings to the gate lead electrode 91. It turns out that there is a difference. This difference becomes more remarkable as the diameter increases and the number of rings increases. The difference in the distance from the unit GTO to the gate lead-out electrode 91 appears as the difference in resistance between the gate electrode of the unit GTO and the gate lead-out electrode 91 of the GTO. It is clear that the smaller the resistance value, the easier it is to draw out the gate current of the unit GTO.

In the third embodiment of the present invention, this unit GT is used.
The final current concentration region of the entire GTO is located in a ring having a small resistance value between the O gate electrode and the GTO gate extraction electrode 91, and the first and second embodiments of the present invention described above are located in the ring. The unit GTO having a high interruption resistance according to the embodiment is arranged. In the example shown in FIG.
Since the gate extraction electrode 91 of the GTO has the center gate structure provided in the central portion of the GTO pellet, the final current concentration region is located on one ring, or one ring and two rings.

A GTO pellet 90 showing a third embodiment of the present invention shown in FIG. 9 is a simplified version of FIG. 8, and is in the same region 120 as the final concentration region of the main current at the turn-off of the GTO. It is shown that the unit GTO having a high interruption resistance according to the first or second embodiment of the present invention is located in FIG.

In the above description, the gate electrode of the unit GTO and the GT
Although it has been stated that the unit GTO having a high interruption resistance is arranged in the ring having a small resistance value between O and the gate extraction electrode 91, that is, in the ring on the inner peripheral side in the case of the center gate structure, the unit GTO having a high interruption resistance is arranged. By arranging the pellets on the entire surface of the pellets, it is possible to improve the interruption resistance of the entire GTO pellets 90.

However, it is difficult to manufacture a unit GTO having a high interruption resistance while securing its strength and the like, and it tends to be expensive. In the structure according to the third embodiment of the present invention described above, by disposing the unit GTO having a high breaking resistance only in a part of the structure, the manufacturing is facilitated while maintaining the same effect, and the device height is improved. The price can be suppressed. Hereinafter, this will be described with reference to FIG.

FIG. 10 is a diagram for explaining the anode current waveform of each ring of the GTO at the time of turn-off. This figure shows the anode current waveform 12 of each ring of the GTO at turn-off.
Simulation waveforms by the inventors of 5 to 128,
The horizontal axis is a time axis. In this figure, the current waveform 128 is the anode current waveform of the ring in the final current concentration region, and the current waveforms 127 to 12
5 is the anode current waveform of the ring located at a position far from the final current concentration region.

At time 0, the external control circuit causes the GT
Suppose O has started to turn off. As shown in FIG. 10, the current waveforms 125, 126, 127, and 128 are formed in the order in which the turn-off ends early in each ring. The anode current 128 of the ring in the final current concentration region is the unit G
It is the maximum even when converted to TO. Then, at the final stage of turn-off, the anode currents 125 to 127 of the other rings have not flowed.

From the above, it is understood that the interruption withstand capability of the GTO is determined by the interruption withstand capability of the unit GTO in the final current concentration region. Therefore, by arranging the unit GTO having a high interruption withstand capability in the region 120 which is the final concentration region of the main current at turn-off, the same effect as when all the unit GTOs on the GTO are made into the unit GTO having a high interruption withstand capability is obtained. Obtainable. At this time, the anode current 1 of the other ring
The breaking tolerance of the unit GTO in the region where 25 to 127 flows is
It is necessary to have a size capable of cutting off the peak value of each anode current converted into unit GTO.

Next, the production of the final current concentration region at the intended position in the GTO pellet will be described.

In order to form the final current concentration region in the GTO pellet at an intended position, the width of the n-type emitter layer of the unit GTO arranged in the region to be the final current concentration region is set to
There are methods such as making the width larger than the width of the n-type emitter layer of the unit GTO in the other region, or shortening the carrier lifetime in the region where it is desired to turn off earlier to reduce the excess carrier amount. Of these, the width of the n-type emitter layer of the unit GTO to be arranged in the region to be the final current concentration region is made larger than the width of the n-type emitter layer of the unit GTO in the other region so that the final current concentration region is located at the intended position. The method of making will be described with reference to FIG.

FIG. 11 is a sectional view for explaining the structure of the unit GTO in the inner peripheral portion and the unit GTO in the outer peripheral portion.

FIG. 11 schematically shows the unit GTO 111 in the inner peripheral portion, the unit GTO 112 in the outer peripheral portion, and the gate lead-out electrode 91 of the GTO. Inner peripheral unit GTO1
11 and the gate lead-out electrode 91 of the GTO are connected with a low resistance because the distance between them is short. Unit GT on the outer periphery
Since the O112 and the gate lead-out electrode 91 of the GTO have a long distance, they are connected to each other through a path having the resistance component 115.

In the above structure, the unit GTO of the inner peripheral portion
If 111 and the unit GTO 112 in the outer peripheral portion have the same structure, extraction of excess carriers from the p-type base layer 7 of each unit GTO is performed in the unit GTO 1 in the outer peripheral portion.
It is delayed by about 12, and the final current concentration region is located in the outer peripheral portion.

However, as shown in FIG. 11, the width of the n-type emitter layer 7 is made wider as much as the unit GTO 111 in the inner peripheral portion, and the lateral resistances 109 and 110 between the gate and the cathode are influenced by the resistance component 115 of the path. And the lateral resistance 109 of the unit GTO 111 in the inner peripheral portion is made larger than the lateral resistance 110 of the unit GTO 112 in the outer peripheral portion so that the final current concentration region is formed in the inner peripheral portion of the GTO pellet. be able to.

The fourth embodiment of the present invention uses the structure of the unit GTO described with reference to FIG.
In the region near the gate extraction electrode of the O pellet, the unit GT having the structure according to the first and second embodiments of the present invention described above.
A unit GTO in which O is arranged and the width (one width divided into two) of the n-type emitter layer of the unit GTO is arranged in another region.
The width of the n-type emitter layer is, for example, twice or more.

According to the fourth embodiment of the present invention as described above, the gate avalanche current described above can be efficiently extracted from the final current concentration region, and the unit GTO in the final current concentration region is cut off. GTO due to high tolerance
It is possible to improve the breaking resistance of the.

FIG. 12 shows the G according to the fifth embodiment of the present invention.
It is a top view explaining the composition of a TO pellet, and is what looked at GTO pellet 90 from the principal plane.

In the fifth embodiment of the present invention, the main current final concentration region (where the unit GTO having a high interruption withstand capability is arranged) at the time of turn-off in the above-described third embodiment of the present invention is formed as a GTO pellet. It is located in the center. In FIG. 12, an inner region 100 (1 shown in FIG.
A ring (corresponding to a ring) can be formed with a short distance between the unit GTOs in the region and relatively easily with uniform characteristics while suppressing variations in manufacturing process (each size, sheet resistance value, etc.). On the other hand, the outer region 101 (corresponding to the four rings in FIG. 8) has a long in-region distance and it is difficult to make the characteristics uniform. The variation in the characteristics of the unit GTO in the outer ring due to this becomes more remarkable as the diameter increases and the number of rings increases.

In the fifth embodiment of the present invention, the inner region 1 capable of forming a unit GTO having relatively uniform characteristics is used.
00, the final concentrated region of the main current at turn-off is positioned as described in the third embodiment. As a result, in the GTO according to the fifth embodiment of the present invention, the characteristics of the unit GTOs arranged in the final concentrated current region can be made uniform, and the final concentrated current sharing among the unit GTOs in the region can be made uniform. can do.

According to the fifth embodiment of the present invention described above, since the characteristics of the unit GTO in the final current concentration area can be made uniform, the unit GTO in the final current concentration area can be made uniform.
The final concentrated currents are evenly distributed among the GTO pellets 90, and the interruption resistance of the entire GTO pellet 90 can be further improved.

The third to fifth embodiments of the present invention described above have been described by applying the present invention to the GTO.
The present invention is not limited, and can be applied to a semiconductor device having a large diameter in which a plurality of unit semiconductor elements are arranged on a semiconductor device and these are operated in parallel.

[0089]

As described above, according to the present invention, the final current concentration region at the time of turn-off of a unit semiconductor device such as a unit GTO can be expanded, and the breaking resistance of the unit semiconductor device can be improved by the pressure welding. It can be realized without being adversely affected by.

Further, according to the present invention, in a semiconductor device having a large diameter, a pellet structure in which the gate avalanche current is efficiently extracted from the final current concentration region can be formed, so that the breaking resistance of the semiconductor device is improved. You can

Further, according to the present invention, as described above, since it is possible to provide a semiconductor device having an improved breaking capability, it is possible to reduce the size of a peripheral circuit such as a snubber circuit of a power converter using the semiconductor device. Therefore, the size and cost of the power conversion device can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a unit GTO according to a first embodiment of the present invention.

FIG. 2 is a top view of the unit GTO shown in FIG.

FIG. 3 is a characteristic diagram for explaining an experimental result of interruption withstand capability of unit GTO.

FIG. 4 is a sectional view showing a structure of a unit GTO according to a second embodiment of the present invention.

5 is a top view of the unit GTO shown in FIG. 4. FIG.

FIG. 6 is a diagram showing waveforms of a cathode current, an anode-cathode voltage, and a gate current of the GTO at the time of turn-off with time as the horizontal axis.

FIG. 7 is a diagram illustrating a relationship between a gate avalanche current and a withstand voltage (breaking limit current under the same voltage).

FIG. 8 is a plan view illustrating the configuration of a GTO pellet to which the third embodiment of the present invention is applied.

FIG. 9 is a plan view illustrating the structure of a GTO pellet according to a third embodiment of the present invention.

FIG. 10 is a diagram illustrating an anode current waveform of each ring of the GTO at turn-off.

FIG. 11 is a cross-sectional view illustrating a structure of an inner peripheral unit GTO and an outer peripheral unit GTO.

FIG. 12 is a plan view illustrating the structure of a GTO pellet according to a fifth embodiment of the present invention.

FIG. 13 is a diagram showing an example of a snubber circuit.

FIG. 14 is a cross-sectional view showing an example of a structure of a general unit GTO according to a conventional technique.

FIG. 15 is a top view of the unit GTO of FIG.

FIG. 16 is a unit G according to the related art in which the breaking resistance is increased.
It is sectional drawing which shows the structure of TO.

FIG. 17 is a diagram schematically showing two unit GTOs connected in parallel.

FIG. 18 is a diagram schematically showing two unit GTOs provided with a floating gate in each unit GTO, short-circuiting them in the GTO, and connected in parallel.

[Explanation of symbols]

 1 semiconductor substrate 2 cathode electrode 3a, 3b gate electrode 4 anode electrode 5 p-type emitter layer (pE) 6 n-type base layer (nB) 7 p-type base layer (pB) 8 n-type emitter layer (nE) 9 anode terminal 10 Cathode terminal 11 Gate terminals 20, 21 are units GTO 30a, 30b Floating gate electrode 61 Insulating layer 91 Gate extraction electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hidekatsu Onose, 3-1-1, Saiwai-cho, Hitachi-shi, Ibaraki Hitachi Incorporated Hitachi, Ltd. Hitachi factory (72) Satoshi Matsuyoshi 3-chome, 1-cho, Hitachi-shi, Ibaraki No. 1 Hitachi Ltd. Hitachi factory

Claims (7)

[Claims] 1. At least three semiconductor layers having different conductivity types are formed adjacent to each other between a pair of main planes of a semiconductor substrate, and the first semiconductor layer of the three semiconductor layers has a substantially constant width. The second semiconductor layer has an elongated shape, and
The semiconductor layer is exposed to the first main surface of the semiconductor substrate together with the first semiconductor layer so as to surround the semiconductor layer, and is exposed to the first semiconductor layer.
In a semiconductor device in which a main electrode is in low-resistance contact and a control electrode is in low-resistance contact with the second semiconductor layer, an insulating region is provided in the widthwise center of the first semiconductor layer, and the first main electrode is the insulating layer. A semiconductor device, wherein two first semiconductor layers divided into two regions are in low-resistance contact across the insulating region. 2. A conductive region is provided between the second semiconductor region and the insulating region on the opposite side of the first main electrode across the insulating region of the insulating region. A semiconductor device characterized by the above. 3. At least three semiconductor layers having different conductivity types are formed adjacent to each other between a pair of main planes of a semiconductor substrate, and the first semiconductor layer of the three semiconductor layers has a substantially constant width. One or more juxtaposed to the first main surface of the semiconductor body having an elongated shape, the second semiconductor layer together with the first semiconductor layer so as to surround the first semiconductor layer, and the first main surface of the semiconductor body. A structure in which a first main electrode is in low-resistance contact with each of the first semiconductor layers and a control electrode is in low-resistance contact with each of the second semiconductor layers is a unit semiconductor element, and the unit semiconductor element is exposed. In a semiconductor device in which a plurality of unit semiconductor elements are connected in parallel and each control electrode of the unit semiconductor element is connected to a control terminal provided on the semiconductor substrate, the plurality of unit semiconductor elements are arranged in the center in the width direction of the first semiconductor layer. Insulating region is provided, and the first main An electrode insulates two first semiconductor layers divided into two by the insulating region into a first unit semiconductor element in low-resistance contact across the insulating region, and insulates in the widthwise center of the first semiconductor layer. A semiconductor device comprising a second unit semiconductor element having no region. 4. The first unit semiconductor element includes the first semiconductor layer between the insulating region and a second semiconductor region opposite to the first main electrode across the insulating region of the insulating region. The semiconductor device according to claim 1, having a structure in which a conductive region is provided in an insulated state. 5. The first unit semiconductor element is the second unit semiconductor element.
5. The semiconductor device according to claim 3, wherein the semiconductor device is arranged in a region near the control terminal with respect to the unit semiconductor element. 6. The control terminal is arranged in the center of a semiconductor substrate having a circular shape, and the first unit semiconductor element is
6. The semiconductor device according to claim 3, wherein the semiconductor device is arranged in the central portion of the semiconductor substrate around the control element. 7. A power conversion device comprising a switching element for controlling the flow and interruption of a current supplied from a power source to a load based on a command from a control means, wherein the switching element is one of the switching elements. A power conversion device using the semiconductor device described in 1.