JPH09213970A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a silicide layer uniformly on a source area and a drain area on a thin-film transistor. SOLUTION: A metallic film 28 which can be changed into silicide is formed over a semiconductor thin film 25 and a channel protection film 26a, and an ion is implanted into the film 25 by using the film 26a as a mask, thereby forming a silicide layer on the surface of the film 25 in such an area excluding the lower side of the film 26a by an ion implanting energy generating at this time. Thus, the energy during implantation of energy is utilized, so that the silicide layer can be formed securely and uniformly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a silicide layer.

[0002]

2. Description of the Related Art For example, in a thin film transistor (semiconductor device) used as a switching element of an active matrix liquid crystal display device, a silicide layer is formed on a source region and a drain region in order to reduce a sheet resistance and increase an ON current. There are some with. Next, an example of manufacturing such a conventional thin film transistor will be described with reference to FIGS. 18 to 21 in order. First, as shown in FIGS. 18A and 18B, a gate electrode 2 and a gate line 3 made of chromium are formed on a predetermined portion of the upper surface of a transparent substrate 1 made of glass or the like, and silicon nitride is formed on the upper surface thereof. A gate insulating film 4 is formed, a semiconductor thin film 5 made of single crystal silicon, amorphous silicon, polysilicon or the like is formed on the upper surface of the gate insulating film 4, and silicon nitride is formed on the upper surface of the semiconductor thin film 5 at a predetermined position on the gate electrode 2. Then, the channel protection film 6 is formed. Next, when ions such as phosphorus and boron are implanted, ion implantation regions 5a are formed in the semiconductor thin film 5 in regions other than below the channel protective film 6.

Next, as shown in FIGS. 19A and 19B, a silicidable metal film 7 made of chromium or the like is formed on the entire upper surface, and a photoresist pattern 8 is formed on the device region on the upper surface. Form. In this case, the photoresist pattern 8 is formed such that the channel protection film 6 is formed in a crotch shape and forms a substantially cross shape with the channel protection film 6. A silicide layer 9 is provided between the metal film 7 and the semiconductor thin film 5.
Is formed. Next, using the photoresist pattern 8 as a mask, the metal film 7, the silicide layer 9 and the semiconductor thin film 5 are formed.
Is etched, it becomes as shown in FIGS. 20 (A) and 20 (B). That is, the metal film 7 remains only under the photoresist pattern 8, the silicide layer 9 remains only under the photoresist pattern 8, and the semiconductor thin film 5 remains only thereunder and under the channel protective film 6. In this state, the portion below the channel protective film 6 of the semiconductor thin film 5 is a channel region 5b made of an intrinsic region, and both sides thereof are respectively the ion implantation regions 5a.
And a source region 5c and a drain region 5d. After that, the photoresist pattern 8 and the metal film 7 are removed.

Next, as shown in FIGS. 21A and 21B, a pixel electrode 10 made of ITO is formed at a predetermined position on the upper surface. Next, a source electrode 11, a drain electrode 12, and a drain line 13 made of an aluminum-titanium alloy are formed at predetermined locations on the upper surface. In this state, the pixel electrode 10 is connected to the source region 5c of the semiconductor thin film 5 via the silicide layer 9 and the source electrode 11, and the drain electrode 5 is connected to the drain region 5d via the silicide layer 9.
Is connected. Thus, a thin film transistor having the silicide layer 9 on the source region 5c and the drain region 5d is manufactured.

[0005]

However, in such a conventional method of manufacturing a thin film transistor, it is necessary to clean the surface of the semiconductor thin film 5 before forming the metal film 7 in the step shown in FIG. is there. That is, since a natural oxide film is formed on the surface of the semiconductor thin film 5, even if the metal film 7 is formed thereon, the silicide layer 9 cannot be formed. Therefore, it is necessary to remove the natural oxide film by performing a surface treatment with ammonium fluoride, but since the semiconductor thin film such as silicon has water repellency, dry islands are removed in the drying process of the cleaning liquid after removing the natural oxide film. Occurs. Therefore, in the conventional method of forming a silicide layer, a formation failure of the silicide layer occurs, and the silicide layer cannot be formed reliably and uniformly. Further, as shown in FIG. 19, since the metal film 7 is formed on the entire upper surfaces of the semiconductor thin film 5 and the channel protective film 6, a silicide layer is formed on the entire upper surface of the semiconductor thin film 5 in a region other than under the channel protective film 6. 9 will be formed. Therefore, when the device region is formed in the step shown in FIG. 20, the unnecessary silicide layer 9 in the region other than the device region is removed, but there is a problem that this removal is difficult. That is, if the unnecessary silicide layer 9 can be removed by dry etching using CCl ₄ gas, it can be easily removed, but it is difficult to remove it under the present circumstances where CCl ₄ gas cannot be used due to regulations. A first object of the present invention is to reliably and uniformly form a silicide layer. A second object of the present invention is to prevent an unnecessary silicide layer from being formed.

[0006]

According to the first aspect of the present invention,
A metal film capable of silicidation is formed on the semiconductor thin film,
Ions containing a donor or acceptor impurity are implanted into the semiconductor thin film from above the metal film, the donor or acceptor impurity is implanted into the semiconductor thin film, and a silicide layer is formed at the interface between the metal film and the semiconductor thin film. Are formed uniformly. According to a second aspect of the present invention, a metal film capable of silicidation is formed on a predetermined region of the semiconductor thin film, and ions containing a donor or acceptor impurity are implanted into the semiconductor thin film from above the metal film to form the semiconductor thin film. The donor or acceptor impurity is implanted therein, and a silicide layer is uniformly formed at the interface between the metal film and a predetermined region of the semiconductor thin film. According to a third aspect of the present invention, a semiconductor thin film is formed on a substrate to remove an oxide film on the surface of the semiconductor thin film, and a metal film capable of silicidation is formed on the semiconductor thin film. Ions containing a donor or acceptor impurity are implanted into the semiconductor thin film from above, the donor or acceptor impurity is implanted into the semiconductor thin film, and a silicide layer is uniformly formed at the interface between the metal film and the semiconductor thin film. It is something that is done.

According to the first to third aspects of the present invention, there is provided a method of forming a silicidable metal film on a semiconductor thin film, implanting ions, and forming a silicide layer at an interface between the metal film and the semiconductor thin film. Yes, unlike the conventional method, because the silicidation is performed using the energy at the time of ion implantation,
The contact resistance can be reduced by making the silicide layer uniform. In addition, according to the second aspect of the present invention, since a metal film capable of silicidation is formed only on a predetermined region of the semiconductor thin film and ions are implanted, the surface of the semiconductor thin film outside the predetermined region is not covered. The silicide layer is not formed,
Therefore, the work required to remove the silicide is unnecessary, and the efficiency can be improved. Further, according to the third aspect of the present invention, since the method of forming the metal film capable of silicidation after removing the oxide film on the surface of the semiconductor thin film, silicidation can be reliably performed.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIGS. 1 to 8 show respective manufacturing steps in a first embodiment of a method of manufacturing a thin film transistor to which the present invention is applied. Therefore, the method of manufacturing the thin film transistor according to the first embodiment will be described with reference to these drawings in order.

First, as shown in FIGS. 1A and 1B,
A gate electrode 22 and a gate line 23 made of chromium or the like are formed in a predetermined position on the upper surface of a transparent substrate 21 made of glass or the like to have a film thickness of about 1000Å. Next, a gate insulating film 24 made of silicon nitride is formed on the entire upper surface to a thickness of 400.
A semiconductor thin film 25 made of single crystal silicon, amorphous silicon, polysilicon or the like after being formed to a film thickness of about 0 Å
Is formed to a film thickness of about 500Å, and then a channel protective film forming film 26 made of silicon nitride is formed.

Next, as shown in FIGS. 2 (A) and 2 (B),
A photoresist pattern 27 is formed on the upper surface of the channel protective film forming film 26 at a predetermined position on the gate electrode 22. In this case, the photoresist pattern 27 has a back surface exposure (exposure from the lower surface side of the transparent substrate 21) using the gate electrode 22 and the gate line 23 as a mask, and a front surface exposure (from the upper surface side of the transparent substrate 21) using a photomask. Exposure). Then, the length L of the photoresist pattern 27 in the channel length direction is determined by the gate electrode 22.
Is the same as the width of.

Next, when the channel protective film forming film 26 is wet-etched using the photoresist pattern 27 as a mask, as shown in FIGS. 3A and 3B, a channel protective film 26a is formed under the photoresist pattern 27. It is formed. In this case, the surface of the semiconductor thin film 25 in the region other than under the channel protective film 26a is exposed, so that a natural oxide film (not shown) is formed on this exposed surface. After that, the photoresist pattern 27 is removed.

Next, as shown in FIGS. 4 (A) and 4 (B),
A silicidable metal film 28 made of chromium or the like is formed on the entire upper surface by sputtering, plasma CVD, or the like. The film thickness of the metal film 28 is thin enough to allow the passage of ions, and is about 50 to 200Å. By the way, in this state, since the natural oxide film is formed on the surface of the semiconductor thin film 25 in the region other than under the channel protective film 26a, the silicide layer is not formed between the semiconductor thin film 25 and the metal film 28.

Next, as shown in FIGS. 5 (A) and 5 (B),
Using the channel protective film 26a as a mask, ions containing a donor impurity such as phosphorus and an acceptor impurity such as boron that make the semiconductor thin film 25 n-type or p-type are implanted. The implanted ions penetrate the metal film 28 and are injected into the semiconductor thin film 25 in a region other than under the channel protective film 26a, so that an ion-implanted region 25a is formed. The ion-implanted region 25a includes portions to be a source region and a drain region of a thin film transistor described later. Further, due to the ion implantation energy at this time, metal (chromium) is injected from the metal film 28 into the natural oxide film formed on the surface of the semiconductor thin film 25 in the region other than under the channel protective film 26a and the semiconductor thin film 25 therebelow. , Semiconductor thin film 2
A silicide layer 29 is formed between the metal layer 5 and the metal film 28.

Thus, since the silicidation is performed by the energy at the time of implanting the ions, the silicide layer 29 can be formed surely and uniformly. Even if the natural oxide film is formed on the surface of the semiconductor thin film 25, the silicide layer 29 can be formed on the surface of the semiconductor thin film 25 in the region other than under the channel protective film 26a by the ion implantation energy. It is not necessary to perform the surface treatment for removing the natural oxide film on the surface of the semiconductor thin film 25 before forming the film 28. Therefore, the number of steps can be reduced accordingly.

Here, as an example, 5% of PH ₃ and 95
% H ₂ doping gas with accelerating voltage of 20 k
After implantation with V and a dose amount of 2 × 10 ¹⁵ / cm ² , the metal film 28 was removed and the sheet resistance of the silicide layer 29 was measured to be about 1100 Ω / □. On the other hand, in the case of the conventional silicide layer 9 shown in FIG. 19B, for example, the sheet resistance was about 12000 Ω / □. As is clear from this measurement result, the low-resistance silicide layer 2 is formed on the surface of the semiconductor thin film 25 in the region other than under the channel protective film 26a by the ion implantation energy.
It is understood that 9 is formed.

Further, 1% which is an etching solution for silicon
When the sheet resistance between the silicide layer 29 in the case of the first embodiment and the silicide layer 9 in the case of the conventional example was measured by immersing in the hydrofluoric acid for 30 seconds, it was about 1100Ω / □ in the case of the first embodiment. However, in the case of the conventional example, it was considerably large, 5 × 10 ¹¹ Ω / □ or more. As is clear from this measurement result, the silicide layer 29 in the first embodiment is the silicide layer 9 in the conventional example.
It is understood that it is more precise and tougher (stable) than. In the case of the first embodiment, the dose amount is 4 × 10 ¹⁵ / cm ^2.
As a result, the sheet resistance of the silicide layer 28 is 570.
The resistance was even lower, around Ω / □.

As described above, the silicidable metal film 2
When ions are implanted in the semiconductor thin film 25 via the metal film 28 and the semiconductor thin film 25 by the ion implantation energy.
It was confirmed that a good contact state was obtained by the growth of silicide in the native oxide film that existed between and. This is not limited to the case of a natural oxide film, and the same applies to an oxide film formed on the semiconductor thin film 25 by performing an oxidation treatment with a resist solution or oxygen plasma. Therefore, a semiconductor thin film on which a natural oxide film is formed is formed. The metal film 28 may be formed after the oxidation treatment of 25. However, as shown in the third embodiment described later, the silicide layer 28 may be formed more uniformly by implanting ions after etching the oxide film of the semiconductor thin film 25.

Next, as shown in FIGS. 6 (A) and 6 (B),
A photoresist pattern 30 is formed on a predetermined portion of the upper surface, that is, a device region by surface exposure using a photomask. In this case, the photoresist pattern 30 is formed so that the gate electrode 22 is formed in a crotch shape and forms a substantially cross shape with the gate electrode 22, and the width D thereof is the same as the desired channel width. Next, when the metal film 28, the silicide layer 29, and the semiconductor thin film 25 are dry-etched using the photoresist pattern 30 as a mask, FIG.
(A) and (B) are obtained.

That is, the metal film 28 remains only under the photoresist pattern 30, and the silicide layer 29 remains only under the photoresist pattern 30.
The semiconductor thin film 25 remains only below. In this state,
A portion of the semiconductor thin film 25 below the channel protection film 26a is a channel region 25b formed of an intrinsic region, and both sides thereof are a source region 25c formed of an ion implantation region 25a.
And a drain region 25d. After that, the photoresist pattern 30 and the metal film 28 are removed.

Next, as shown in FIGS. 8 (A) and 8 (B),
A pixel electrode 31 made of ITO is formed at a predetermined position on the upper surface so as to have a film thickness of about 500Å. Next, a source electrode 32, a drain electrode 33, and a drain line 34 made of an aluminum-titanium alloy are formed on a predetermined portion of the upper surface with a film thickness of 3000.
Formed to about Å. In this state, the silicide layer 29 and the source electrode 3 are formed in the source region 25c of the semiconductor thin film 25.
2 is connected to the pixel electrode 31 via the drain region 25.
The drain electrode 32 is connected to d via the silicide layer 29. Thus, the thin film transistor of the first embodiment is manufactured.

By the way, in the first embodiment, as shown in FIG. 5, the semiconductor thin film 25 and the channel protective film 26.
Since the ions are implanted with the metal film 28 formed on the entire upper surface of a, the silicide layer 29 is also formed on the surface of the semiconductor thin film 25 in regions other than the device region. As a result, when the device region is formed in the step shown in FIG. 7, it becomes difficult to remove the unnecessary silicide layer 29 in the region other than the device region.

(Second Embodiment) Next, a second embodiment of the present invention which can solve the above problems will be described with reference to FIGS. 9 to 12 in order. In the embodiment, the steps up to the step shown in FIG. 4 of the first embodiment are the same, so the steps after that will be described. After the step shown in FIG. 4, as shown in FIGS. 9A and 9B, a photoresist pattern 30 is formed by surface exposure on a predetermined portion of the upper surface, that is, a device region. Next, when the metal film 28 is dry-etched using the photoresist pattern 30 as a mask, FIGS.
As shown in, the metal film 28 remains only under the photoresist pattern 30. Then, the photoresist pattern 30 is removed.

Next, as shown in FIGS. 11A and 11B, the semiconductor thin film 2 is formed using the channel protective film 26a as a mask.
Ions are implanted containing phosphorus, boron, or the like to make 5 n-type or p-type. The implanted ions penetrate the metal film 28 where the metal film 28 is present, and are directly injected into the semiconductor thin film 25 in a region other than below the channel protective film 26a where the metal film 28 is not present, and the ion implantation region is formed. 25a is formed. Further, due to the ion implantation energy at this time, metal (chromium) is injected from the metal film 28 into the natural oxide film formed on the surface of the semiconductor thin film 25 in the region other than under the channel protective film 26a and the semiconductor thin film 25 therebelow. A silicide layer 29 is formed between the metal film 28 remaining around the channel protection film 26a and the semiconductor thin film 25.

Next, using the metal film 28, the silicide layer 29 and the channel protection film 26a as a mask, the semiconductor thin film 25 is formed.
Is dry-etched, the semiconductor thin film 25 remains only under the metal film 28 and the channel protection film 26a, as shown in FIGS. In this state, the portion of the semiconductor thin film 25 below the channel protective film 26a is a channel region 25b made of an intrinsic region, and both sides thereof are a source region 25c and a drain region 25d made of the ion-implanted regions 25a. After that, the metal film 28 is removed. Hereinafter, since the process is the same as the process shown in FIG. 8 of the first embodiment, the subsequent process is omitted.

As described above, in the second embodiment, as shown in FIG.
As shown in FIG. 0, unnecessary portions other than the device region of the metal film 28 are removed, and thereafter, as shown in FIG. 11, since the ions are implanted, the metal film 28 remaining around the channel protective film 26a. The silicide layer 29 is formed only between the semiconductor thin film 25 and the semiconductor thin film 25. That is, the metal film 2
No silicide layer is formed on the surface of the semiconductor thin film 25 in the lower region, that is, in the region other than the device region, and therefore an unnecessary silicide layer can be prevented from being formed. As a result, when the unnecessary portion of the semiconductor thin film 25 is removed by dry etching using the metal film 28, the silicide layer 29, and the channel protection film 26a as a mask, only the semiconductor thin film 25 needs to be dry etched.

Now, dry etching of the semiconductor thin film 25 will be described. First, three types of samples were prepared.
That is, as the first sample, which is the same as the case of the second embodiment, for example, referring to FIG. 11B, the silicon nitride film (2) is formed on the upper surface of the glass substrate (21).
4) and a silicon film (25) are formed, a chromium film (28) is formed on a part of the upper surface of the natural oxide film formed on the surface of the silicon film (25), and ions are implanted in this state, A silicide layer was formed only on the surface of the silicon film below the chromium film (28) formed in the portion, and then the chromium film (28) was removed to prepare a material. As the second sample,
A silicon nitride film and a silicon film are formed on the upper surface of the glass substrate, a chromium film is formed on the entire upper surface of the natural oxide film formed on the surface of the silicon film, and ions are implanted in this state to form the entire surface of the silicon film. A silicide layer was formed and then the chromium film was removed to prepare a material. A third sample was prepared by forming a silicon nitride film and a silicon film on the upper surface of a glass substrate and implanting ions in this state (in this case, since the chrome film is not formed, the silicide layer is Not formed.).

Then, for the first, second and third samples,
Plasma etching was performed using a mixed gas of Cl and SF ₆ . Then, in the case of the first sample, all of the silicon film in the region other than below the silicide layer formed on a part of the surface of the silicon film was removed. In the case of the second sample, two phenomena appeared. First, the etching hardly progressed (this second sample is out of the problem and is removed). The other is that the silicide layer formed on the entire surface of the silicon film and the silicon film below it were all removed (hereinafter referred to as the second sample a). Third
In the case of the sample, the silicon film was completely removed.

Next, an ITO film (corresponding to the pixel electrode 31 in FIG. 8) is formed on each upper surface of the first sample, the second sample a and the third sample, and a silicon nitride film (the gate insulating film 24 in FIG. 8) is formed. The sheet resistance and the like of the ITO film formed thereon were examined. Then, in the case of the first sample and the third sample, the sheet resistance of the ITO film was about 45Ω / □, which was almost the same value. On the other hand, in the case of the second sample a, ITO
The film is cloudy, its sheet resistance is extremely high,
Some of them were also broken. This is because the surface of the silicon nitride film under the ITO film is rough.

From the above, in the case of the second embodiment, as shown in FIG. 11, when ions are implanted and thereafter unnecessary portions of the semiconductor thin film 25 are removed, Cl and SF are added.
_When the plasma etching using the mixed gas of ₆ is performed, all of the semiconductor thin film 25 in the region other than under the metal film 28 is removed, and the gate insulating film 24 exposed by this removal is removed.
It is understood that the pixel electrode 31 is well formed on top.

By the way, in the case of the second embodiment,
As shown in FIG. 3, a channel protection film 26a is formed, the photoresist pattern 27 is removed thereafter, and then the channel protection film 26a is formed.
0, the metal film 28 is left only in the device region, and then, as shown in FIG. 11, only between the metal film 28 and the semiconductor thin film 25 remaining around the channel protection film 26a by the ion implantation energy. The silicide layer 29 is formed. However, as shown in FIG. 3, when the channel protection film 26a is formed and then the photoresist pattern 27 is removed, oxidation by a resist solution or the like progresses and the oxide film formed on the surface of the semiconductor thin film 25 is removed. The thickness may become too thick. When such a phenomenon occurs, silicidation may be insufficient with ion implantation energy.

For example, as the fourth sample, which is the same as in the case of the second embodiment, for example, referring to FIG. 11B, a silicon nitride film (24) is formed on the upper surface of the glass substrate (21). And a silicon film (25), and a channel protection film (26) is formed on a part of the upper surface of the silicon film (25).
a) was formed, a chromium film (28) was formed on the entire upper surface without surface treatment, ions were implanted in this state, and then the chromium film (28) was removed to prepare a film. As a fifth sample, a silicon nitride film and a silicon film were formed on the upper surface of a glass substrate, a channel protective film was formed on a part of the upper surface of the silicon film, and a chromium film was formed on the entire upper surface with surface treatment. In this state, ions were implanted, and then the chromium film was removed to prepare a product. As a sixth sample, a silicon nitride film and a silicon film were formed on the upper surface of the glass substrate,
A chromium film is formed on the upper surface of the silicon film without surface treatment,
In this state, ions were implanted, and then the chromium film was removed was prepared (in this case, since the channel protective film was not formed, the oxidation by the resist solution or the like did not proceed).

However, for the ion implantation in the fourth, fifth and sixth samples, a doping gas consisting of 1% PH ₃ and 99% H ₂ was used for accelerating voltage 20 kV and dose 2 × 10 ^15.
I hit it in / cm ² . Then, the sheet resistance of each of the silicide layers of the fourth, fifth, and sixth samples was measured and found to be about 1 × 10 ⁶ Ω / □ in the case of the fourth sample. In the case of the sample, it was about 1 × 10 ³ Ω / □. That is, in the case of the fourth sample, the fifth sample and the sixth sample
The sheet resistance of the silicide layer cannot be made sufficiently low as compared with the sample. This is because in the case of the fourth sample, the oxidation by the resist solution when removing the photoresist pattern after forming the channel protective film proceeds, and the thickness of the oxide film formed on the surface of the silicon film becomes too thick. ,
This is due to insufficient silicidation with ion implantation energy. In the case of the fifth sample, after the surface treatment, it was left in a normal environment for 2 hours or more to allow natural oxidation to proceed. However, as described above, the sheet resistance of the silicide layer was 1 × 10 ³ Ω / □ The resistance was low. Therefore,
Considering the progress of oxidation by the resist solution and the like, it is desirable to perform the surface treatment even if the number of steps is increased.

However, in the case of the fifth sample, the silicon nitride film and the silicon film are formed on the upper surface of the glass substrate, the channel protective film is formed on a part of the upper surface of the silicon film, and the surface treatment is performed on the entire upper surface. Since the chrome film is formed, the silicide layer is also formed on the surface of the silicon film in the region other than the device region, which makes it difficult to remove the silicide layer. In addition, in the case of the second embodiment, after removing the photoresist pattern 27 shown in FIG. 3, it is washed with water and dried. At this time, the surface of the semiconductor thin film 25 in the region other than under the channel protective film 26a is exposed. In addition, since silicon, which is the material of the semiconductor thin film 25, has water repellency, the semiconductor thin film 25
In some cases, contaminants may be locally generated on the surface of the semiconductor due to poor drying, and removal of unnecessary portions of the semiconductor thin film 25 may be insufficient.

(Third Embodiment) Next, a third embodiment of the present invention which can solve the above problems will be described with reference to FIGS. 13 to 17 in order. In the embodiment, the steps up to the step shown in FIG. 3 of the first embodiment are the same, so the steps after that will be described. First, as shown in FIGS. 3A and 3B, a channel protection film 26a is formed, and then the photoresist pattern 27 is removed. Next, it is washed with water and dried. In this case, contaminants may be locally generated on the surface of the semiconductor thin film 25 due to poor drying. Next, surface treatment with ammonium fluoride or the like is performed to remove the oxide film on the surface of the semiconductor thin film 25.

Next, as shown in FIGS. 13A and 13B, a silicidable metal film 28 made of chromium or the like is formed on the entire upper surface. In this case, since the oxide film on the surface of the semiconductor thin film 25 has been removed, the silicide layer 29 is formed between the semiconductor thin film 25 and the metal film 28. Next, as shown in FIGS. 14A and 14B, a photoresist pattern 30 is formed on a predetermined portion of the upper surface, that is, a device region.
Are formed by surface exposure. Next, when the metal film 28 is wet-etched using the photoresist pattern 30 as a mask, as shown in FIGS. 15A and 15B, the metal film 28 remains only under the photoresist pattern 30. Then, the photoresist pattern 30 is removed.

Next, as shown in FIGS. 16A and 16B, the semiconductor thin film 2 is formed using the channel protective film 26a as a mask.
Ions are implanted containing phosphorus, boron, or the like to make 5 n-type or p-type. The implanted ions penetrate the metal film 28 where the metal film 28 is present, and are directly injected into the semiconductor thin film 25 in a region other than below the channel protective film 26a where the metal film 28 is not present, and the ion implantation region is formed. 25a is formed. By the ion implantation energy at this time,
Similar to the first and second embodiments, the metal film 28
A silicide layer is formed on the boundary surface between the semiconductor thin film 25 and the semiconductor thin film 25. In this case, in this embodiment, as shown in FIG.
Although the silicide layer has already been formed as described in (B), it can be more reliably formed by silicidation utilizing the energy at the time of ion implantation. That is, even if the silicide layer formed when the metal film 28 is formed on the upper surface of the semiconductor thin film 25 is non-uniform due to the dry island of the cleaning liquid, it is uniform by the silicidation utilizing the energy due to this ion implantation. It will be Further, the ion implantation energy at this time appropriately blows off the silicide layer 29 formed on the surface of the semiconductor thin film 25 in the region other than under the metal film 28, contaminants due to poor drying, and the like due to this silicide layer 29 and poor drying. The contaminants are sparse. This allows
The surface side of the semiconductor thin film 25 in the region other than under the metal film 28 is in a state of being easily etched.

Next, the metal film 28 and the channel protective film 2
When plasma etching is performed using a mixed gas of Cl and SF ₆ with 6a as a mask, the semiconductor thin film 25 in the region other than under the metal film 28 and under the channel protective film 26a remains sparsely on the surface of the silicide layer 29. 17A and 17B, the semiconductor thin film 25 remains only under the metal film 28 and the channel protection film 26a, as shown in FIGS. In this state, the portion of the semiconductor thin film 25 below the channel protective film 26a is a channel region 25b made of an intrinsic region, and both sides thereof are a source region 25c and a drain region 25d made of the ion-implanted regions 25a. After that, the metal film 28 is removed. Hereinafter, since the process is the same as the process shown in FIG. 8 of the first embodiment, the subsequent process is omitted.

As described above, in the third embodiment, sufficient silicidation can be achieved, and even if the silicide layer 29 or the like is formed on the surface of the semiconductor thin film 25 in the region other than the device region, ion implantation is performed. The surface side of the semiconductor thin film 25 in the region under the metal film 28, that is, the region other than the device region is easily etched by the energy, and the metal film 28 and the channel protective film 26a are under the condition.
The unnecessary semiconductor thin film 25 in the region other than the lower region can be easily removed together with the silicide layer 29 and the like remaining sparsely on the surface thereof.

Now, description will be given of the state where the surface side of the semiconductor thin film 25 is easily etched due to the ion implantation energy. First, as in the case of the third embodiment described above, for example, referring to FIG. 16B, the silicon nitride film (2) is formed on the upper surface of the glass substrate (21).
4) and the silicon film (25) are formed, and the silicon film (2
Forming a channel protective film (26a) on a part of the upper surface of 5), forming a chromium film (28) on the entire upper surface with surface treatment, and leaving the chromium film (28) only in the device region,
Next, as shown in FIG. 16 (B), ion implantation is performed, and then, as shown in FIG. 17 (B), when plasma etching using a mixed gas of Cl and SF ₆ is performed, the ion implantation conditions are When the completion time of plasma etching was examined, the results shown in Table 1 below were obtained.

[0040]

[Table 1] However, the gas concentration is the concentration of PH ₃ in the gas obtained by diluting PH ₃ with H ₂ gas (hereinafter, the same). The completion time is the completion time of the plasma etching, and is the time when the completion of the plasma etching performed discontinuously can be confirmed (hereinafter the same).

For comparison, when the same manufacturing process as described above was performed without surface treatment, the ion implantation conditions and the plasma etching completion time were examined, and the results shown in Table 2 below were obtained. was gotten.

[Table 2]

As is clear from Tables 1 and 2, in the case of no surface treatment, compared with the case of surface treatment,
The plasma etching completion time is short and the etching rate is low. Also, in the case of no surface treatment,
The surface of the silicon nitride film (corresponding to the gate insulating film 24 in FIG. 17) was roughened, and the glass substrate was fogged. From this, it is understood that it is better to have the surface treatment than not have it. In the case where the surface treatment is performed and the plasma etching using the mixed gas of Cl and SF ₆ is performed without implanting the ions, the plasma etching is performed by 80
Almost no change was observed in the silicide layer on the silicon film to be removed even after performing the etching for more than sec. Further, in the case where the surface treatment is not performed and the plasma etching using the mixed gas of Cl and SF ₆ is performed without performing the ion implantation, even if the plasma etching is performed for 50 seconds or more,
There was a portion of the silicide layer on the silicon film to be removed where etching was scarcely progressed. From this,
It is understood that even if there is a silicide layer on the surface of the semiconductor thin film, the surface side of the semiconductor thin film is easily etched by the ion implantation energy.

Next, the removal of contaminants due to poor drying will be described. First, as in the case of the third embodiment, as shown in FIG. 13B, after the surface treatment, a chromium film (28) is formed to form a silicide layer (29) on the surface of the semiconductor thin film (25). ) Is formed, and then a chromium film (28) is left only in the device region as shown in FIG.
Next, as shown in FIG. 16 (B), ion implantation was performed, and then, as shown in FIG. 17 (B), plasma etching was performed using a mixed gas of Cl and SF ₆ . In this case, the ion implantation is performed by using a doping gas composed of 1% PH ₃ and 99% H ₂ for an acceleration voltage of 10 kV and a dose of 2 ×.
Implanted at 10 ¹⁵ / cm ² . The plasma etching time was set to two types of 10 seconds and 20 seconds. Then, in each case, it was confirmed that the etching proceeded uniformly and was completely etched. On the other hand, when the manufacturing process similar to the above is performed without performing ion implantation, etching progresses unevenly, and microscopic stains that may be caused by contaminants due to poor drying remain. It was
From this, it is understood that even if the surface of the semiconductor thin film has contaminants due to poor drying, the surface side of the semiconductor thin film is easily etched by the ion implantation energy.

[0044]

As described above, according to the invention described in claims 1 to 3, a metal film capable of silicidation is formed on a semiconductor thin film, and ions are implanted thereinto to form an interface between the metal film and the semiconductor thin film. In this method, the silicide layer is formed by utilizing the energy at the time of ion implantation. Therefore, unlike the conventional method, the silicide layer can be made uniform and the contact resistance can be reduced. In addition, according to the second aspect of the present invention, since a metal film capable of silicidation is formed only on a predetermined region of the semiconductor thin film and ions are implanted, the metal film on the surface of the semiconductor thin film outside the predetermined region is formed. Since a silicide layer is not formed, therefore, the work required to remove the silicide is unnecessary and efficiency can be improved. Further, according to the third aspect of the present invention, since the method of forming the metal film capable of silicidation after removing the oxide film on the surface of the semiconductor thin film, silicidation can be reliably performed.

[Brief description of drawings]

FIG. 1A is a plan view showing a state in which a semiconductor thin film, a film for forming a channel protective film, and the like are formed on a transparent substrate in manufacturing the thin film transistor according to the first embodiment of the present invention, and FIG. Sectional drawing which follows the B line.

2 is a step following FIG. 1, in which (A) is a plan view, FIG.
(B) is sectional drawing which follows the BB line.

FIG. 3 is a step following FIG. 2, in which (A) is a plan view;
(B) is sectional drawing which follows the BB line.

FIG. 4 is a step following FIG. 3, in which (A) is a plan view;
(B) is sectional drawing which follows the BB line.

5 is a step following FIG. 4, in which (A) is a plan view, FIG.
(B) is sectional drawing which follows the BB line.

FIG. 6 is a step following FIG. 5, in which (A) is a plan view;
(B) is sectional drawing which follows the BB line.

FIG. 7 is a step following FIG. 6, in which (A) is a plan view;
(B) is sectional drawing which follows the BB line.

FIG. 8 is a step following FIG. 7, in which (A) is a plan view;
(B) is sectional drawing which follows the BB line.

FIG. 9 is a step following the step of FIG. 4 of the first embodiment in manufacturing the thin film transistor according to the second embodiment of the present invention, in which (A) is a plan view and (B) is a cross section taken along line BB thereof. Fig.

10 is a step following FIG. 9, in which (A) is a plan view,
(B) is sectional drawing which follows the BB line.

FIG. 11 is a step following FIG. 10, in which (A) is a plan view and (B) is a cross-sectional view taken along the line BB.

FIG. 12 is a step following FIG. 11, in which (A) is a plan view and (B) is a cross-sectional view taken along the line BB.

FIG. 13 is a step following the step of FIG. 3 of the first embodiment in manufacturing the thin film transistor according to the third embodiment of the present invention, in which (A) is a plan view and (B) is a cross section taken along line BB thereof. Fig.

FIG. 14 is a step following FIG. 13, in which (A) is a plan view and (B) is a cross-sectional view taken along the line BB.

FIG. 15 is a step following FIG. 14, in which (A) is a plan view and (B) is a cross-sectional view taken along the line BB.

FIG. 16 is a step following FIG. 15, in which (A) is a plan view and (B) is a cross-sectional view taken along the line BB.

FIG. 17 is a step following FIG. 16, in which (A) is a plan view and (B) is a cross-sectional view taken along the line BB.

18A is a plan view showing a state in which a semiconductor thin film, a channel protective film, and the like are formed on a transparent substrate in manufacturing a conventional thin film transistor, and FIG. 18B is a sectional view taken along the line BB.

FIG. 19 is a step following FIG. 18, in which (A) is a plan view and (B) is a cross-sectional view taken along the line BB.

FIG. 20 is a step following FIG. 19, in which (A) is a plan view and (B) is a cross-sectional view taken along the line BB.

FIG. 21 is a step subsequent to FIG. 20, in which (A) is a plan view and (B) is a cross-sectional view taken along the line BB.

[Explanation of symbols]

 21 transparent substrate 25 semiconductor thin film 26a channel protective film 28 metal film 29 silicide layer

Claims (6)

[Claims] 1. A metal film capable of silicidation is formed on a semiconductor thin film, and ions containing a donor or acceptor impurity are implanted into the semiconductor thin film from above the metal film to form the donor or acceptor in the semiconductor thin film. A method for manufacturing a semiconductor device, comprising implanting impurities and forming a silicide layer uniformly at an interface between the metal film and the semiconductor thin film. 2. A metal film capable of silicidation is formed on a predetermined region of a semiconductor thin film, ions containing donor or acceptor impurities are implanted into the semiconductor thin film from above the metal film, and the metal thin film is formed into the semiconductor thin film. A method for manufacturing a semiconductor device, which comprises implanting a donor or acceptor impurity and uniformly forming a silicide layer at an interface between the metal film and a predetermined region of the semiconductor thin film. 3. A semiconductor thin film is formed on a substrate to remove an oxide film on a surface of the semiconductor thin film, a silicidable metal film is formed on the semiconductor thin film, and the metal film is formed from above the metal film. Implanting ions containing a donor or acceptor impurity into the semiconductor thin film, implanting the donor or acceptor impurity into the semiconductor thin film, and forming a silicide layer uniformly at the interface between the metal film and the semiconductor thin film. A method for manufacturing a characteristic semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film is formed to have a thickness of about 50 to 200 Å. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film is removed after the ion implantation. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor thin film is made of amorphous silicon.