JPH0921846A - Inspection device - Google Patents

Abstract

(57) [Abstract] [Purpose] To reliably and reliably inspect semiconductor integrated circuit devices at low cost. [Structure] The pin electronics PE provided in the inspection device 2 is composed of a general AC channel for performing a DC characteristic test, an AC characteristic test, and a function test, and a DC channel for performing only a DC characteristic test. The DC channel is composed of a driver for applying a signal to the device under test 1 and a DC measuring machine for measuring a current value or a voltage value in the device under test 1. Then, a test item such as voltage measurement in the input / output latch of the device under test 1 that does not require an AC channel is performed by the DC channel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection device, and more particularly to a technique effective when applied to the reduction of the device cost in an inspection device for inspecting a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art According to a study made by the present inventor, an inspection device for inspecting internal logic in a semiconductor integrated circuit device includes all necessary units such as a timing generator, a waveform formatter, a driver, a fail memory and a comparator. A channel is provided which is the provided pin electronics.

Then, a channel is connected to each pin of the semiconductor integrated circuit device, and tests such as a DC test and an AC test for confirming whether or not the semiconductor integrated circuit device operates according to its function are performed.

[0004] As an example in which this type of inspection device is described in detail, "Journal of Semiconductor," published by Press Journal Co., Ltd., September 9, 1994.
World special edition The Equipment "1
1994 Special Issue, Volume 13, No. 10, Shinji Matsushita (ed.),
P115 to P120, and this document describes the outline and development trend of the LSI test apparatus.

[0005]

However, the present inventor has found that the above LSI tester has the following problems.

That is, all the configured channels are DC.
Since this is an expensive channel for conducting tests and AC tests, there is a problem that the manufacturing cost per channel and the test cost increase.

With the recent increase in the number of pins of semiconductor integrated circuit devices, the number of channels tends to increase, and the increase in manufacturing cost and test cost has become remarkable.

An object of the present invention is to provide an inspection apparatus which can reliably inspect a semiconductor integrated circuit device at low cost.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the inspecting apparatus of the present invention is used as an interface for the input / output pins of the device under test, and only the first inspection means for performing the AC test and the DC test of the device under test and the DC test in the device under test. The second inspection means for performing is mixedly provided.

Further, in the inspection apparatus of the present invention, the second inspection means is used as an interface for the input / output pins of the device under test, and is composed of pin electronics which can be arbitrarily mounted.

Further, in the inspection apparatus of the present invention, the second inspection means is a level driver for generating a predetermined DC voltage applied to the device under test, and a DC measurement unit for measuring DC parameters in the device under test. It consists of

[0014]

According to the above-described inspection apparatus of the present invention, the first inspection means is the pin electronics for performing the AC test and the DC test on the device under test, and the pin electronics for performing only the DC test on the device under test. Two inspection means are provided in a mixed manner, and the first inspection means and the second inspection means are selectively used depending on the inspection item.
Significant cost reductions can be achieved by arbitrarily changing the number of these components mounted.

Further, according to the above-described inspection apparatus of the present invention, the level driver for generating the predetermined DC voltage for applying the second inspection means to the device under test and the DC parameter in the device under test are measured. By configuring with the DC measuring unit, the circuit configuration is simplified and the cost can be further reduced.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an inspection apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram of an AC channel in the inspection apparatus according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a block diagram of a DC channel in the inspection apparatus according to the present invention.
Explanatory drawing in which C channel and DC channel are mounted, FIG.
6 is an explanatory diagram showing a test procedure of an internal logic in a device under test by an inspection apparatus according to an embodiment of the present invention, FIG.
7 is an explanatory diagram showing a test procedure of an input latch in a device under test by an inspection apparatus according to an embodiment of the present invention, and FIG. 7 shows a test procedure of an output latch in a device under measurement by an inspection apparatus according to an embodiment of the present invention. It is an explanatory view shown.

In this embodiment, for example, the inspection apparatus 2 for performing various tests such as AC test and DC test of the device under test 1 such as a semiconductor integrated circuit device is a host computer 3 such as a workstation and the device under test 1. It is configured by an LSI inspection device 4 which serves as a tester.

Further, the host computer 3 has a control terminal 3a composed of a keyboard for inputting predetermined data and a monitor for displaying the input data.
Is connected.

Further, the host computer 3 is an LSI
The device under test 1 connected to the inspection device 4 is L
It is connected via a performance board 5 provided in the SI inspection device 4.

The performance board 5 functions as an interface between the LSI inspection device 4 and the device under test 1, and includes a socket for coupling with an external terminal of the device under test 1, and the socket under test. The device 1 is adapted to be connected.

Further, the LSI inspection apparatus 4 performs a tester unit 4a, which is a tester main body, and a DC characteristic test, an AC characteristic test, and a functional test or a DC characteristic test only. It is configured to be installed.

The tester section 4a is the tester section 4a.
There is provided a processor 6 that controls all the control of a, and a host interface 7 that exchanges data between the host computer 3 and the tester 4a.

Further, the tester unit 4a has a buffer memory 8 for temporarily storing data transferred to the host computer 3 and data transferred from the host computer 3.
Is provided.

The data stored in the buffer memory 8 is the object data JD, the test result TE and the test pattern TP.

Further, the test section 4a includes a timing generator 9 for determining the timing of the input waveform in the repeating cycle for testing the device under test 1 and the timing for comparing the output signals, and a reference power supply 10 for regulating the voltage level. It is provided.

Further, the tester section 4a is provided with a device power supply 11 for supplying power required to operate the device under test 1 and a device power supply controller 12 for controlling the voltage value of the device power supply 11.
1 and the device power supply controller 12 are connected.

Further, the tester section 4a is provided with a test pattern memory 13 for storing the test pattern TP and a fail memory 14 for storing fail data and fail address.

Further, the tester section 4a includes a test controller 1 for controlling the pin controller 15 for controlling the pin electronics PE, the timing generator 9, the reference power source 10, the pin controller 15 and the like.
6 are provided.

The processor 6, the host interface 7, the buffer memory 8, the timing generator 9, the reference power supply 10, the device power supply controller 12 and the test controller 16 are connected by a system bus 17 to exchange various data and signals. Is being done.

Further, the voltage output from the reference power supply 10 is connected so as to be output to the timing generator 9, and the output signal from the timing generator 9 is connected to be output to the test controller 16.

Furthermore, the pin controller 15 is connected to the test controller 16, the test pattern memory 13 and the fail memory 14 so that data can be input and output.

The voltage output from the device power supply 11 is connected to the device under test 1 via the performance board 5.

Next, as many pin electronics PE as the number of pins of the device under test 1 are provided, and as described above, the pin electronics PE are provided in FIG.
As shown in FIG. 3, an AC channel (first inspection means) 4b for performing a DC characteristic test, an AC characteristic test, and a function test.
And a DC channel (second inspection means) 4c for performing only the DC characteristic test.

First, the AC channel 4b shown in FIG. 2 generates a driver 18 that applies a signal to the device under test 1, a comparator 19 that detects the output of the device under test 1, and a test waveform that is applied to the device under test 1. The waveform formatter 20 and the DC measuring machine 21 for measuring the current value and voltage value in the device under test 1 are configured.

Then, the comparator 19, the waveform formatter 20 and the DC measuring device 2 in the AC channel 4b are used.
1 is connected to the pin controller 15 and the driver 18
Is connected to the reference power supply 10 and is supplied with an arbitrary voltage.

The waveform formatter 20 is connected to the driver 18, the signal output from the waveform formatter 20 is input to the driver 18, and the performance board 5 for connecting to the pin of the device under test 1 is connected to the driver 18, respectively. Comparator 19 and DC measuring device 21
The input / output of a predetermined signal is performed.

Further, in the DC channel 4c, the driver (level driver) 22 for applying a signal to the device under test 1 and the device under test 1 as shown in FIG.
DC measuring machine 23 for measuring current value and voltage value in
It consists of.

The driver 22 and the DC measuring device 23 provided in the DC channel 4c are similarly connected to the pin controller 15, and the driver 18 is also connected to the reference power source 10 and is supplied with an arbitrary voltage. .

The performance boards 5 that are connected to the pins of the device under test 1 have drivers 18 respectively.
And a DC measuring device 21 for inputting and outputting a predetermined signal.

As shown in FIG. 4, the AC channels 4b and the DC channels 4c are provided in a predetermined number, and the signals of the AC channels 4b and the DC channels 4c are transmitted from the performance board 5 (FIG. 1). It is input to and output from the device under test 1 (FIG. 1) via the device.

Next, the operation of this embodiment will be described.

First, the user generates a test control program by the host computer 3, compiles the control program to generate the object data JD, and then stores it in a storage device (not shown) such as a magnetic disk device.

Next, when inspecting the device under test 1, predetermined data is input from the control terminal 3a of the host computer 3 to activate the test program.

As a result, the object data JD stored in the above-mentioned storage device is output to the buffer memory 8 via the host interface 7.

Thereafter, the object data JD stored in the buffer memory 8 is read out and executed by the processor 6 to form the environment described in the test program.

When the test program is activated, the test pattern TP is transferred to the test pattern memory 13 via the pin controller 15.

In the case of a test using the AC channel 4b in the pin electronics PE, this test pattern TP is input to the waveform formatter 20 together with the level signal generated by the timing generator 9 and the reference power supply 10 to form an input waveform. The driver 18 outputs a signal to be applied to the device under test 1, and the signal is applied to a predetermined pin of the device under test 1 via the performance board 5.

The signal output from the internal logic of the device under test 1 is taken into the AC channel 4b via the performance board 5 and the comparator 19
Is compared with a predetermined expected value.

As a result of the comparison of the comparator 19, it is determined that the data matches the expected value (pass) (normal), and if they do not match, the fail (abnormal), and these data are stored in the fail memory 14.

In this embodiment, it is necessary to separately carry out the internal logic test, the input latch test and the output latch test.

For example, in FIG. 5 to FIG. 7, the device under test 1 to be tested is the internal logic 1a, the internal logic 1
An input latch 1b and an output latch 1c connected to a are provided for each pin 1d which is an external connection line, and an input side scan circuit 1e and an output side scan circuit 1f are provided in the common area.

First, as shown in FIG. 5, application of the test pattern for testing the internal logic 1a in the device under test 1 is performed by scanning the scan-in data SID and the scan-in clock S stored in the test pattern memory.
The ICK, the scan-out clock SOCK, and the scan address SADR are not applied to the input pad (not shown) but to the input latch 1b via the input side scan circuit 1e.

Similarly, the output data is not fetched from the output pad (not shown) but is fetched from the output latch 1c to the comparator 19 provided in the AC channel 4b via the output side scan circuit 1f.

Next, the comparator 19 compares the scan-out data SOD which is the expected output value stored in the test pattern memory 13 with the fetched output data, and the result is written in the fail memory 14. Be seen.

Then, these operations are repeated for all patterns.

Therefore, in the test in the internal logic 1a, the required channel is the scan-in data SID,
Only the pin 1d to which the scan-in clock SICK, the scan-out clock SOCK, and the scan address SADR are input is required, and all of them need to be the AC channel 4b.

Next, as shown in FIG. 6, the input latch 1b
I will explain the test in.

The purpose of this test is to determine whether the Hi signal or the Lo signal set in the input pad (not shown) of the device under test 1 has been correctly taken into the input latch 1b. 1b cannot be directly read back because it is connected to the internal logic 1a.

To this end, the latch data is scanned out to the output side scan circuit 1f, and the comparator 19 judges this.

Therefore, the data output from the test pattern memory 13 does not need to be scanned in, and only the data output from the input latch 1b is scanned out to the output side scan circuit 1f.

In this test, scan-in data SI
The channel used for the pin 1d to which D, the scan-in clock SICK, and the scan address SADR are input needs to be the AC channel 4b, but since the signal application to the input pad may be level data, it need not be the AC channel 4b. Since it does not exist, the DC channel 4c should be used.

Next, as shown in FIG. 7, the output latch 1c
The purpose of the test is to determine whether the Hi signal or the Lo signal set in the output latch 1c is correctly output to the output pad (not shown). Since it is connected to 1a, direct setting cannot be performed.

Therefore, the Hi signal / Lo signal is scanned into the output latch 1c by using the input side scan circuit 1e, and the DC measuring instrument 23 determines this data.

Therefore, in the data output from the test pattern memory 13, scan-out data is unnecessary, and the scan-in data SID of the test pattern memory 13 is set in the output latch 1c via the input side scan circuit 1e. All you have to do is

Also in this test, the channel used for the pin 1d to which the scan-in data SID, the scan-in clock SICK and the scan address SADR are input needs to be the AC channel 4b, but the signal level to the output pad is not measured. Since it can be performed by the DC measuring machine 23, it is not necessary to use the AC channel 4b, and the DC channel 4c may be used.

As a result, in this embodiment, the LSI
By providing not only the AC channel 4b but also the DC channel 4c having a simple circuit configuration in the inspection apparatus 4, the LSI inspection apparatus 4 can be significantly reduced in cost.

Further, the number of mounted AC channels 4b and DC channels 4c can be arbitrarily changed according to the input / output method of the device under test 1, so that the test cost can be greatly reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

[0070]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, not only the first inspecting means for performing the AC test and the DC test in the device under test but also the inexpensive second inspecting means for performing only the DC test are mixedly provided. As a result, the cost of the inspection device can be significantly reduced.

(2) Further, in the present invention, the cost of the entire inspection process can be greatly reduced by the above (1).

[Brief description of drawings]

FIG. 1 is a block diagram of an inspection apparatus according to an embodiment of the present invention.

FIG. 2 is an AC in an inspection apparatus according to an embodiment of the present invention
It is a block diagram of a channel.

FIG. 3 is a DC in an inspection apparatus according to an embodiment of the present invention
It is a block diagram of a channel.

FIG. 4 is an explanatory diagram in which an AC channel and a DC channel are mounted on the inspection device according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an internal logic test procedure in the device under test performed by the inspection apparatus according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram showing a test procedure of the input latch in the device under test by the inspection apparatus according to the embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a test procedure of the output latch in the device under test by the inspection apparatus according to the embodiment of the present invention.

[Explanation of symbols]

 1 device under test 1a internal logic 1b input latch 1c output latch 1d pin 1e input side scan circuit 1f output side scan circuit 2 inspection device 3 host computer 3a control terminal 4 LSI inspection device 4a tester unit 4b AC channel 4c DC channel (first 1 inspection means) 5 performance board 6 processor 7 host interface 8 buffer memory 9 timing generator 10 reference power supply 11 device power supply 12 device power supply controller 13 test pattern memory 14 fail memory 15 pin controller 16 test controller 17 system bus 18 driver 19 comparator 20 Waveform Formatter 21 DC Measuring Machine 22 Driver (Level Driver) 23 DC Measuring Machine PE Pin Electronics D object data TE test result TP test pattern SID scan-in data SICK scan ink lock SOCK scan-out clock SADR scan address SOD scan-out data

Claims (3)

[Claims] 1. An inspection apparatus which is used as an interface for an input / output pin of a device under test and is provided with a first inspection means for performing an AC test and a DC test on the device under test, the device under test. 2. An inspection apparatus characterized in that it is provided with a second inspection means for performing only the DC test in. 2. The inspection apparatus according to claim 1, wherein the second inspection means is used as an interface for an input / output pin of the device under test, and is composed of pin electronics capable of arbitrarily changing the number of mounted devices. Characteristic inspection device. 3. The inspection apparatus according to claim 1, wherein the second inspection means sets a level driver for generating a predetermined DC voltage applied to the device under test and a DC parameter in the device under test. DC to measure
An inspection device comprising a measuring unit.