JPH09219636A - Drive circuit - Google Patents

Abstract

(57) Abstract: A drive circuit capable of controlling an output current based on an input voltage is provided. An output buffer 54 in a drive circuit 51
The N-channel transistor N5 inserted between the output terminal 59 and the ground voltage GND is supplied to the N-channel transistor N2 by the P-channel transistors P2 and P3 and the N-channel transistors N4 and N5 configured as a current mirror circuit. Controlled by the applied current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit composed of CMOS (complementary metal oxide semiconductor), and more particularly to a drive circuit suitably used for a driver for driving an active matrix type liquid crystal display panel.

[0002]

2. Description of the Related Art FIG. 17 is a circuit diagram of a drive circuit 1 as a first prior art used as an operational amplifier circuit formed on a MOS integrated circuit. The drive circuit 1 includes a differential amplifier circuit 2 and an output buffer 3. The drive circuit 1 includes an inverting input terminal 4, a non-inverting input terminal 5, and a first
A bias input terminal 6, a second bias input terminal 7, and an output terminal 8 are provided.

The differential amplifier circuit 2 is a differential amplifier circuit having N-channel MOS transistors as a differential pair, and includes N-channel MOS transistors Tn1, Tn2, Tn3 and P-channel MOS transistors Tp1, Tp2. To be done. In this specification, the N-channel MOS transistor and the P-channel MOS transistor may be simply referred to as “transistor”.

The gate of the transistor Tn1 is connected to the non-inverting input terminal 5 and supplied with the non-inverting input voltage VINb. The gate of the transistor Tn2 is connected to the inverting input terminal 4 and supplied with the inverting input voltage VINa. The transistors Tp1 and Tp2 are active loads of the transistors Tn1 and Tn2, and their sources have a voltage VDD as a power supply voltage.
Is given.

The gate of the transistor Tn3 is connected to the first bias input terminal 6 and supplied with the bias voltage VB1 having a predetermined voltage level. The source of the transistor Tn3 is grounded, and the drain thereof is the transistors Tn1 and Tn.
Commonly connected to each drain of n2. Transistor T
n3 is a constant current source for applying an appropriate bias current to the transistors Tn1 and Tn2.

In the output buffer 3, the P channel M
The gate of the OS transistor Tp3 is supplied with the potential of the drain of the transistor Tn1 in the differential amplifier circuit 2. The voltage VDD is applied to the source of the transistor Tp3, and a current flows based on the drain voltage. This current is given to the external load via the output terminal 8. A bias voltage VB2 of a predetermined voltage level is applied from the second bias input terminal 7 to the gate of the N-channel MOS transistor Tn4. The source of the transistor Tn4 is grounded, and the drain is the transistor Tn4.
It is connected to the output terminal 8 similarly to the drain of p3. The transistor Tn4 acts as a constant current load. The drive circuit 1 includes a liquid crystal display panel 63 as shown in FIG.
When driving, the inverting input terminal 4 and the output terminal 8 are connected to operate as a voltage follower.

The operation of the drive circuit 1 will be described. The amount of current flowing through the transistor Tn1 is controlled according to the voltage level of the non-inverting input voltage VINb. Further, depending on the voltage level of the inverting input voltage VINa, the transistor Tn2
To control the amount of current flowing through the current mirror circuit composed of the transistors Tp1 and Tp2, the amount of current flowing to the output transistor Tp3 changes. For example, when the voltage level of the non-inverting input voltage VINb is higher than the voltage level of the inverting input voltage VINa, the current flowing through the transistor Tp3 increases. In addition, the non-inverted input voltage VI with respect to the voltage level of the inverted input voltage VINa
When the voltage level of Nb is low, the current flowing through the transistor Tp3 decreases.

The current flowing through the transistor Tp3 is the second
The bias voltage VB2 from the bias input terminal 7 is compared with the load current flowing through the transistor Tn4. Based on the result of this comparison, the voltage output from the output terminal 8 changes. In the voltage follower described above, by connecting the output terminal 8 to the inverting input terminal 4, the inverting input voltage VINa follows the non-inverting input voltage VINb of the non-inverting input terminal 5 and becomes the same voltage as the non-inverting input voltage VINb. The negative feedback operation is performed so that

A drive circuit capable of always performing optimum bidirectional output current control regardless of the state of the load is disclosed in JP-A-6-214527 as the second and third prior arts.

FIG. 18 shows a second prior art drive circuit 1
1 is a circuit diagram of FIG. 1, and FIG. 19 is a circuit diagram of a drive circuit 16 which is a third prior art. In the drive circuits 11 and 16, the same components as those of the above-described drive circuit 1 and components that perform the same functions are designated by the same reference numerals and description thereof will be omitted.

The drive circuit 11 shown in FIG. 18 includes a differential amplifier circuit 12, a level conversion circuit 13, and an output buffer 1.
4 is included. The differential amplifier circuit 12 includes input transistors Tn11 and Tn12, a constant current transistor Tn13, and current mirror transistors Tp11 and Tn.
p12 and are included. The level conversion circuit 13
It is configured to include P-channel transistors Tp13 and Tp14 and loads respectively connected to the drains of the transistors Tp13 and Tp14. Transistor Tp1
The drain of the transistor Tp12 is supplied to the gate of the transistor 3 as the output of the differential amplifier circuit 12, and the drain of the transistor Tp13 is supplied to the gate of the transistor Tp14.

In the drive circuit 11, the transistor Tp13
A constant DC voltage V as a load connected to the drain of the
N-channel transistor Tn whose gate is B2
14 is used, and an N-channel transistor Tn15 whose gate is connected to its drain is used as the load of the transistor Tp14.

The output buffer 14 comprises a P-channel transistor Tp15 and an N-channel transistor Tn16, the output of the differential amplifier circuit 12 is given to the gate of the transistor Tp15, and the transistor Tn1.
The gate of 6 receives the output of the level conversion circuit 13. Transistor Tp15 and transistor Tn16
Are connected to each other.

The operation of the drive circuit 11 will be described. The differential amplifier circuit 12 obtains an output obtained by amplifying the voltage difference between the non-inverting input voltage VINb and the inverting input voltage VINa, and outputs the non-inverting input voltage VINa with respect to the inverting input voltage VINa.
When the voltage of b increases, the drain voltage of the transistor Tn12 which is the output of the differential amplifier circuit 12 decreases, and conversely, when the voltage of the non-inverting input voltage VINb decreases, the drain voltage of the transistor Tn12 increases. Therefore, the transistor Tp15 of the output buffer 14 having the gate to which the output of the differential amplifier circuit 12 is applied is connected to the non-inverting input voltage VI.
When the voltage of Nb increases, the resistance value between the source and the drain decreases, and conversely, when the voltage of the non-inverting input voltage VINb decreases, the resistance value between the source and the drain increases. When the inverting input voltage VINa and the non-inverting input voltage VINb are equal, the differential amplifier circuit 12 is set so that the output voltage of the differential amplifier circuit 12 becomes the threshold voltage of the transistor Tp15.

On the other hand, the output of the differential amplifier circuit 12 is inverted by the transistor Tp13 of the level conversion circuit 13, further inverted by the transistor Tp14, and output from the output buffer 14.
Applied to the gate of the transistor Tn16. Therefore, when the voltage of the non-inverting input voltage VINb increases, the resistance value between the source and the drain of the transistor Tn16 increases, and conversely, when the voltage of the non-inverting input voltage VINb decreases, the resistance value between the source and the drain decreases. When the inverting input voltage VINa and the non-inverting input voltage VINb are equal to each other, the transistor Tp13 has a drain voltage equal to the threshold voltage of the transistor Tp14, and the transistor Tp14 has a drain voltage equal to the threshold voltage of the transistor Tn16. Tp13, Tp14
The load value of is set. Therefore, the inverting input voltage
The output voltage corresponding to the voltage difference of the non-inverting input voltage is obtained,
Achieved bidirectional output current control.

The drive circuit 16 shown in FIG. 19 includes a differential amplifier circuit 12, a level conversion circuit 17, and an output buffer 18. The differential amplifier circuit 12 is the same circuit as the differential amplifier circuit 12 in the drive circuit 11 described above. The level conversion circuit 17 includes P-channel transistors Tp21 and Tp22 and transistors Tp21 and Tp.
A load connected to each drain of p22 is included, and the output of the differential amplifier circuit 12 is applied to each gate of the transistors Tp21 and Tp22.

In the drive circuit 16, the transistor Tp21
A constant DC voltage V as a load connected to the drain of the
N-channel transistor Tn whose gate is B2
21 is used as the load of the transistor Tp22, and an N-channel transistor Tn22 having a drain connected to the drain of the transistor Tp22 and a gate connected to the drain is used.

The output buffer 18 includes a P channel transistor Tp23 and an N channel transistor Tn23. The gate of the transistor Tp23 is connected to the drain of the transistor Tp21, the gate of the transistor Tn23 is connected to the drain of the transistor Tp22, and the drains of the transistors Tp23 and Tn23 are connected to each other.

In the drive circuit 16 as well as the drive circuit 11, the inverted input voltage VINa and the non-inverted input voltage VI.
An output voltage corresponding to the voltage difference of Nb is obtained, and bidirectional output current control is realized.

FIG. 20 shows a fourth prior art of Japanese Unexamined Patent Publication No. Hei.
FIG. 9 is a circuit diagram of a drive circuit 21 which is a CMOS operational amplifier circuit disclosed in Japanese Patent Publication No. 92008. Drive circuit 21
Is provided with an inverting input terminal 25, a non-inverting input terminal 26, a first bias input terminal 27, a second bias input terminal 28, and an output terminal 29, and the first differential amplifier circuit 2
2, a second differential amplifier circuit 23, and an output amplifier circuit 24.

The first differential amplifier circuit 22 comprises N channel transistors Mn1, Mn2, Mn3 and P channel transistors Mp1, Mp2. Also, the second
The differential amplifier circuit 23 includes N-channel transistors Mn4 and Mn4.
Mn5 and P-channel transistors Mp4, Mp5, Mp
6 is included. The output amplifier circuit 24 is configured to include a transistor Mp3 whose gate is supplied with the output a of the first differential amplifier circuit 22 and a transistor Mn6 whose gate is supplied with the output b of the second differential amplifier circuit 23.

In the first differential amplifier circuit 22, the sources of the transistors Mn2 and Mn3 forming a differential pair are commonly connected. The gate of the transistor Mn2 is connected to the inverting input terminal 25 and supplied with the voltage V1. The gate of the transistor Mn3 has a non-inverting input terminal 2
6 and is supplied with voltage V2.

The transistors Mp1 and Mp2 are active loads of the transistors Mn2 and Mn3, and the voltage VDD is applied to their sources. Also, the transistor Mp
The drain potential of the transistor Mn2 is applied to the gates of 1 and Mp2, and conduction / cutoff is controlled. The potential of the drain of the transistor Mp2 serves as a signal for controlling the output a to the output amplifier circuit 24.

The transistor Mn1 is a transistor Mn.
2, Mn3 is a constant current source for applying an appropriate bias current, the voltage VSS is applied to the source, and the drain is connected to the sources of the transistors Mn2 and Mn3. Further, the bias voltage VB1 from the first bias input terminal 27 applied to the gate determines the bias current supplied to the transistors Mn2 and Mn3.
The output a of the first differential amplifier circuit 22 drives the output transistor Mp3.

Since the second differential amplifier circuit 23 has a structure in which the conductivity types of the transistors included in the first differential amplifier circuit 22 are exchanged, the points different from the first differential amplifier circuit 22 will be described. Transistors Mn1, Mn2, Mn3, M
p1 and Mp2 in this order are transistors Mp4 and Mp.
5, Mp6, Mn4, and Mn5, respectively.

The gate of the transistor Mp5 is connected to the inverting input terminal 25 in common with the transistor Mn2,
The gate of the transistor Mp6 is connected to the non-inverting input terminal 26 in common with the transistor Mn3. The voltage VSS is supplied to the sources of the transistors Mn4 and Mn5. The potential of the drain of the transistor Mp5 is given to the gate of the transistor Mn6 as the output b. The gate of the transistor Mp4 is connected to the second bias input terminal 28 and is supplied with the bias voltage VB2. The voltage VDD is supplied to the source of the transistor Mp4, and the drain is connected to the sources of the transistors Mp5 and Mp6.

In the output amplifier circuit 24, the transistor Mp
The voltage VDD is applied to the source of the transistor 3 and the transistor M
The voltage VSS is applied to the source of n6. The drains of the transistors Mp3 and Mn6 are commonly connected to the output terminal 29.

The operation of the drive circuit 21 configured as described above will be described. FIG. 21 is a diagram for explaining the operation of the drive circuit 21. The horizontal axis represents the voltage V2 which is the non-inverting input voltage input to the non-inverting input terminal 26, and the vertical axis represents the voltage V1 which is the inverting input voltage input to the inverting input terminal 25.

When the voltage input to the non-inverting input terminal 26 becomes higher than the voltage input to the inverting input terminal 25, the first
Since the current flowing through the transistor Mn3 of the differential amplifier circuit 22 increases and the drain potential of the transistor Mp2 is lowered, the transistor Mp3 is rendered conductive and the potential of the output terminal 29 is raised. In addition, the current flowing through the transistor Mp6 of the second differential amplifier circuit 23 decreases, and the transistor Mn5
Since the drain potential of the transistor Mn6 is lowered, the transistor Mn6 is cut off. Therefore, the potential of the output terminal 29 is the voltage VD.
Rise to the D side.

When the voltage input to the non-inverting input terminal 26 becomes lower than the voltage input to the inverting input terminal 25, the second
The current flowing through the transistor Mp6 of the differential amplifier circuit 23 increases, the drain potential of the transistor Mn5 rises, and the transistor Mn6 becomes conductive. Further, the current flowing through the transistor Mn3 decreases, the drain potential of the transistor Mp2 rises, and the transistor Mp3 is cut off. Therefore, the potential of the output terminal 29 drops to the voltage VSS side.

As described above, the output terminal 2 of the drive circuit 21
The output from 9 is output in a push-pull format by the transistors Mp3 and Mn6. Transistor Mp3
The sources of Mn6 are all grounded, and the gate signal has a sufficient amplitude, so that a wide output dynamic range and driving of a large load can be expected.

An enhancement type transistor is generally used as each of the transistors forming the drive circuit 21. Since the enhancement-type transistor does not form a channel region at the time of manufacture, in the case of an N-channel transistor, for example, a drain current flows only when a positive voltage is applied to the gate. In addition, in the duplication type transistor, which is different from the enhancement type transistor, a channel region is formed between the source and the drain at the time of manufacturing, so that a drain current flows regardless of whether a positive or negative voltage is applied to the gate.

The transistors Mn2 and Mn3 are enhancement type transistors and have a positive threshold voltage Vt.
Assuming that n is provided, each input terminal 25, 2
The voltages V1 and V2 supplied from 6 are the voltage VSS + Vtn
In the following case, the transistors Mn2 and Mn3 are cut off and no current flows through the first differential amplifier circuit 22, so that the gate potential of the transistor Mp3 rises to the voltage VDD. At this time, the transistor Mp3 is an enhancement type transistor and has a negative threshold voltage Vtp.
, The transistor Mp3 is cut off, and the output voltage V0 is changed to the voltage VDD− | Vtp |
The voltage cannot exceed. Similarly, assuming that the transistors Mp5 and Mp6 are enhancement type transistors and have a negative threshold voltage Vtp, when the input voltage is higher than the voltage VDD− | Vtp |, the second differential amplifier circuit. No current flows through 23,
The gate potential of the transistor Mn6 drops to the voltage VSS. If the transistor Mn6 is an enhancement type transistor and has a positive threshold voltage Vtn, it is cut off, and the output voltage V0 output from the output terminal 29 cannot be set to a voltage lower than the voltage VDD + Vtn.

The drive circuit 21 configured as described above operates normally only when the inverting and non-inverting input terminals 25 and 2 are operated.
The voltage input to 6 is from the voltage VSS + Vtn to the voltage VD
The range is up to D- | Vtp |, and the range of voltage at which the drive circuit 21 can operate is limited.

By forming each transistor of the drive circuit 21 by the above-described duple region type transistor, the operable voltage range is from the voltage VSS to the voltage VSS.
Although it can be a DD, the duple region type transistor requires a special manufacturing process for the enhancement type transistor, which causes a rise in manufacturing cost.

As a fifth prior art, a drive circuit 31 is disclosed in Japanese Patent Application Laid-Open No. 4-295699. FIG.
23 is a block diagram showing a schematic configuration of the drive circuit 31, and FIG. 23 is a differential amplifier circuit 32 included in the drive circuit 31.
FIG. The drive circuit 31 is used, for example, as a circuit for driving a liquid crystal display panel 63 shown in FIG. 2 described later.

The drive circuit 31 includes a differential amplifier circuit 32 and an output circuit 33. The output terminal 32d of the differential amplifier circuit 32 is connected to the input terminal 33a of the output circuit 33. The output from the output terminal 33b of the output circuit 33 is connected to the inverting input terminal 32c of the differential amplifier circuit 32. Therefore, the drive circuit 31 is a voltage follower.

In FIG. 22, an analog signal Y, such as a video signal, to be sampled and held is input from the input signal line 39. The capacitors 34 and 35 are for holding the voltage of the analog signal Y, and one terminal of each of the capacitors 34 and 35 is connected to the input signal line 39 via the analog switches 37 and 38, and the other terminal. Both terminals are grounded.

The differential amplifier circuit 32 in the drive circuit 31
Has two non-inverting input terminals 32a and 32b, the non-inverting input terminal 32a is connected to one terminal of the capacitor 35, and the non-inverting input terminal 32b is connected to one terminal of the capacitor 34. Control terminal 3 of the differential amplifier circuit 32
Control signals S3 and S4 are input to 2e and 32f, respectively. The N-channel MOS transistor 36 connected between the output of the output circuit 33 and the ground functions as an analog switch, and the control signal R is input to its gate via the signal line 40.

Referring to FIG. 23, the differential amplifier circuit 32
Is configured to include N-channel transistors N51 to N57 and P-channel transistors P51 and P52. The source of the transistor N57 is connected to the ground, and a predetermined voltage Vb is applied to the gate. The transistor N57 is the transistors N53, N54, N5.
6 is a constant current source for giving an appropriate bias current to the transistor 6.

P-channel MOS transistors P51, P
Each source of 52 is connected to the power supply VDD, and each gate is connected to the drain of the transistor P51. N-channel MOS transistors N56, N5
Each source of 3 is connected to the drain of the transistor N57, and each drain of the transistors N56 and N53 is connected to the drain of the transistor P51 via the transistors N55 and N51.

The gates of the transistors N56 and N53 are connected to the non-inverting input terminals 32a and 32b, respectively, and the gates of the transistors N55 and N51 are connected to the control terminals 32e and 32f, respectively, and the control signals S3 and S4 are input. There is.

The drain of the transistor N54 is connected to the drain of the transistor P52 via the transistor N52, and the source of the transistor N54 is connected to the drain of the transistor N57. The gate of the transistor N54 is connected to the inverting input terminal 32c. The connection point of the transistors N52 and P52 is connected to the output terminal 32d of the differential amplifier circuit 32. The gate of the transistor N52 is connected to the power supply VDD and is always in a conductive state.

FIG. 24 is a timing chart of the operation of the differential amplifier circuit 32. At time t1, when the control signal S1 becomes high level, the analog switch 37 is turned on, the signal Y is applied to the capacitor 35, and the capacitor 35
Is charged. After that, when the signal S1 goes low and the analog switch 37 is turned off, the capacitor 35
Holds the voltage D1 of the signal Y at that time.

After that, when the control signal R becomes high level, the transistor 36 becomes conductive and the output of the output circuit 33 becomes ground level. When the control signal S3 becomes high level, the voltage D1 held in the capacitor 35 is output as the output voltage D1a via the differential amplifier circuit 32 and the output circuit 33.

When the control signal S2 becomes high level at time t2, the analog switch 38 is turned on, the signal Y is applied to the capacitor 34, and the capacitor 34 is charged. After that, when the signal S2 becomes low level and the analog switch 38 is turned off, the capacitor 34 holds the voltage D2 of the signal Y at that time.

After that, when the control signal R becomes high level, the transistor 36 becomes conductive and the output of the output circuit 33 becomes ground level. When the control signal S4 becomes high level, the voltage D2 held in the capacitor 34 is output as the output voltage D2a via the differential amplifier circuit 32 and the output circuit 33.

Thereafter, the analog switches 37 and 38 are alternately turned on, and the voltages D3, D4, ... Of the signal Y are sampled and output.

[0049]

In the drive circuit 1 as shown in FIG. 17, since the output current for driving the load is controlled by the transistor Tp3 of the output buffer 3, the controlled output current flows out (or flows in). ) In one direction, and the other direction is determined by the current flowing through the constant current transistor Tn4 which is a load forming the output buffer 3. If this current capacity is increased, the through current of the output buffer 3 increases, so that the current consumption of the output circuit increases,
On the other hand, if the current consumption is to be suppressed, the current capacity becomes small and the load driving capability of the output circuit decreases.

Further, in the drive circuits which can be driven only in one direction, such as the drive circuits 1, 21, 31 described above,
If the non-inverting input voltage drops, the drain voltage of the transistor whose gate is supplied with the non-inverting input voltage drops, so that the transistor does not operate as a constant current source and the current supplied to the differential pair decreases. Therefore, the drive circuits do not operate normally. Further, when the non-inverting input voltage drops, the transistors of the differential pair are cut off, and the operation of the drive circuit stops. Therefore, these circuits cannot operate unless the input voltage is higher than or lower than the threshold voltage of the transistors forming the differential pair. That is, for example, when the transistors forming the differential pair have a positive threshold voltage Vtn, they do not operate in the region where the input voltage is voltage GND to voltage Vtn. Since the voltage range is about 1 V or more, it becomes a particularly important problem in the recent trend of lowering driving voltage.
Therefore, there is a demand for an enhancement type push-pull differential amplifier circuit which can be driven over the entire power supply voltage region with a small number of elements.

Further, although the drive circuits 11 and 16 realize bidirectional driving, they cannot be driven in the entire power supply voltage region.

Further, in a general drive circuit having one non-inverting input terminal, the voltage held in each of the two capacitors is read as in the drive circuit 31 shown in FIG. 22, and one of them is read in accordance with the control signal. Cannot be alternately selected and output, the circuit configuration of the sample and hold becomes complicated, the sampled voltage may be attenuated depending on the circuit configuration, and the signal transmission accuracy may deteriorate.

An object of the present invention is to provide a drive circuit capable of controlling the output current by performing amplification based on two input signals input to the two input terminals of the differential amplifying means. is there.

Another object of the present invention is to use two different signals as one of the two input signals inputted to the differential amplifying means.
It is an object of the present invention to provide a drive circuit that can alternately input two signals to perform amplification in two different combinations and control the output current.

[0055]

SUMMARY OF THE INVENTION The present invention provides a first gate.
One channel type first field effect transistor to which the input signal of 1 is supplied and the one channel type second field effect transistor to which the second input signal is supplied to the gate are formed as a differential pair, and each source is connected to each source. Is provided with a predetermined first potential, and an active load for supplying a current to each transistor is interposed between each drain and a predetermined second potential; and the first field effect. The drain potential of the transistor is applied to the gate and the second potential is applied to the source of the other channel type third field effect transistor, and the source is applied with the first potential, and the drain is the third field effect transistor. A fourth channel-type field effect transistor connected to the drains of the first and second output terminals, the output means outputting the potential of the commonly connected drains; Load is based on the amount of current supplied to the second field effect transistor, a drive circuit which comprises a current control means for driving the fourth field-effect transistors of said output means. According to the invention, the third field effect transistor of the output means is driven by the first and second input signals supplied to the differential amplification means. The output means is configured to include a fourth field effect transistor that controls a current flowing between the drain of the third field effect transistor and the first potential. The fourth field effect transistor is driven by the current amount control means based on the amount of current supplied by the active load to the second field effect transistor. Therefore, the current flowing through the output means is controlled not only by the third field effect transistor but also by the fourth field effect transistor, and when the voltage levels of the first and second input signals are substantially equal, The current flowing through the output means can be reduced. Further, when the difference between the first and second input signals is large, the amount of current flowing through the fourth field effect transistor increases, and the driving ability for the load connected to the driving circuit can be improved.

Further, the active load of the present invention is configured to include the other channel type fifth and sixth field effect transistors in which the respective gates are commonly connected and the respective sources are supplied with the second potential. The drain of the fifth field effect transistor is connected to the drain of the first field effect transistor, the drain of the sixth field effect transistor is connected to the drain of the second field effect transistor and each of the commonly connected gates, The current amount control means forms a current mirror circuit by connecting the gate to the gate and the drain of the sixth field effect transistor, and the other channel type seventh electric field in which the second potential is applied to the source. By connecting the effect transistor and the gate of the fourth field effect transistor to the gate and the drain, A rent mirror circuit is configured, and the drain of the seventh field effect transistor is connected to the drain, and the source includes the one channel type eighth field effect transistor to which the first potential is applied. Characterize. According to the invention, since the fifth and sixth field effect transistors are current mirror circuits, equal currents flow in the first and second field effect transistors, and the sixth and seventh field effect transistors form a current mirror circuit. Therefore, the same current as the current flowing through the second field effect transistor flows from the seventh field effect transistor to the eighth field effect transistor, and the eighth and fourth field effect transistors are current mirror circuits. The fourth field effect transistor is driven by applying a current equal to the current supplied from the sixth field effect transistor to the second field effect transistor to the gate. Therefore, the current flowing through the output means can be controlled not only by the third field effect transistor but also by the fourth field effect transistor, and the current flowing through the output means in the equilibrium state can be reduced. Further, when the difference between the first and second input signals is large, the amount of current flowing through the fourth field effect transistor increases, and the driving ability for the load connected to the driving circuit can be improved.

Further, the active load of the present invention is provided in parallel with the fifth and sixth field effect transistors, respectively, and is of a second channel type of the other channel type which is in a conductive state by applying a predetermined potential to each gate. It is characterized in that it includes ninth and tenth field effect transistors. According to the present invention, the active load ninth and tenth field effect transistors are provided with a predetermined potential at their gates, and a predetermined current is applied to the first and second field effect transistors together with the fifth and sixth field effect transistors. Supply to the transistor. The amount of current flowing through the fourth field effect transistor of the output means is controlled by the amount of current supplied from the sixth field effect transistor and the tenth field effect transistor to the second field effect transistor. Therefore, by controlling the potentials applied to the gates of the ninth and tenth field effect transistors, the amount of current given to the gate of the fourth field effect transistor is controlled, and the amount of current flowing through the output means can be controlled. . In addition, the first and second
When the difference between the input signals is large, the amount of current flowing through the fourth field effect transistor is large, and the driving ability for the load connected to the driving circuit can be improved.

Further, the present invention is characterized in that the output of the output means is given to the gate of the second field effect transistor as the second input signal to form a voltage follower circuit. According to the invention, the output of the output means is given to the gate of the second field effect transistor as the second input signal to form the voltage follower circuit. Therefore, unless the voltage levels of the signals applied to the first and second field effect transistors have the same potential and the first and second input signals applied to the first and second field effect transistors do not change abruptly. The drive circuit operates in a balanced state, and the current flowing through the output means, that is, the current consumed by the drive circuit can be reduced.

Further, the present invention is a drive circuit comprising a first drive circuit and a second drive circuit, wherein the first drive circuit is an N-channel type whose gate is supplied with a first input signal. A first field-effect transistor and an N-channel second field-effect transistor having a gate to which a second input signal is supplied are used as a differential pair, a ground potential is applied to each source, and a drain is connected to each drain. First differential amplifier means in which a first active load for supplying a current to each transistor is interposed between the power supply potential and a predetermined power supply potential, and the drain potential of the first field effect transistor is applied to the gate, A P-channel type third field effect transistor in which a potential is applied to the source, and an N channel in which the ground potential is applied to the source and the drain is connected to the drain of the third field effect transistor. Driving the fourth field effect transistor of the first output means based on the amount of current supplied to the second field effect transistor by the first active load. The second drive circuit includes a P-channel fifth field effect transistor having a gate supplied with the first input signal, and a gate supplied with the second input signal. And a P-channel type sixth field effect transistor configured as a differential pair, each source is supplied with the power supply potential, and a current is supplied to each transistor between each drain and the ground potential. 2nd differential amplifying means in which an active load is interposed, and the drain of the fifth field effect transistor is applied to the gate thereof, and the ground potential thereof is applied to the source thereof. Second output means including a field effect transistor and a P-channel type eighth field effect transistor having a source supplied with the power supply potential and a drain connected to the drain of the seventh field effect transistor; Second current amount control means for driving the eighth field effect transistor of the second output means based on the amount of current supplied to the sixth field effect transistor by the active load, and the first and second output means. The drive circuit is characterized in that the drains of the field effect transistors are connected to each other and the potential at the connection point is output. According to the invention, the drive circuit includes the N-channel type first and second field-effect transistors as a differential pair, and is provided with the N-channel type fourth field-effect transistor for controlling the amount of current flowing through the first output means. And a second drive circuit provided with a P-channel type eighth field effect transistor for controlling the amount of current flowing through the second output means, and the first and second input signals are commonly used. The drains of the field effect transistors of the first and second output means are connected to each other and the potential at the connection point is output. Therefore, no matter what the voltage level of the first and second input signals is in the range from the ground potential to the power supply potential, the voltage from the power supply potential to the output terminal and from the output terminal to the ground potential is changed. There is at least one path through which a current flows from the power supply potential to the ground potential, and the drive circuit can be operated if the first and second input signals have voltage levels within the above range.

Further, the first active load of the present invention is configured to include P-channel type ninth and tenth field effect transistors in which respective gates are commonly connected and each source is supplied with the power supply potential. The drain of the ninth field effect transistor is connected to the drain of the first field effect transistor, and the drain of the tenth field effect transistor is connected to the drain of the second field effect transistor and each of the commonly connected gates. The first current amount control means forms a current mirror circuit by connecting a gate to a gate and a drain of the tenth field effect transistor, and a P-channel type eleventh P-channel type whose source is supplied with the power supply potential. Field effect transistor and the gate of the fourth field effect transistor are connected to the gate and the drain. A current mirror circuit is configured by and the drain of the eleventh field effect transistor is connected to the drain, and the source includes an N-channel type twelfth field effect transistor to which the ground potential is applied. The second active load is configured to include N-channel type thirteenth and fourteenth field effect transistors to which the respective gates are commonly connected and each source is supplied with the ground potential, and the thirteenth field effect transistor. The drain of the fifth field-effect transistor is connected to the drain of the fourteenth field-effect transistor, the drain of the fourteenth field-effect transistor is connected to the drain of the sixth field-effect transistor and the commonly connected gates, and the second current amount The control means is such that the gate is connected to the gate and drain of the fourteenth field effect transistor. What constitutes a current mirror circuit, the ground potential is applied to the source N
A channel type fifteenth field effect transistor and the gate of the eighth field effect transistor are connected to the gate and the drain to form a current mirror circuit, and the drain of the fifteenth field effect transistor serves as the drain. It is characterized in that it is configured to include a P-channel type 16th field effect transistor connected to the gate and having the source to which the power supply potential is applied. According to the invention, in the first differential amplifying means, since the ninth and tenth field effect transistors are current mirror circuits, equal currents flow through the first and second field effect transistors, and the tenth and eleventh field effect transistors are provided. Since the effect transistor forms a current mirror circuit, the same current as the current flowing through the second field effect transistor flows from the eleventh field effect transistor to the twelfth field effect transistor, and further the twelfth field effect transistor and the fourth field effect transistor are connected. Since the field effect transistor and the field effect transistor form a current mirror circuit, the fourth field effect transistor is driven by supplying the current supplied from the tenth field effect transistor to the second field effect transistor to the gate. Further, in the second differential amplifying means, since the thirteenth and fourteenth field effect transistors are current mirror circuits, equal currents flow through the fifth and sixth field effect transistors, and the fourteenth and fifteenth field effect transistors have currents. Since the mirror circuit is configured, the fifteenth field effect transistor to the sixteenth field effect transistor
Since the same current as the current flowing through the sixth field effect transistor flows through the field effect transistor, and the 16th field effect transistor and the eighth field effect transistor are current mirror circuits, the eighth field effect transistor is The current supplied from the 14th field effect transistor to the 6th field effect transistor is applied to the gate to be driven. Therefore, the current flowing through the first output means is controlled by not only the third field effect transistor but also the fourth field effect transistor, and the current flowing through the second output means is not limited to the seventh field effect transistor. It is also controlled by the eight field effect transistor, and when the voltage levels of the first and second input signals are substantially equal, the currents flowing through the first and second output means can be reduced respectively. When the difference between the first and second input signals is large, the amount of current flowing through the fourth and eighth field effect transistors is large,
It is possible to improve the driving ability for the load connected to the driving circuit.

Further, the first active load of the present invention is provided in parallel with the ninth and tenth field effect transistors, respectively, and is a P-channel type in which each gate is provided with a predetermined potential to be in a conductive state. The seventeenth and eighteenth
And a second active load including:
It includes N-channel type nineteenth and twentieth field effect transistors which are respectively provided in parallel with the thirteenth and fourteenth field effect transistors and are in a conductive state by applying a predetermined potential to each gate. Characterize. According to the invention, the seventeenth and first active loads
The 8-field effect transistor has a gate supplied with a predetermined potential, and supplies a predetermined current to the first and second field effect transistors together with the ninth and tenth field effect transistors. The amount of current flowing through the fourth field effect transistor of the first output means is controlled by the amount of current supplied from the tenth and eighteenth field effect transistors to the second field effect transistor. The nineteenth and twentieth field effect transistors of the second active load have predetermined potentials applied to their gates, and supply a predetermined current to the fifth and sixth field effect transistors together with the thirteenth and fourteenth field effect transistors. . The amount of current flowing through the eighth field effect transistor of the second output means is 14th and 2nd.
It is controlled by the amount of current supplied from the 0 field effect transistor to the sixth field effect transistor. Therefore,
By controlling the potentials applied to the gates of the seventeenth and eighteenth and nineteenth and twentieth field effect transistors, the amount of current given to the gates of the fourth and eighth field effect transistors is controlled, and the first and second field effect transistors are controlled. The amount of current flowing through the output means can be controlled.

The present invention is also characterized in that the potential at the connection point is applied to the gates of the second and sixth field effect transistors as the second input signal to form a voltage follower circuit. According to the present invention, the output of the drive circuit is applied to the gates of the second and sixth field effect transistors to form a voltage follower circuit. Therefore, the first of the first drive circuit
And the voltage levels of the signals applied to the second field effect transistors have the same potential, and the voltage levels of the signals applied to the fifth and sixth field effect transistors of the second drive circuit have the same potential, and the first and second inputs As long as the signal does not change abruptly, each drive circuit operates in a balanced state, and the current flowing through the output means, that is, the current consumed by the drive circuit can be reduced.

According to the present invention, the one-channel first field effect transistor having the gate supplied with the first input signal and the one-channel second field effect transistor having the gate supplied with the second input signal are provided. An effect transistor and a channel-type third field effect transistor whose gate is supplied with a third input signal, each source being supplied with a predetermined first potential, and each drain being supplied with a predetermined first potential. Two
An active load for supplying a current to each transistor is interposed between the first field effect transistor and the active load, and a first switching element is interposed between the first field effect transistor and the active load. Between the active load and the second
Switching element is interposed and one of the first and second switching elements is turned on to form a differential pair with the first and second transistors, or
And a differential amplifying means for switching whether to configure a differential pair with the third transistor, and the potential of the drain of any one of the first and third field effect transistors is given to the gate, and the second potential is the source. A fourth channel field effect transistor of the other channel type, and a fifth field effect transistor of the one channel type whose source is supplied with the first potential and whose drain is connected to the drain of the fourth field effect transistor. Output means for outputting the potential of the drain connected in common, and the active load includes the second means.
And a current amount control means for driving the fifth field effect transistor of the output means based on the amount of current supplied to the field effect transistor. According to the present invention, in the differential amplification means of the drive circuit, the combination of the field effect transistors forming the differential pair is changed by controlling conduction / cutoff of the first and second switching means. Whether the fourth field effect transistor of the output means is driven by the first and second input signals supplied to the first and second field effect transistors, or
The fourth field effect transistor is driven by the second and third input signals supplied to the third field effect transistor. The output means includes a fifth field effect transistor connected to the drain of the fourth field effect transistor, supplied with the first potential at the source, and driven by the current amount control means. The current flowing between the drain and the first potential is controlled. Therefore, by controlling conduction / cutoff of the first and second switching elements, it is possible to switch the first and third input signals to perform a differential amplification operation.

Further, the active load of the present invention is configured so as to include the other channel type sixth and seventh field effect transistors in which respective gates are commonly connected and each source is supplied with the second potential. The drain of the sixth field effect transistor is commonly connected to the first and second switching elements, and the drain of the seventh field effect transistor is connected to the drain of the second field effect transistor and each of the commonly connected gates. The current amount control means is
A gate is connected to the gate and drain of the seventh field effect transistor to form a current mirror circuit, and the other channel type eighth field effect transistor in which the second potential is applied to the source, and the fifth field effect transistor. The gate of the field effect transistor is connected to the gate and the drain to form a current mirror circuit, the drain of the eighth field effect transistor is connected to the drain, and the source is supplied with the first potential. And a ninth field effect transistor of the mold. According to the invention, sixth and seventh
Since the field effect transistor is a current mirror circuit, an equal current flows through the first and second or second and third field effect transistors, and the eighth and eighth field effect transistors form a current mirror circuit. The same current as the current flowing through the second field effect transistor flows from the field effect transistor to the ninth field effect transistor, and the ninth and fifth field effect transistors are current mirror circuits. Is driven by supplying the current supplied to the second field effect transistor to the gate. Therefore, the current flowing through the output means can be controlled not only by the fourth field effect transistor but also by the fifth field effect transistor, and the current flowing through the output means in the equilibrium state can be reduced. Further, when the difference between the first or third input signal and the second input signal is large, the amount of current flowing through the fifth field effect transistor increases, and the driving ability for the load connected to the driving circuit can be improved. .

The active load of the present invention is provided in parallel with the sixth and seventh field effect transistors, respectively, and is of the other channel type which is in a conductive state when a predetermined potential is applied to each gate. It is characterized in that it includes tenth and eleventh field effect transistors. According to the present invention, the active load tenth and eleventh field effect transistors are provided with a predetermined potential at their gates, and a predetermined current is applied to the first and third field effect transistors together with the sixth and seventh field effect transistors. Supply to the transistor and the second field effect transistor. Fifth of output means
The amount of current flowing through the field effect transistor is determined by the second field effect transistor from the seventh field effect transistor and the eleventh field effect transistor.
It is controlled by the amount of current supplied to the field effect transistor. Therefore, in equilibrium, the tenth and eleventh
By controlling the potential applied to the gate of the field effect transistor, the amount of current supplied to the gate of the fifth field effect transistor is controlled, and the amount of current flowing through the output means can be reduced. Further, when the difference between the first or third input signal and the second input signal is large, the amount of current flowing through the fifth field effect transistor increases, and the driving ability for the load connected to the driving circuit can be improved. .

The present invention is also characterized in that the output of the output means is applied to the gate of the second field effect transistor as the second input signal to form a voltage follower circuit. According to the invention, the output of the output means is given to the gate of the second field effect transistor as the second input signal to form the voltage follower circuit. Therefore, the voltage levels of the signals applied to the second and first or third field effect transistors become the same potential, and the first or third input signal and the second input applied to the first or third and second field effect transistors. As long as the signal does not change abruptly, the drive circuit operates in a balanced state, and the current flowing through the output means, that is, the current consumed by the drive circuit can be reduced.

Further, the present invention is a drive circuit comprising a first drive circuit and a second drive circuit, wherein the first drive circuit is an N-channel type whose gate is supplied with a first input signal. A first field effect transistor, an N-channel type second field effect transistor whose gate is supplied with a second input signal, and an N-channel type third electric field whose gate is supplied with a third input signal. An effect transistor, each source is provided with a predetermined ground potential, and a first active load that supplies a current to each transistor is interposed between each drain and a predetermined power supply potential. A first switching element is interposed between the effect transistor and the first active load, and a second switching element is interposed between the third field effect transistor and the first active load. And A first differential amplifier that switches between configuring a differential pair with the first and second transistors or configuring a differential pair with the second and third transistors by conducting one of the second switching elements. Means, and a P-channel type fourth field effect transistor in which the potential of the drain of any one of the first and third field effect transistors is applied to the gate, and the power supply potential is applied to the source, and the source First output means including an N-channel type fifth field effect transistor having a ground potential applied thereto and a drain connected to the drain of the fourth field effect transistor; and the first active load having the second field effect transistor. First current amount control means for driving the fifth field effect transistor of the first output means based on the amount of current supplied to the effect transistor, The driving circuit includes a sixth field effect transistor of the P-channel type, wherein the gate first input signal is supplied, the gate second
A seventh P-channel field effect transistor to which an input signal is supplied; and a eighth P-channel field effect transistor to the gate of which the third input signal is supplied,
The power supply potential is applied to each source, a second active load that supplies a current to each transistor is interposed between each drain and the ground potential, and the sixth field effect transistor and the second active load are connected to each other. A third switching element is interposed between the second field effect transistor and the second active load, and a fourth switching element is interposed between the eighth field effect transistor and the second active load. Second differential amplifying means for switching one of the sixth and seventh transistors to form a differential pair or the seventh and eighth transistors to form a differential pair by making one of them conductive; An N-channel type ninth field effect transistor in which the potential of the drain of any one of the eighth field effect transistors is applied to the gate and the ground potential is applied to the source; To the source of the power supply potential, and a drain of the P-channel type tenth field effect transistor having a drain connected to the drain of the ninth field effect transistor; and the second active load. 7th
A second current amount control means for driving the tenth field effect transistor of the second output means on the basis of the amount of current supplied to the field effect transistor, and each of the field effect transistors of the first and second output means. The drive circuit is characterized in that the drains are connected to each other and the potential at the connection point is output. According to the invention, the first, second and third input signals are commonly applied to the first drive circuit and the second drive circuit, and the drains of the field effect transistors of the first and second output means are connected to each other. , Output the potential of the connection point. Therefore, what voltage level the voltage level of the second input signal and the signal of the corresponding switching element of the first and third input signals is in conduction is within the range from the ground potential to the power supply potential. Even then, there is at least one path through which a current flows from the power supply potential to the output terminal and from the output terminal to the ground potential to the ground potential.
If the first, second and third input signals have voltage levels within the above range, the drive circuit can be operated.

The first active load of the present invention is configured to include eleventh and twelfth P-channel type field effect transistors having their gates connected in common and having their sources supplied with the power supply potential. The drain of the eleventh field effect transistor is commonly connected to the first and second switching elements, and the drain of the twelfth field effect transistor is connected to the drain of the second field effect transistor and each of the commonly connected gates. The first current amount control means is connected to the gate and drain of the twelfth field effect transistor to form a current mirror circuit, and the source is supplied with the power supply potential. The thirteenth field effect transistor and the gate of the fifth field effect transistor are connected to the gate and the drain. By configuring a current mirror circuit, the drain of the thirteenth field effect transistor is connected to the drain, and the source includes an N-channel type fourteenth field effect transistor to which the ground potential is applied, The second active load is configured to include N-channel type fifteenth and sixteenth field effect transistors to which the respective gates are commonly connected and each source is supplied with the ground potential. The drain is commonly connected to the third and fourth switching elements, the drain of the sixteenth field effect transistor is connected to the drain of the seventh field effect transistor, and the second current amount control means is the sixteenth field effect transistor. A current mirror circuit is configured by connecting the gate to the gate and the drain of the transistor. A current mirror circuit is configured by connecting an N-channel type seventeenth field effect transistor whose source is given the ground potential and a gate of the tenth field effect transistor to a gate and a drain, The drain of the seventeenth field effect transistor is connected to the drain, and the source includes a P-channel type eighteenth field effect transistor to which the power supply potential is applied. According to the present invention, in the first differential amplifying means, the eleventh and twelfth field effect transistors are current mirror circuits, so that equal currents flow in the first or third and second field effect transistors, and the twelfth and twelfth field effect transistors are provided. Since the thirteenth field effect transistor constitutes the current mirror circuit,
Since the same current as the current flowing in the second field effect transistor flows from the thirteenth field effect transistor to the fourteenth field effect transistor, and the fourteenth field effect transistor and the fifth field effect transistor form a current mirror circuit. The fifth field effect transistor is driven by supplying the current supplied from the twelfth field effect transistor to the second field effect transistor to the gate. Also,
In the second differential amplification means, since the fifteenth and sixteenth field effect transistors are current mirror circuits, equal currents flow in the sixth and seventh or eighth and seventh field effect transistors, and the sixteenth and seventeenth field effect transistors are provided. Since the effect transistor constitutes a current mirror circuit,
The same current as the current flowing through the seventh field effect transistor flows from the field effect transistor to the eighteenth field effect transistor, and further, the eighteenth field effect transistor and the tenth field effect transistor.
Since the field effect transistor is a current mirror circuit, the tenth field effect transistor is driven by supplying the current supplied from the sixteenth field effect transistor to the seventh field effect transistor to the gate. Therefore, the current flowing through the first output means is controlled not only by the fourth field effect transistor but also by the fifth field effect transistor, and the current flowing through the second output means is controlled not only by the ninth field effect transistor but also by the ninth field effect transistor. 10 field effect transistors, and when the second input signal and the signal in which the corresponding switching element of the first and third input signals is conducting are in the equilibrium state where the voltage levels are substantially equal, The current flowing through the first and second output means can be reduced respectively. Further, when the difference between the second input signal and the signal of the first and third input signals to which the corresponding switching element is conducting is large, the amount of current flowing through the fifth and tenth field effect transistors increases and the driving The drivability for the load connected to the circuit can be improved.

The first active load of the present invention is the eleventh
P-channel type nineteenth and second P-channel type transistors which are provided in parallel with the twelfth and twelfth field effect transistors, respectively, and are in a conductive state by applying a predetermined potential to each gate.
N-channels including 0 field effect transistors, wherein the second active load is provided in parallel with the 15th and 16th field effect transistors, respectively, and is in a conductive state by applying a predetermined potential to each gate. 21st of the mold
And a twenty-second field effect transistor. According to the present invention, the nineteenth and twentieth field effect transistors of the first active load are provided with a predetermined potential at their gates, and a predetermined current is applied to the first and second field effect transistors together with the eleventh and twelfth field effect transistors. Alternatively, it is supplied to the third and second field effect transistors. The amount of current flowing through the fifth field effect transistor of the first output means is controlled by the amount of current supplied from the twelfth and twentieth field effect transistors to the second field effect transistor. Second
The twenty-first and twenty-second field effect transistors of the active load have their gates supplied with a predetermined potential,
And a predetermined current is supplied to the sixth and seventh or eighth and seventh field effect transistors together with the sixteenth field effect transistor. The amount of current flowing through the tenth field effect transistor of the second output means is controlled by the amount of current supplied from the sixteenth and twenty-second field effect transistors to the seventh field effect transistor. Therefore, by controlling the potentials applied to the gates of the nineteenth and twentieth and the twenty-first and twenty-second field effect transistors, the amount of current given to the gates of the ninth and tenth field effect transistors is controlled, and the first and The amount of current flowing through the second output means can be reduced.

The present invention is also characterized in that the potential at the connection point is applied to the respective gates of the second and seventh field effect transistors as the second input signal to form a voltage follower circuit. According to the present invention, the output of the drive circuit is applied to the respective gates of the second and seventh field effect transistors to form a voltage follower circuit. Therefore, the voltage levels of the signals applied to the first and second or third and second field effect transistors of the first drive circuit have the same potential, and the sixth and seventh or eighth and seventh of the second drive circuit are provided. As long as the voltage levels of the signals applied to the field effect transistors have the same potential and the first, second and third input signals do not change abruptly, each drive circuit operates in a balanced state and flows through the output means. The current, that is, the current consumed by the driving circuit can be reduced.

[0071]

1 is a circuit diagram of a drive circuit 51 according to a first embodiment of the present invention. Drive circuit 51
Includes a differential amplifier circuit 52, a level conversion circuit 53, and an output buffer 54.

The differential amplifier circuit 52 is an N-channel MOS transistor input differential amplifier circuit, and is an N-channel MO transistor.
The non-inverting input terminal 57 is connected to the gate of the S transistor N1, and the inverting input terminal 56 is connected to the gate of the N-channel MOS transistor N2. P channel MOS
The transistors P1 and P2 are active loads of the transistors N1 and N2. The drain potential of the transistor N1 is applied to the gate of the transistor P4 of the output buffer 54. The drain potential of the transistor N2 is applied to the gate of the transistor P3 of the level conversion circuit 53.

The first bias input terminal 58 is connected to the gate of the N-channel MOS transistor N3, which is a constant current source, to which a predetermined first bias voltage BV1 is applied, and a predetermined bias current forms a differential pair. It is given to the transistors N1 and N2.

Level conversion circuit 53 which is a current amount control means
Is a P-channel MOS transistor P3 and an N-channel MOS transistor N whose gate and drain are connected.
4 is included. The potential of the drain of the transistor N2 is applied to the gate of the transistor P3 as described above. The drain of the transistor P3 and the gate / drain of the transistor N4 are connected to each other.

The output buffer 54, which is an output means, includes a P-channel MOS transistor P4 and an N-channel MOS transistor.
It is configured to include a transistor N5. Transistor P
The gate of 4 receives the potential of the drain of the transistor N1. The gate of the transistor N5 is supplied with the gate / drain potential of the transistor N4. The drains of the transistors P4 and N5 are connected to each other, and the potential at the connection point is output from the output terminal 59 to the output signal OUT.
Is taken out as

Next, the operation of the drive circuit 51 will be described. In the differential amplifier circuit 52, an output obtained by amplifying the voltage difference between the non-inverting input voltage VIA and the inverting input voltage VIB is obtained.
Non-inverted input voltage V with respect to the inverted input voltage VIB
When the voltage of IA increases, the drain voltage of the transistor N2, which is the output on the inverting side of the differential amplifier circuit 52, increases,
The drain voltage of the transistor N1 drops. On the contrary, when the non-inverting input voltage VIA becomes low, the transistor N
The drain voltage of 2 drops and the drain voltage of the transistor N1 rises. Transistor N of differential amplifier circuit 52
The drain voltage of 2 is inverted by the transistor P3 of the level conversion circuit 53, and the transistor N3 of the output buffer 54 is inverted.
5 gates.

The drain voltage of the transistor P1 of the differential amplifier circuit 52 is applied to the gate of the transistor P4 of the output buffer 54. Therefore, the non-inverting input voltage VIA
When the voltage of 1 increases, the resistance value between the source and drain of the transistor P4 decreases, while the resistance value between the source and drain of the transistor N5 increases. Conversely, when the voltage of the non-inverting input voltage VIA decreases, the resistance value between the source and drain of the transistor P4 increases, while the resistance value between the source and drain of the transistor N5 decreases. As described above, the output voltage corresponding to the voltage difference between the inverting input voltage and the non-inverting input voltage is obtained, and the output current control is realized.

Transistors N1 and N2, which are a differential pair,
At the connection point VS with the transistor N3 which is a constant current source, the current flowing from the transistor N1 is I1 and the current flowing from the transistor N2 is I2. Also, the connection point VS
The current flowing from the transistor to the transistor N3 is I3. Also, a connection point V between the transistor N1 and the transistor P1
The current flowing from the transistor P1 to the first transistor is I1a.
The current flowing from the transistor P2 to the connection point V2 between the transistor N2 and the transistor P2 is I2a. The current supplied to the transistor N4 of the level conversion circuit 53 is I4, and the current supplied to the transistor N5 of the output buffer 54 is I5.

Non-inverting input voltage VIA and inverting input voltage VI
If B and the equilibrium state are almost equal, the transistor N
The currents flowing through 1 and N2 are as follows: I1 = I1a = I2a = I2 (1) I3 / 2 = I1 = I2 (2) because the transistors P1 and P2 form a current mirror circuit. Further, since the transistors P2 and P3 form a current mirror circuit, I4 = I2 = I3 / 2 (3) and the current flowing through the transistor N5 of the output buffer 54 is the current I3 / given to the transistor N4. It will be controlled by 2.

When the equilibrium state is lost and a voltage difference occurs between the non-inverting input voltage VIA and the inverting input voltage VIB, the difference affects the potential at the connection point VS, and the balance between the currents I1 and I2 is lost. The change of the current I1 changes the potential of the connection point V1, and the change of the current I2 and the potential of the connection point V1 determines the potential of the connection point V2. On the contrary, the change of the current I2 changes the potential of the connection point V2, and the change of the current I1 and the potential of the connection point V2 determines the potential of the connection point V1.

In the drive circuit 51, all the transistors are operating in the saturation region. Therefore, a minute change in the current applied to the gate is caused by the source-drain voltage of the transistor P2 or the source-drain voltage of the transistor P1. It is taken out as a big change of.

The inverting input voltage VIB is the non-inverting input voltage VI.
When it becomes higher than the voltage of A (potential of the connection point V1> potential of the connection point V2), the current amount of the current I2 increases and the current I3
Is equal to the current flowing as.

I2 = I3 (4) Therefore, since the transistor P2 and the transistor P3 form a rent mirror circuit, the current flowing as the current I4 is I4 = I2 = I3 (5). Further, since the transistor N4 and the transistor N5 form a current mirror circuit, the transistor N4
The current flowing through 5 is controlled by the current I3. Therefore, a maximum of twice as much current can flow through the transistor N5 as compared with the equilibrium state.

The reduction of current consumption in the drive circuit 51 will be described below. The current I3 flowing through the differential amplifier circuit 52 is 2.5 μA, and the maximum current that can be passed through the transistor N5 is 30 μA.

As described above, in the drive circuit 51, the maximum current that can flow in the transistor N5 is twice the current that flows in the transistor N5 at the time of equilibrium.
In the equilibrium state, I5 = 30 μA / 2 = 15 μA (6) may be applied to the transistor N5 as a bias current.

The current flowing through the differential amplifier circuit 52 is I3 =
Since it is given as 2.5 μA, the currents supplied from the transistors P1 and P2 at the time of equilibrium are as follows: I1a = I2a = I3 / 2 = 1.25 μA (7)

Here, the size of the transistor P2 (W /
L (transistor gate width) / (transistor gate length): If the sizes of the transistors P2 and P3 are set so that the size of the transistor P3 is 1: 2, According to the ratio, the current I4 in the drive circuit 51 becomes I4 = I2a × 2 = 2.5 μA (8) based on the equation (7).

Further, when the size of each of the transistors N4 and N5 is set so that the size of the transistor N4: the size of the transistor N5 = 1: 6, the current I5 can be calculated by the ratio of the transistors N4 and N5. Based on 8), I5 = I4 * 6 = 2.5 [mu] A * 6 = 15 [mu] A (9), and a necessary current can be passed as a desired bias current. Overall current consumption I in the drive circuit 51
Is I = I3 + I4 + I5 = 20 μA (10)

In the above-mentioned conventional drive circuit 1, the current Ij1 flowing through the transistor Tn3 of the differential amplifier circuit 2 is 2.5 μA and the transistor T of the output buffer 3 is T.
If the maximum current Ij2 that can be supplied to n4 is 30 μA, the total current consumption in the drive circuit 1 is 32.5.
μA. Drive circuit 1 in the above-mentioned first prior art
The current consumption in the equilibrium state can be reduced more than that.

FIG. 2 shows a drive circuit 5 constructed as described above.
1 is a block diagram showing a configuration of a TFT (thin film transistor) type liquid crystal display device 60 in which 1 is used, and FIG. 3 is a block diagram showing a configuration of a source driver 61 in the liquid crystal display device 60.

The liquid crystal display device 60 includes a source driver 61.
A gate driver 62, a liquid crystal display panel 63, a driving power supply circuit 64, and a display control circuit 65.

On the liquid crystal display panel 63, the source electrode s1
.. to sn (generally referred to by reference numeral s) and gate electrodes g1 to gm (generally referred to by reference numeral g) are provided so as to be orthogonal to each other. In the vicinity of the point where the electrodes are orthogonal to each other, the thin film transistor Hij
(I is 1 or more and n or less, j is 1 or more and m or less), the gates of the thin film transistors Hij on the same horizontal line are connected to the same gate electrode g, and are sequentially scanned by the gate driver 62. Further, the sources of the thin film transistors Hij on the same vertical line are connected to the same source electrode s, and a voltage according to the gradation displayed by the source driver 61 is supplied to each thin film transistor Hij.

The drain of the thin film transistor Hij is connected to the pixel electrode Kij. Each picture element electrode Kij faces a common electrode L formed so as to cover the picture element electrode Kij with a liquid crystal layer interposed therebetween, and a voltage is held in a region of the liquid crystal layer sandwiched between the picture element electrode and the common electrode. Is displayed. Note that, in FIG. 2, the common electrode L is shown individually associated with each pixel electrode Kij.

The display control circuit 65 includes a liquid crystal display panel 63.
The display data for performing the display and the clock signal defining the timing are supplied to the source driver 61 and the gate driver 62. The drive power supply circuit 64 supplies a voltage for driving the liquid crystal display panel 63 to the source driver 61, the gate driver 62, and the common electrode L.

The source driver 61 will be described in detail with reference to FIG. The source driver 61 includes a bidirectional shift register 66 and an intermediate withstand voltage circuit 67.
The medium breakdown voltage circuit 67 is configured to be able to operate at a voltage of, for example, 14 to 20V. Medium voltage circuit 67
Is a level shifter 68 and analog switches AS1 to A
Sn (generally referred to by reference numeral AS) and analog switches AW1 to AWn (generally referred to by reference numeral AW)
, And sampling capacitors CS1 to CSn
(A reference numeral CS is used when collectively referred to), hold capacitors CH1 to CHn (a reference numeral CH is used when collectively referred to), and operational amplifiers OP1 to OPn (a reference numeral OP is used when collectively referred to). Composed.

The display control circuit 65 supplies a start pulse, a shift clock, and a control signal to the bidirectional shift register 66. The bidirectional shift register 66 sequentially shifts the input start pulse based on the shift clock and outputs it. Bidirectional shift register 6
6 operates with a power supply of 5V, for example. Level shifter 6
8 converts the output signal level of the bidirectional shift register 66 into a voltage of 14 to 20 V and outputs it.

The analog switch AS is a level shifter 6
The output of 8 controls the opening and closing of the analog switch AS. The video signal supplied from the display control circuit 65 is input to the sampling capacitor CS via the analog switch AS until the analog switch AS is opened, and is held by the sampling capacitor CS after the analog switch AS is opened.

The output of the sampling capacitor CS is given to the hold capacitor CH via the analog switch AW. Conduction / interruption of the analog switch AW is controlled by the output enable signal, the output of the sampling capacitor CS is input to the hold capacitor CH while the analog switch AW is in conduction, and the voltage at that time when the analog switch AW is interrupted. Is retained.

The operational amplifier OP is the drive circuit 51 whose circuit diagram is shown in FIG. 1 described above, and the voltage held in the hold capacitor CH is input to the non-inverting input terminal 57. The output terminal 59 is connected to each source electrode s, and the driving circuit 5
1 inverting input terminal 56. Since the output is input to the inverting input terminal 56, the drive circuit 51 operates as a voltage follower.

Although the case where the drive circuit 51 is a differential pair of N-channel transistors has been described, the drive capability of the output transistor is similarly improved even when the differential pair is a P-channel differential amplifier circuit. It goes without saying that it is possible to raise it.

FIG. 4 is a circuit diagram of a drive circuit 68 which is another structural example of the first embodiment of the present invention. Drive circuit 6
Reference numeral 8 is a drive circuit in which the differential pair is composed of P-channel transistors. The drive circuit 68 includes a differential amplifier circuit 69,
It is configured to include a level conversion circuit 70 and an output buffer 71. The drive circuit 68 has a configuration in which the transistors N1 to N5 and P1 to P4 of the drive circuit 51 are replaced with transistors P11 to P15 and N11 to N14 in this order.

The second bias voltage BV2 is applied to the gate of the transistor P13, which is the current source in the differential amplifier circuit 69 of the drive circuit 68, via the second bias input terminal 72.

The drive circuit 68 operates as the drive circuit 5
The detailed description thereof will be omitted because it is the same as that of No. 1, but the drive circuit 68
Then, the drive capability of the transistor P15 is changed to the differential amplifier circuit 69.
Since it is determined on the basis of the output of the drive circuit,
It is possible to reduce the shoot-through current flowing in the output buffer 71 in the balanced state.

As described above, in the drive circuits 51 and 68 according to the first embodiment of the present invention, the current I5 flowing through the transistor N5 is the current I2 given to the transistor N2.
Since it is controlled by a, the through current flowing through the output buffers 54, 71 can be reduced.

FIG. 5 is a circuit diagram of a drive circuit 76 according to the second embodiment of the present invention. In the drive circuit 76,
The same components as those of the driving circuit 51 are designated by the same reference numerals and the description thereof will be omitted. The drive circuit 76 includes a differential amplifier circuit 77, a level conversion circuit 53, and an output buffer 54. The operation of the drive circuit 76 is performed by the drive circuit 5
The operation is similar to the operation No. 1 and the characteristic points of the drive circuit 76 will be described.

The characteristic of the drive circuit 76 is that it is a differential amplifier circuit 77.
P channel MOS transistors P5 and P6 are added in parallel to the P channel MOS transistors P1 and P2, respectively. In the differential amplifier circuit 77, currents are supplied from the transistors P5 and P6 in addition to the transistors P1 and P2 to the transistors N1 and N2 which are a differential pair. A source and a drain of the transistor P5 are commonly connected to the transistor P1, and a second bias voltage BV2 is applied to the gate of the transistor P5 via the second bias input terminal 78. The source and drain of the transistor P6 are commonly connected to the transistor P2, and the gate of the transistor P6 is the second transistor.
Bias voltage BV2 is applied. Therefore, by controlling the voltage level of the second bias voltage BV2, the amount of current supplied to the differential pair N1, N2 can be determined.

The currents supplied from the transistors P5 and P6 are currents I1b and I2b, respectively. Therefore,
In the differential amplifier circuit 77, the current I1 is the current I1a + I1b.
And the current I2 becomes the current I2a + I2b. Regarding the operation of the drive circuit 76, the operation of the drive circuit 51 and
The description is omitted because they are the same except that the currents I1 and I2 are different.

Each current in the drive circuit 76 will be described. Non-inverting input voltage VIA and inverting input voltage VIB
Are almost equal to each other, the currents flowing through the transistors N1 and N2 are P-channel transistors P1 and P2.
By configuring one current mirror circuit by combining 5 and P2 and P6, I1 = I1a + I1b = I2a + I2b = I2 (11) I3 / 2 = I1 = I2 (12) ), (12), I2a = I3 / 2-I2b (13) is obtained.

When the equilibrium state is lost and a voltage difference occurs between the non-inverting input voltage VIA and the inverting input voltage VIB, the difference affects the potential of the connection point VS, and the balance of the currents I1 and I2 is lost. The change of the current I1 changes the potential of the connection point V1, and the change of the current I2 and the potential of the connection point V1 determines the potential of the connection point V2. On the contrary, the change of the current I2 changes the potential of the connection point V2, and the change of the current I1 and the potential of the connection point V2 determines the potential of the connection point V1.

In the drive circuit 76, all the transistors are operating in the saturation region. Therefore, a minute change in the current applied to the gate causes a voltage between the source and drain of the transistor P2 or a voltage between the source and drain of the transistor P1. It is taken out as a big change of.

The inverting input voltage VIB is the non-inverting input voltage VI.
When higher than A (potential of connection point V1> connection point V2
Potential), the current amount of the current I2 increases, and the current amount of the current I1 decreases. The current I1 decreases and the differential amplifier circuit 77
Is saturated, the current I1 becomes almost zero. In the saturation state, the current I3 is the current I flowing through the transistor N2.
It becomes 2.

I3 = I2 = I2a + I2b (14) From equation (14), I2a = I3-I2b (15) Equation (15) and the above equation (13) in the equilibrium state are used to calculate the ratio. (I3-I2b) / (I3 / 2-I2b) (16) is obtained. Expression (16) shows the ratio of the magnitude of the current I2a when the differential amplifier circuit 77 is in the balanced state and when it is in the saturated state where the potential of the connection point V1> the potential of the connection point V2. .

As an example, when the operating point is designed so that I3: I2b = 12: 5, the ratio in equation (16) is (12-5) / (12 / 2-5) = 7 (17) Therefore, if the operating point is set as described above, the current I
It can be seen that 2a changes up to 7 times at equilibrium and in the saturated state.

On the other hand, the transistors P2 and P
I4 = I2a (18) by the current mirror circuit constituted by 3 and. Further, the transistors N4 and N5
Since the current I5 flowing through the transistor N5 is controlled by the current I4 by the current mirror circuit configured by, the current I5 is determined by the current I2a.

The reduction of current consumption in the drive circuit 76 will be described below. As described above, in the drive circuit 76, the maximum current that can be passed through the transistor N5 is
It can be determined by the ratio of the sizes of the transistors P1 and P5 and P2 and P6. Here, if the design is such that the size of P1: the size of P5 = the size of P2: the size of P6 = 1: 4, the maximum current flowing through the transistor N5 is the current flowing through the transistor N5 at equilibrium. Therefore, I5 = 30 μA / 6 = 5 μA (19) should be applied to the transistor N5 at the time of equilibrium as a bias current.

The current flowing through the differential amplifier circuit 77 is I3 =
Given that it is 2.5 μA, transistors P1 and P5
And the ratio of the transistors P2 and P6 are set to 1: 4, respectively.
The current supplied from 6 and is I1b = I2b = 1 μA (20), and the current between the transistors P1 and P2 is I1a = I2a = 0.25 μA (21). Here, if the size of the transistor P2 is set to the size of the transistor P3 = 1: 2, the current I4 becomes as follows: I4 = I2a × 2 = 0.5 μA (22) with reference to the equation (21). Further, by designing the size of the transistor N4: the size of the transistor N5 = 1: 10, the formula (2
From 2), I5 = I4 × 10 = 0.5 μA × 10 = 5 μA (23), and a current required as a bias current can be passed through the transistor N5. The total current consumption I in the drive circuit 76 is I = I3 + I4 + I5 = 8 μA (24), and referring to the equation (9), the current consumption in the equilibrium state can be reduced as compared with the drive circuit 51 described above.

Although the case where the drive circuit 76 is a differential pair of N-channel transistors has been described, the drive capability of the output transistor is similarly improved even if the differential amplifier is a P-channel differential amplifier circuit. It goes without saying that it is possible to raise it.

FIG. 6 is a circuit diagram of a drive circuit 81 which is another configuration example of the above-described second embodiment. Drive circuit 81
Is a drive circuit in which the differential pair is composed of P-channel transistors. In the drive circuit 81, the drive circuit 6 described above is used.
The same constituent elements as those in No. 8 are designated by the same reference numerals and the description thereof will be omitted. The drive circuit 81 includes a differential amplifier circuit 82, a level conversion circuit 70, and an output buffer 71. The drive circuit 81 has a configuration in which the transistors N1 to N5 and P1 to P6 of the drive circuit 76 are replaced with transistors P11 to P15 and N11 to N16 in this order.

The second bias voltage BV2 is applied to the gate of the transistor P13 which is the current source in the differential amplifier circuit 82 of the drive circuit 81 via the second bias input terminal 72.

The drive circuit 81 operates as the drive circuit 7
6, the detailed description thereof will be omitted, but the drive circuit 81
Then, the drive capability of the transistor P15 is changed to the differential amplifier circuit 82.
Since it is determined based on the output of, the through current flowing through the output buffer 71 can be reduced and the driving capability can be improved.

As described above, it is possible to design the circuit so that the current I2a can be greatly changed. As a result, it is possible to realize a drive circuit in which the through current flowing through the output buffer 54 is reduced and the drive capability is improved. The magnitude of change in the current I2a can be controlled by changing the ratio of the magnitudes of the currents I3 and I2b.

FIG. 7 is a circuit diagram of a drive circuit 91 according to the third embodiment of the present invention. In the drive circuit 91, the same components as those of the drive circuits 51 and 68 described above are designated by the same reference numerals, and description thereof will be omitted. The drive circuit 91 is configured to include the drive circuit 51 described above and the drive circuit 68 described above. The outputs of the drive circuits 51 and 68 are applied to the output terminal 96, respectively, so that the transistors P4 and N14 perform push-pull operation. In the drive circuit 91, the inverting input terminal 92 has the transistors N2 and P12.
An inverting input voltage V1B is applied to the gate of the transistor N1, and a non-inverting input terminal 93 applies a non-inverting input voltage V1A to the gates of the transistors N1 and P11. The first bias input terminal 94 supplies the first bias voltage BV1 to the gate of the transistor N3, and the second bias input terminal 95 supplies the second bias voltage BV2 to the gate of the transistor P13.

As for the operation of the drive circuit 91, when the inverting input voltage VIB becomes higher than the non-inverting input voltage VIA, the current flowing through the transistor N1 of the drive circuit 51 increases, the drain potential of the load transistor P1 decreases, and the output transistor P4. Are conducted, and the potential at the output terminal 96 is raised. At the same time, the transistor P11 of the drive circuit 68
Current decreases, the drain potential of the load transistor N11 decreases, and the output transistor N14 is cut off. Therefore, the potential at the output terminal 96 rises to the power supply voltage VDD side.

On the other hand, when the inverting input voltage VIB becomes lower than the non-inverting input voltage VIA, the current flowing through the transistor P11 of the drive circuit 68 increases and the load transistor N11.
Rises in potential, causing the output transistor N14 to conduct and pulling down the potential at the output terminal 96. At the same time, the current flowing through the transistor N1 of the drive circuit 51 decreases, the drain potential of the load transistor P1 rises, and the output transistor P4 is cut off. Therefore, the potential at the output terminal 96 drops to the ground voltage GND side. As described above, the drive circuit 91 includes the transistors P4 and N14.
Is driven by push-pull.

FIG. 8 is a diagram for explaining the operation of drive circuit 91. In FIG. 8, the horizontal axis represents the terminals 92, 93.
Indicates the voltage input from. First, each input voltage VIA,
In the region E1 where VIB is between the ground voltage GND and the threshold voltage | VthN | of the transistors N1 and N2, the transistors N1 and N2 are cut off. At this time, the voltage at the point C applied to the gate of the transistor P4 rises to the power supply voltage VDD, and the transistor P4 is cut off. At this time, the transistors P11 and P12 are performing a normal differential amplification operation, and the voltage at the point D given to the gate of the transistor N14 is sufficiently high and the output transistor N14 is driven. In addition, the voltage at the point F becomes sufficiently low to drive the transistor P15. Therefore, when the input voltage is within the range of the area E1, the output voltage is determined by the transistors N14 and P15.

Input voltages VIA and VIB are voltage | VthN
Region E between | and voltage VDD− | VthP |
Within the range of 2, the transistors N1, N2; P11, P
Both 12 are conductive, and the output voltage is determined by the transistors P4 and N14. The threshold voltage VthP is
This is the threshold voltage of the transistors P11 and P12.

The input voltages VIA and VIB are the voltage VDD−
In the region E3 between | VthP | and the voltage VDD,
The transistors P11 and P12 are cut off. At this time, the voltage at the point D drops to the ground voltage GND, and the transistor N14 is cut off. At this time, the transistor N
1 and N2 are performing the normal differential amplification operation, the voltage at the point C is sufficiently low, and the output transistor P4 is conducting.
Further, the point G also has a sufficiently high potential to drive the transistor N5. Therefore, when the input voltage is within the range of the area E3, the output voltage is determined by the transistors P4 and N5.

As described above, the input voltage is the voltage GND to V
In the entire area of DD, at least one output terminal-current path between GND and at least one output terminal-
Since the current paths between VDD are present at the same time, it can be configured to operate regardless of the input voltage GND to VDD, and the input dynamic range can be expanded.

As described above, according to the third embodiment of the present invention, while achieving the effect of the above-described first embodiment that the current consumption is reduced, the conventional drive circuit does not operate. It is possible to configure an enhancement type drive circuit capable of normally driving a load connected to the output terminal even at the input voltage. Therefore, it is possible to obtain a wide dynamic range without forming a differential pair by using a duple region type transistor as the structure of the drive circuit. Further, when manufacturing the drive circuit, a wide input dynamic range can be obtained even if the IC is manufactured by an ordinary logic circuit IC manufacturing process, and a high-performance and low-cost mixed digital / analog IC can be configured. .

FIG. 9 is a circuit diagram of a drive circuit 101 according to the fourth embodiment of the present invention. The drive circuit 101 includes the drive circuit 76 described above and the drive circuit 81 described above. In the drive circuit 101, the above-mentioned drive circuit 7
The same components as 6, 81, 91 are designated by the same reference numerals and the description thereof will be omitted. In the drive circuit 101, the outputs of the drive circuits 76 and 81 are applied to the output terminal 96, respectively, so that the transistors P4 and N14 perform the push-pull operation. The drive circuit 101 has a configuration in which transistors P5, P6; N15, N16 are provided as additional active loads to the drive circuit 91 described above.

Since the operation of the drive circuit 101 is similar to that of the drive circuit 91 described above, the description thereof will be omitted.

The reduction of current consumption in the drive circuit 101 will be described below. In the drive circuit 101, the size of each transistor is the same as the drive circuits 76 and 81.
The same design example will be used. Therefore, the current I13 flowing through the transistor N3 and the transistor P1
The current I23 flowing through 3 is 2.5 μA each,
The current I14 flowing through the transistor N4 and the current I24 flowing through the transistor P14 are both 0.5 μA. Since the current I15 flowing from the transistor P15 to the transistor N5 is 5 μA, the consumption current I of the entire drive circuit 101 is I = I13 + I23 + I14 + I24 + I15 = 11 μA (25)

As described above, according to the fourth embodiment of the present invention, while realizing the low current consumption which is the effect of the second embodiment, the conventional drive circuit does not operate. It is possible to configure an enhancement type drive circuit capable of normally driving a load connected to the output terminal even at the input voltage. Further, by the transistors P5, P6; N15, N16 provided as active loads,
The bias current can be controlled by the bias voltage supplied from the outside, and the drive capability of the transistors P4 and N14 can be controlled.

Further, a wide dynamic range can be obtained without using a special duplication type input transistor as the structure of the drive circuit, and when the drive circuit is manufactured, it is manufactured by an ordinary IC manufacturing process of a logic circuit. Even with a wide input dynamic range,
A high-performance, low-cost mixed digital / analog IC can be configured.

FIG. 10 is a circuit diagram of a drive circuit 111 according to the fifth embodiment of the present invention. In the drive circuit 111, the same components as those of the drive circuit 51 are designated by the same reference numerals and the description thereof will be omitted. The drive circuit 111 includes a differential amplifier circuit 112, a level conversion circuit 53, and an output buffer 5
4 is included. The level conversion circuit 53 and the output buffer 54 form an output circuit 113. Drive circuit 1
The eleventh feature is that two terminals 116 and 117 are prepared as input terminals to which the non-inverting input voltage VIA is applied.

The differential amplifier circuit 112 includes the differential amplifier circuit 52.
The configuration is similar to that of the first embodiment, and the same components are designated by the same reference numerals and the description thereof will be omitted. In the differential amplifier circuit 112,
A transistor N6 is provided in parallel with the transistor N1 which is one of the differential pairs. The gate of the transistor N1 is connected to the first non-inverting input voltage VIA1 via the terminal 116.
Is given to the gate of the transistor N6 at the terminal 11
A second non-inverting input voltage VIA2 is applied via 7.

An N-channel transistor N7 is interposed between the drain of the transistor N6 and the drain of the transistor P1 which is an active load, and an N-channel transistor N8 is interposed between the drain of the transistor N1 and the drain of the transistor P1. Is inserted. The input terminal 1 is connected to the gate of the transistor N8 which is the first switching element.
The first switching signal is supplied via 18 and the second switching signal is supplied to the gate of the transistor N7, which is the second switching element, via the input terminal 119. One of the transistors N7 and N8 is rendered conductive by the first and second switching signals. When the transistor N8 is turned on, the transistors N1 and N2 form a differential pair,
When the transistor N7 becomes conductive, the transistor N6
A differential pair is formed by N2.

The drive circuit 111 can be used in place of the drive circuit 31 in the prior art. The differential amplifier circuit 112 corresponds to the differential amplifier circuit 32, and the output circuit 113 corresponds to the output circuit 33. One end of the capacitor 35 is connected to the input terminal 116, and one end of the capacitor 34 is connected to the input terminal 117. The control signal S3 is applied to the input terminal 118 as the first switching signal, and the input terminal 1
A control signal S4 is given to 19 as a second switching signal. The drive circuit 111 outputs at the timing shown in FIG. 24, similarly to the drive circuit 31 described above.

FIG. 11 is a circuit diagram of a drive circuit 121 which is another structural example of the fifth embodiment described above. In the drive circuit 121, the same components as those of the drive circuit 68 described above are designated by the same reference numerals, and description thereof will be omitted. Drive circuit 1
21 includes a differential amplifier circuit 122, a level conversion circuit 70, and an output buffer 71. The level conversion circuit 70 and the output buffer 71 are the output circuit 123.
Is configured.

The differential amplifier circuit 122, like the differential amplifier circuit 112, is provided with two terminals to which the non-inverting input voltage VIA is input. The drive circuit 111 and the drive circuit 121 are similar to the relationship between the drive circuit 51 and the drive circuit 68 described above.
Means that the conductivity type of each transistor is replaced by P type and N type, and the ground potential and the power source potential are replaced. The P-channel transistors P16, P17, P18 and P19 in the differential amplifier circuit 122 are the transistors N in the differential amplifier circuit 112 in this order.
It corresponds to 6, N7, N8 and N9. The input terminals 116, 117, 118, 119 correspond to the input terminals 126, 127, 128, 129, respectively, in this order.

As described above, in the drive circuits 111 and 121 according to the fifth embodiment of the present invention, the drive circuit 5 described above is used.
Similar to No. 1 and No. 68, the amount of current consumed in the drive circuit in the equilibrium state can be reduced, and the transistors N1 and N6 are alternately conducted so that the capacitors 34 and 35 are sampled. The voltage can be output without being attenuated.
Further, since the drive circuits 111 and 121 are voltage follower circuits that give the voltage output from the output terminal 59 to the gate of the transistor N2 or P12, the operating state is almost in the equilibrium state. The current consumption of 111 and 121 can be effectively reduced.

FIG. 12 is a circuit diagram of a drive circuit 131 according to the sixth embodiment of the present invention. In the drive circuit 131, the same components as those of the drive circuit 51 and the drive circuit 111 described above are designated by the same reference numerals and the description thereof will be omitted.
The drive circuit 131 includes a differential amplifier circuit 132, a level conversion circuit 53, and an output buffer 54.

The driving circuit 131 is characterized in that the differential amplifier circuit 1
32 has a non-inverting input terminal 1 similar to the differential amplifier circuit 112.
16 and 117 are provided, and the differential amplifier circuit 7
7, the transistors P5 and P6 are provided in parallel with the transistors P1 and P2 as active loads for controlling the amount of current. Transistors P5 and
Since P6 is provided, the current supplied by the transistors P1 and P5 flows into the drains of the transistors N7 and N8, and the current supplied by the transistors P2 and P6 flows into the drain of the transistor N9.

The gates of the transistors P5 and P6 are
A predetermined constant voltage is applied via the second bias input terminal 133. The drive circuit 131 is the drive circuit 1
Similar to 11, the driving circuit 31 can be replaced and used.

FIG. 13 is a circuit diagram of a drive circuit 141 which is another configuration example of the sixth embodiment described above. In the drive circuit 141, the drive circuit 68 and the drive circuit 1 described above are used.
The same components as those of reference numeral 21 are designated by the same reference numerals, and description thereof will be omitted. The drive circuit 141 includes a differential amplifier circuit 142,
It is configured to include a level conversion circuit 70 and an output buffer 71. In the drive circuit 131 and the drive circuit 141, similarly to the relationship between the drive circuit 51 and the drive circuit 68, the conductivity type of each transistor is replaced by P type and N type, and the ground potential and the power source potential are replaced. It has a crossed structure.

Transistors N15 and N1 as active loads
Since 6 is provided in parallel with the transistors N11 and N12, the current supplied by the transistors N11 and N15 flows into the drains of the transistors P17 and P18, and the drain of the transistor P19 is supplied from the transistors N12 and N16. Current flows in. The gates of the transistors N15 and N16 have a first gate
A predetermined constant voltage is applied via the bias input terminal 143. The drive circuit 141 is the drive circuit 121.
It can be used in place of the drive circuit 31 in the same manner as.

As described above, in the drive circuits 131 and 141 according to the sixth embodiment of the present invention, the drive circuit 7 described above is used.
As with Nos. 6 and 81, it is possible to reduce the amount of current consumed in the drive circuit in the equilibrium state, and by conducting the transistors N1 and N6 alternately, for example, the capacitors 34 and 35 are sampled. The voltage can be output without being attenuated.
In the drive circuits 131 and 141, the output buffer 5 is controlled by controlling the bias voltage applied to the active load.
The driving capability of the transistors P4 and N14 of Nos. 4 and 71 can be defined, and the amount of current consumed by the drive circuits 131 and 141 can be controlled to further reduce the amount of current consumed. Further, the drive circuits 131 and 141 output the voltage output from the output terminal 59 to the transistor N2 or P.
Since the voltage follower circuit is provided to the 12 gates, the operating state is in a balanced state in almost all cases, and the current consumption of the drive circuits 131 and 141 can be effectively reduced.

FIG. 14 is a block diagram showing the configuration of drive circuit 151 and its periphery according to the seventh embodiment of the present invention, and FIG. 15 is a circuit diagram of drive circuit 151. The drive circuit 151 is used as a drive circuit for driving an active matrix type liquid crystal display panel, for example.
The circuit configuration shown in FIG. 14 can be replaced with the operational amplifier Op and the capacitor CH in the source driver shown in FIG. In the drive circuit 151, the same components as those of the above-mentioned drive circuits 51, 68, 111, 121 and components having the same function are designated by the same reference numerals and description thereof will be omitted.

The drive circuit 151 is the drive circuit 111 described above.
The input and output terminals of the drive circuit 121 and the drive circuit 121 are commonly connected, and the push-pull operation can be performed with a wide range of operable input voltage. The drive circuit 151 can operate over the entire power supply region where the input voltage is from the ground voltage GND to the power supply voltage VDD.

In the drive circuit 151, the output terminal 59 is connected in common, and the first non-inverting input terminals 116 and 126, the second non-inverting input terminals 117 and 127, the terminals 118 and 128, and the terminals 119 and 129 are commonly used. Connected to. The output terminal 59 is connected to the transistors N2 and P12.
Connected to. The drive circuit 151 operates as a voltage follower circuit by providing the output as an inverted input voltage.

In FIG. 14, capacitors 153, 15
4 holds the voltage of the analog signal Y, one terminal of each of the capacitors 153 and 154 is connected to the input signal line 157 via the analog switches 155 and 156, and the other terminals are both connected to the ground. There is.

In the drive circuit 111, the transistor N
Reference numerals 7 and N8 are transistors for controlling which of the non-inverting input voltages given to the gates of the transistors N1 and N6 from the input terminals 116 and 117 is selected. Transistors N7 and N8 have control signals S3 and S3.
4 is input to each gate, and the transistors N7 and N8 are alternately turned on at the respective voltage levels of the control signals S3 and S4, so that the transistor forming a differential pair with the transistor N2 is the transistors N1 and N6. Switch.
The transistor N9 is a transistor that is inserted because it is necessary to have a symmetrical circuit configuration due to the configuration of the current mirror circuit, and the voltage applied to the gate is the power supply voltage VDD that is a high level, and is always conductive. It is in a state.

The transistors P17, P18 and P19 in the drive circuit 121 are the same as the above-mentioned transistor N.
7, N8, and N9, which are transistors corresponding to each other, and their conduction / cutoff states are controlled by control signals S3B and S4B obtained by inverting control signals S3 and S4, respectively.

The drive circuit 151 shown in FIG.
As shown in the timing chart of FIG.
1 and the capacitor 153 at the timing synchronized with S2.
And 154 are subjected to data sampling, and the sampled voltage is alternately output from the two drive circuits 111 and 121 by the control signals S3 and S4.

The capacitor 153 is controlled by the control signal S3.
When the voltage held by is output, the voltage is sampled and held in the capacitor 154, and the control signal S4
When the capacitor 154 is outputting the voltage held by, the voltage of the capacitor 153 is sampled and held, so that the operations of data sampling and output are alternately repeated.

As described above, according to the seventh embodiment of the present invention, drive circuit 151 connects input terminals and output terminals of drive circuits 111 and 121 in the fifth embodiment described above in common. , The transistors P4 and N14 are made to perform push-pull operation, the above-mentioned drive circuits 111 and 1
21 can be obtained, and the operable input voltage range can be the entire power supply region from the ground voltage to the power supply voltage. Therefore, a wide input dynamic range can be obtained in the normal logic circuit IC manufacturing process without forming a special duplication type transistor, and a high-performance driving circuit for driving an active matrix type liquid crystal display panel is provided. Can be realized.

FIG. 16 is a circuit diagram of a drive circuit 171 according to the eighth embodiment of the present invention. The drive circuit 171 is
Similar to the drive circuit 151, it is used as a drive circuit for driving an active matrix type liquid crystal display panel, for example. In the drive circuit 171, the above-mentioned drive circuits 7
6,81,131,141,151 and the same components,
Also, constituent elements having the same function are designated by the same reference numerals, and description thereof will be omitted.

The drive circuit 171 connects the input and output terminals of the drive circuit 131 and the drive circuit 141, which are provided with the transistors P5, P6; The push-pull operation can be performed in a wider range. In the drive circuit 171, the input voltage can operate over the entire power supply region from the ground voltage GND to the power supply voltage VDD.

In the drive circuit 171, the output terminal 59 is commonly connected, and the first non-inverting input terminals 116 and 126, the second non-inverting input terminals 117 and 127, the terminals 118 and 128, and the terminals 119 and 129 are commonly used. Connected to. The first bias input terminal 172 is connected to the gates of the transistors N3, N15, N16, and the second bias input terminal 173 is connected to the transistors P5, P6, P.
It is connected to each gate of 13. The output terminal 59 is
It is connected to the transistors N2 and P12. The output is given as an inverting input voltage, so that the drive circuit 171
Operates as a voltage follower circuit.

As described above, according to the eighth embodiment of the present invention, drive circuit 171 connects input terminals and output terminals of drive circuits 131 and 141 in the sixth embodiment described above in common. Since the transistors P4 and N14 are made to perform push-pull operation, it is possible to realize an active matrix liquid crystal drive circuit using a sample and hold that can normally drive an output even at an input voltage that does not operate in a conventional circuit. You can Therefore, a wide input dynamic range can be obtained in the normal logic circuit IC manufacturing process without forming a special duplication type transistor, and a high-performance driving circuit for driving an active matrix type liquid crystal display panel is provided. Can be realized.

[0161]

According to the present invention, the current flowing through the output means is caused not only by the third field effect transistor driven by the differential amplifier means but also by the fourth field effect transistor driven by the current amount control means. Being controlled, the current flowing through the output means can be reduced when the voltage levels of the first and second input signals are in an equilibrium state where they are substantially equal. Further, when the difference between the first and second input signals is large, the amount of current flowing through the fourth field effect transistor increases, and the driving ability for the load connected to the driving circuit can be improved.

Further, according to the present invention, since the fifth and sixth field effect transistors, the sixth and seventh field effect transistors, and the eighth and fourth field effect transistors are current mirror circuits, the fourth field effect transistor. Is driven by the current supplied from the sixth field effect transistor to the second field effect transistor being given to the gate, and the current flowing through the output means is controlled not only by the third field effect transistor but also by the fourth field effect transistor. It is possible to reduce the current flowing through the output means in the equilibrium state. Further, when the difference between the first and second input signals is large, the amount of current flowing through the fourth field effect transistor increases, and the driving ability for the load connected to the driving circuit can be improved.

Further in accordance with the present invention, the ninth and tenth aspects
By controlling the potential applied to the gate of the field effect transistor, the amount of current given to the gate of the fourth field effect transistor is controlled, so that the amount of current flowing through the output means can be reduced, for example. Also, the first
When the difference between the second input signal and the second input signal is large, the amount of current flowing through the fourth field effect transistor is large, and the driving capability for the load connected to the driving circuit can be improved.

Furthermore, according to the present invention, the output of the output means is given to the gate of the second field effect transistor as the second input signal to form the voltage follower circuit.
As long as the voltage levels of the signals given to the first and second field-effect transistors have the same potential and the first and second input signals given to the first and second field-effect transistors do not change abruptly, the drive circuit Will operate in a balanced state, and the current flowing through the output means, that is, the current consumed in the drive circuit can be reduced.

According to the present invention, no matter what the voltage level of the first and second input signals is from the ground potential to the power supply potential, the power supply potential to the output terminal and the output terminal to the ground. Since there is at least one path through which a current flows from the power supply potential up to the potential to the ground potential, the drive circuit can be operated regardless of the voltage levels of the first and second input signals. In the first and second drive circuits, not only the third field effect transistor driven by the differential amplification means but also the fourth field effect transistor driven by the current amount control means controls the amount of current flowing through the output means. Controlled, so the first
And when the voltage levels of the second input signal are substantially equal, the current flowing through the output means can be reduced. Further, when the difference between the first and second input signals is large, the amount of current flowing through the fourth field effect transistor increases, and the driving ability for the load connected to the driving circuit can be improved.

Further, according to the present invention, the fourth field effect transistor of the first differential amplifying means is driven by supplying the current supplied from the tenth field effect transistor to the second field effect transistor to the gate, The eighth field effect transistor of the second differential amplifying means is driven by the gate supplied with the current supplied from the fourteenth field effect transistor to the second field effect transistor, so that the current flowing through the first output means is , Not only the third field effect transistor but also the fourth
It is also controlled by the field effect transistor, and the current flowing through the second output means is controlled not only by the seventh field effect transistor but also by the eighth field effect transistor, and the voltage of the first and second input signals is controlled. When in the equilibrium state where the levels are almost equal, the currents flowing through the first and second output means can be reduced respectively. Further, when the difference between the first and second input signals is large, the amount of current flowing through the fourth and eighth field effect transistors is large, and the driving ability for the load connected to the driving circuit can be improved.

Further according to the present invention, the fourth field effect transistor of the first output means is controlled by the amount of current supplied from the tenth and eighteenth field effect transistors to the second field effect transistor, and the second output means. Since the eighth field effect transistor is controlled by the amount of current supplied to the sixth field effect transistor from the fourteenth and twentieth field effect transistors, the gates of the seventeenth and eighteenth field effect transistors and the nineteenth and twentieth field effect transistors are controlled. By controlling the potential applied to the gate electrodes, the amount of current supplied to the gates of the fourth and eighth field effect transistors is controlled, and for example, the amount of current flowing through the first and second output means can be reduced.

Further, according to the present invention, since the output of the drive circuit is given to the respective gates of the second and sixth field effect transistors to form a voltage follower circuit, the first and second field effect transistors of the first drive circuit are provided. The voltage level of the signal applied to the second drive circuit has the same potential, and the voltage level of the signal applied to the fifth and sixth field effect transistors of the second drive circuit has the same potential.
As long as the input signal does not change abruptly, each drive circuit operates in a balanced state, and the current flowing through the output means, that is, the current consumed by the drive circuit can be reduced.

According to the present invention, in the differential amplification means of the drive circuit, the combination of the field effect transistors forming the differential pair is changed by controlling the conduction / interruption of the first and second switching means. The fourth field effect transistor is driven by the first and second input signals or the second and third input signals. The output means includes a fifth field effect transistor driven by the current amount control means, and controls the current flowing between the drain of the fourth field effect transistor and the first potential, so that the first and second field effect transistors are controlled.
By controlling conduction / interruption of the switching element, the first and third input signals are switched to perform a differential amplification operation, and the voltage levels of the first and second input signals or the second and third input signals are The current flowing through the output means can be reduced when the equilibrium states are almost equal. Further, when the difference between the voltage levels of the first and second input signals or the second and third input signals is large, the amount of current flowing through the fourth field effect transistor is large, and the drive capability for the load connected to the drive circuit is increased. Can be improved.

Further, according to the present invention, the sixth and seventh field effect transistors, the seventh and eighth field effect transistors, and the ninth and fifth field effect transistors are current mirror circuits, and the fifth field effect transistor is used. Since the gate of the transistor is driven by the current supplied to the second field effect transistor, the current flowing through the output means can be controlled not only by the fourth field effect transistor but also by the fifth field effect transistor. The current flowing through the output means in the equilibrium state can be reduced. In addition, when the difference between the voltage levels of the first and second input signals or the second and third input signals is large, the amount of current flowing through the fifth field effect transistor is large and the driving ability for the load connected to the driving circuit is improved. Can be made.

Further in accordance with the present invention, the ninth and tenth aspects
By controlling the potential applied to the gate of the field effect transistor, the amount of current given to the gate of the fourth field effect transistor is controlled, so that the amount of current flowing through the output means in the equilibrium state can be reduced. Further, when the difference between the voltage levels of the first and second input signals or the second and third input signals is large, the amount of current flowing through the fourth field effect transistor is large, and the drive capability for the load connected to the drive circuit is increased. Can be improved.

Furthermore, according to the present invention, the output of the output means is given to the gate of the second field effect transistor as the second input signal to form the voltage follower circuit.
And the voltage levels of the signals applied to the second field effect transistors become the same potential, and the voltage levels of the first and second input signals or the second and third input signals applied to the first and second field effect transistors suddenly increase. As long as there is no change, the drive circuit operates in a balanced state, and the current flowing through the output means, that is, the current consumed by the drive circuit can be reduced.

According to the present invention, the first drive circuit and the second drive circuit are commonly supplied with the first, second and third input signals,
Since the drains of the field effect transistors of the first and second output means are connected to each other and the potential at the connection point is output,
Regardless of the voltage level of the first and second input signals or the second and third input signals from the ground potential to the power supply potential, from the power supply potential to the output terminal and from the output terminal to the ground potential Since there is at least one path through which a current flows from the power supply potential to the ground potential, no matter what the voltage level of the first and second input signals or the second and third input signals is, The driving circuit can be operated.

According to the invention, in the first differential amplifying means, the eleventh and twelfth field effect transistors and the twelfth field effect transistor are provided.
Since the thirteenth and thirteenth field effect transistors, and the thirteenth and fifth field effect transistors form a current mirror circuit, the fifth field effect transistor has a current supplied from the twelfth field effect transistor to the second field effect transistor. The second differential amplifying means is driven by being applied to the gate, and the fifteenth and sixteenth field effect transistors, the sixteenth and seventeenth field effect transistors, and the seventeenth and tenth field effect transistors serve as a current mirror circuit. Since the tenth field effect transistor is driven by the gate supplied with the current supplied from the sixteenth field effect transistor to the seventh field effect transistor, the current flowing through the first output means changes to the fourth field effect transistor. Controlled by not only the transistor but also the fifth field effect transistor And the current flowing through the second output means is controlled not only by the ninth field effect transistor but also by the tenth field effect transistor, and the first and second input signals or the second and third input signals are controlled. The currents flowing through the first and second output means can be reduced respectively when the voltage levels are in a state of equilibrium. Further, when the difference between the voltage levels of the first and second input signals or the second and third input signals is large, the amount of current flowing through the fifth and tenth field effect transistors is large, and the load connected to the drive circuit is driven. You can improve your ability.

Further, according to the present invention, the fifth field effect transistor of the first output means is controlled by the amount of current supplied from the nineteenth and twentieth field effect transistors to the second field effect transistor, and the second output means. Since the tenth field effect transistor of is controlled by the amount of current supplied to the seventh field effect transistor from the 21st and 22nd field effect transistors, the gates of the 19th and 20th and 21st and 22nd field effect transistors are By controlling the potential applied to the first and second field effect transistors, the amount of current supplied to the gates of the fifth and tenth field effect transistors can be controlled, and the amount of current flowing through the first and second output means can be reduced.

Further, according to the present invention, since the output of the drive circuit is given to the respective gates of the second and sixth field effect transistors to form a voltage follower circuit, the first and second field effect transistors of the first drive circuit are provided. And the voltage levels of the signals applied to the pair of one of the third and second field effect transistors have the same potential, and the sixth and seventh field effect transistors of the second drive circuit and the eighth and seventh field effect transistors. Unless the voltage level of the signal given to either one of the pair of effect transistors becomes the same potential, and the voltage level of the first and second input signals or the second and third input signals does not change abruptly. The drive circuit operates in a balanced state, and the current flowing through the output means, that is, the current consumed by the drive circuit It is possible to reduce the current.

[Brief description of drawings]

FIG. 1 is a drive circuit 51 according to a first embodiment of the present invention.
FIG.

FIG. 2 is a block diagram showing a configuration of a liquid crystal display device 60.

FIG. 3 is a block diagram showing a configuration of a source driver 61.

FIG. 4 is a circuit diagram of a drive circuit 68 that is another configuration example of the first embodiment of the present invention.

FIG. 5 is a drive circuit 76 according to a second embodiment of the present invention.
FIG.

FIG. 6 is a circuit diagram of a drive circuit 81 which is another configuration example of the second embodiment of the invention.

FIG. 7 is a drive circuit 91 according to a third embodiment of the present invention.
FIG.

FIG. 8 is a diagram for explaining the operation of the drive circuit 91.

FIG. 9 is a drive circuit 10 according to a fourth embodiment of the present invention.
1 is a circuit diagram of FIG.

FIG. 10 is a drive circuit 1 according to a fifth embodiment of the present invention.
11 is a circuit diagram of FIG.

FIG. 11 is a circuit diagram of a drive circuit 121 that is another configuration example of the fifth embodiment of the present invention.

FIG. 12 is a drive circuit 1 according to a sixth embodiment of the present invention.
It is a circuit diagram of 31.

FIG. 13 is a circuit diagram of a drive circuit 141 which is another configuration example of the sixth embodiment of the present invention.

FIG. 14 is a drive circuit 1 according to a seventh embodiment of the present invention.
It is a block diagram which shows the structure of 51 and its periphery.

FIG. 15 is a circuit diagram of a drive circuit 151.

FIG. 16 is a drive circuit 1 according to an eighth embodiment of the present invention.
It is a circuit diagram of 71.

FIG. 17 is a circuit diagram of a drive circuit 1 which is a first prior art.

FIG. 18 is a circuit diagram of a drive circuit 11 that is second prior art.

FIG. 19 is a circuit diagram of a drive circuit 16 that is third prior art.

FIG. 20 is a circuit diagram of a drive circuit 21 that is fourth prior art.

FIG. 21 is a diagram for explaining the operation of the drive circuit 21.

FIG. 22 is a block diagram showing a configuration of a drive circuit 31 and its periphery according to a fifth prior art.

FIG. 23 is a circuit diagram of a differential amplifier circuit 32 included in a drive circuit 31.

FIG. 24 is a timing chart showing the operation of the drive circuit 31.

[Explanation of symbols]

51, 68, 76, 81, 91, 101, 111, 12
1, 131, 141, 151, 171 Drive circuit 52, 69, 77, 82, 112, 122, 132, 1
42 differential amplifier circuit 53, 70 level conversion circuit 54, 71 output buffer 56, 92 inverting input terminal 57, 93 non-inverting input terminal 58, 94, 143 first bias input terminal 59, 96 output terminal 72, 78, 95, 133 second bias input terminal 116,126 first inverting input terminal 117,119,127,129 terminal 118,128 second inverting input terminal P1, P2, P3, P4 P-channel transistor N1, N2, N3, N4, N5 N Channel transistor

Claims (16)

[Claims] 1. A one-channel first field effect transistor having a gate supplied with a first input signal, and a one-channel second field effect transistor supplied with a second input signal to a gate. Is a differential pair, each source is given a predetermined first potential, and an active load for supplying a current to each transistor is interposed between each drain and a predetermined second potential. The amplifying means, the drain potential of the first field effect transistor is applied to the gate, the second potential is applied to the source of the other channel type third field effect transistor, and the first potential is applied to the source. , A drain connected to the drain of the third field effect transistor and a channel type fourth field effect transistor, and outputs the potential of the commonly connected drains. And a current amount control unit for driving the fourth field effect transistor of the output unit based on the amount of current supplied by the active load to the second field effect transistor. . 2. The active load is configured to include fifth and sixth field effect transistors of the other channel type in which respective gates are commonly connected and each source is supplied with the second potential. The drain of the field effect transistor is connected to the drain of the first field effect transistor, the drain of the sixth field effect transistor is connected to the drain of the second field effect transistor and each of the commonly connected gates, The quantity control means forms a current mirror circuit by connecting the gate to the gate and drain of the sixth field effect transistor, and the other channel type seventh field effect transistor in which the second potential is applied to the source. And a gate of the fourth field effect transistor is connected to a gate and a drain of the fourth field effect transistor. A drain circuit of the seventh field effect transistor is connected to the drain, and the source includes the channel-type eighth field effect transistor to which the first potential is applied. The drive circuit according to claim 1. 3. The active channel loads are provided in parallel with the fifth and sixth field effect transistors, respectively, and a predetermined potential is applied to each gate to bring the other into conduction. The driving circuit according to claim 2, further comprising a tenth field effect transistor. 4. The voltage follower circuit according to claim 1, wherein the output of the output means is applied to the gate of the second field effect transistor as the second input signal.
The drive circuit according to any one of 3 to 3. 5. A drive circuit comprising a first drive circuit and a second drive circuit, wherein the first drive circuit is an N-channel type first circuit whose gate is supplied with a first input signal. A field-effect transistor and an N-channel type second field-effect transistor whose gate is supplied with a second input signal are used as a differential pair, each source is given a ground potential, and each drain and a predetermined power supply. A first differential amplification means in which a first active load for supplying a current to each transistor is interposed between the potential and a potential, the potential of the drain of the first field effect transistor is given to the gate, and the power source potential is the source. A P-channel type third field-effect transistor given to the source, and a fourth N-channel type field-effect transistor whose source is given the ground potential and whose drain is connected to the drain of the third field-effect transistor.
First field-effect transistor including a first field-effect transistor and a first field-effect transistor driving the fourth field-effect transistor of the first output means based on an amount of current supplied to the second field-effect transistor by the first active load. A second drive circuit including a current amount control means; a P-channel type fifth field effect transistor having a gate supplied with the first input signal; and a gate having the gate supplied with the second input signal. A channel type sixth field effect transistor is used as a differential pair, the power supply potential is applied to each source, and a second active load that supplies current to each transistor between each drain and the ground potential. And the N-channel seventh electric field effect in which the potential of the drain of the fifth field effect transistor is applied to the gate and the ground potential is applied to the source. A P-channel type eighth transistor in which the power supply potential is applied to the transistor and the source, and the drain is connected to the drain of the seventh field effect transistor.
Second field-effect transistor including the second field-effect transistor and a second field-effect transistor driving the eighth field-effect transistor of the second field-effect transistor based on the amount of current supplied to the sixth field-effect transistor by the second active load. A drive circuit comprising: a current amount control means, wherein the drains of the field effect transistors of the first and second output means are connected to each other to output the potential at the connection point. 6. The first active load is configured to include ninth and tenth P-channel type field effect transistors having respective gates connected in common and having respective sources supplied with the power supply potential. A drain of the ninth field effect transistor is connected to a drain of the first field effect transistor, a drain of the tenth field effect transistor is connected to a drain of the second field effect transistor and the commonly connected gates, The first current amount control means forms a current mirror circuit by connecting the gate to the gate and drain of the tenth field effect transistor, and an eleventh P-channel type electric field to which the power supply potential is applied to the source. The effect transistor and the gate of the fourth field effect transistor are connected to the gate and the drain. A current mirror circuit, the drain of the eleventh field effect transistor is connected to the drain, and the source includes an N-channel type twelfth field effect transistor to which the ground potential is applied. The second active load is configured to include N-channel type thirteenth and fourteenth field effect transistors having respective gates connected in common and having the sources supplied with the ground potential. The drain is connected to the drain of the fifth field effect transistor, the drain of the fourteenth field effect transistor is connected to the drain of the sixth field effect transistor and each of the commonly connected gates, and the second current amount control The means is characterized in that the gate is connected to the gate and drain of the fourteenth field effect transistor. A fifteenth N-channel type field effect transistor which constitutes a current mirror circuit and whose source is given the ground potential, and a gate of the eighth field effect transistor, the gate of which is connected to the drain of the current mirror circuit. The drain of the fifteenth field effect transistor is connected to the drain and the gate, and the source includes a P-channel type sixteenth field effect transistor to which the power supply potential is applied. The drive circuit according to claim 5, wherein the drive circuit is a drive circuit. 7. The first active load is provided in parallel with each of the ninth and tenth field effect transistors, and is a P-channel type first gate which is in a conductive state by applying a predetermined potential to each gate. The second active load is provided in parallel with the thirteenth and fourteenth field effect transistors, respectively, and a predetermined potential is applied to each gate to be in a conductive state. 7. The drive circuit according to claim 6, further comprising N-channel type nineteenth and twentieth field effect transistors. 8. The voltage follower circuit according to claim 5, wherein the potential of the connection point is applied to the gates of the second and sixth field effect transistors as the second input signal to form a voltage follower circuit. The drive circuit according to one. 9. A one-channel type first field-effect transistor whose gate is supplied with a first input signal, and a one-channel second field-effect transistor whose gate is supplied with a second input signal. , A channel-type third field-effect transistor whose gate is supplied with a third input signal, each source being provided with a predetermined first potential, and each drain being supplied with a predetermined second potential. An active load for supplying a current to each transistor is interposed between the first field effect transistor and the active load, and a first switching element is interposed between the first field effect transistor and the active load. A second switching element is interposed between the load and the first and second switching elements so that the first and second switching elements are electrically connected.
Differential amplifying means for switching between a differential pair of transistors or a differential pair of second and third transistors; and a drain of one of the first and third field effect transistors. The other channel type fourth field effect transistor in which a potential is applied to the gate and the second potential is applied to the source, and the first potential is applied to the source and the drain is connected to the drain of the fourth field effect transistor On the other hand, based on the amount of current supplied to the second field effect transistor by the active load, the output means including a channel-type fifth field effect transistor and outputting the potential of the commonly connected drains. And a current amount control means for driving the fifth field effect transistor of the means. 10. The active load includes sixth and seventh field-effect transistors of the other channel type, the gates of which are connected in common and the sources of which are supplied with the second potential. The drain of the field effect transistor is commonly connected to the first and second switching elements, the drain of the seventh field effect transistor is connected to the drain of the second field effect transistor and each of the commonly connected gates, The current amount control means forms a current mirror circuit by connecting the gate to the gate and drain of the seventh field effect transistor, and the other channel type eighth electric field in which the second potential is applied to the source. The effect transistor and the gate of the fifth field effect transistor are connected to the gate and the drain of the effect transistor. And a drain of the eighth field effect transistor is connected to the drain, and a source includes the channel-type ninth field effect transistor to which the first potential is applied. The drive circuit according to claim 9. 11. The active channel load is provided in parallel with each of the sixth and seventh field effect transistors, and the other channel type tenth and tenth transistors are in a conductive state by applying a predetermined potential to each gate. 11. The drive circuit according to claim 10, further comprising an eleventh field effect transistor. 12. The output potential of the output means is set to the second potential.
The drive circuit according to claim 9, wherein a voltage follower circuit is provided as an input signal to the gate of the second field effect transistor. 13. A drive circuit comprising a first drive circuit and a second drive circuit, wherein the first drive circuit is a first N-channel type whose gate is supplied with a first input signal. A field-effect transistor, an N-channel second field-effect transistor whose gate is supplied with a second input signal, and an N-channel third field-effect transistor whose gate is supplied with a third input signal. A predetermined ground potential is applied to each source, a first active load for supplying a current to each transistor is interposed between each drain and a predetermined power supply potential, and the first field effect transistor and A first switching element is interposed between the first active load and a second switching element is interposed between the third field effect transistor and the first active load. Sui A first differential amplifying means for switching between forming a differential pair with the first and second transistors and forming a differential pair with the second and third transistors by conducting either one of the teaching elements; A P-channel type fourth field effect transistor in which the potential of the drain of any one of the first and third field effect transistors is applied to the gate and the power supply potential is applied to the source, and the source is connected to the ground. First output means including an N-channel type fifth field effect transistor having a potential applied thereto and having a drain connected to the drain of the fourth field effect transistor; and the first active load having the second field effect transistor. A first current amount control means for driving the fifth field effect transistor of the first output means based on the amount of current supplied to the second drive circuit. The path includes a P-channel type sixth field effect transistor whose gate is supplied with the first input signal, a P-channel type seventh field effect transistor whose gate is supplied with the second input signal, and a gate. And a P-channel type eighth field effect transistor to which the third input signal is supplied, each source is provided with the power supply potential, and each transistor is provided between each drain and the ground potential. A second active load supplying a current is interposed, a third switching element is interposed between the sixth field effect transistor and the second active load, and the eighth field effect transistor and the second active load are connected. A fourth switching element is interposed between
A second switch that switches between configuring a differential pair with the sixth and seventh transistors or configuring a differential pair with the seventh and eighth transistors by conducting one of the third and fourth switching elements. Differential amplifying means, and an N-channel type ninth field effect transistor in which the drain potential of any one of the sixth and eighth field effect transistors is applied to the gate and the ground potential is applied to the source. , A second output means including a source to which the power supply potential is applied and a drain connected to a drain of the ninth field effect transistor, and a second output means including the P-channel type tenth field effect transistor. A second current amount control means for driving the tenth field effect transistor of the second output means based on the amount of current supplied to the seventh field effect transistor. Wherein the door, the first and drain were connected to each other in each of the field effect transistors of the second output means, driving circuits and outputs the potential of the connection point. 14. The first active load is configured to include eleventh and twelfth P-channel type field effect transistors having respective gates connected in common and having respective sources to which the power supply potential is applied. The drain of the eleventh field effect transistor is commonly connected to the first and second switching elements, and the drain of the twelfth field effect transistor is connected to the drain of the second field effect transistor and each of the commonly connected gates. The first current amount control means forms a current mirror circuit by connecting a gate to a gate and a drain of the twelfth field effect transistor, and a P-channel type thirteenth source to which the power supply potential is applied. And the gate of the fifth field effect transistor is connected to the gate and the drain. A current mirror circuit is constituted by and the drain of the thirteenth field effect transistor is connected to the drain, and the source includes an N-channel type fourteenth field effect transistor to which the ground potential is applied. The second active load is configured to include N-channel type fifteenth and sixteenth field effect transistors having respective gates connected in common and each source being supplied with the ground potential, and the drain of the fifteenth field effect transistor. Is commonly connected to the third and fourth switching elements, the drain of the sixteenth field effect transistor is connected to the drain of the seventh field effect transistor, and the second current amount control means is the sixteenth field effect transistor. A current mirror circuit is constructed by connecting the gate to the gate and the drain of An N-channel type seventeenth field effect transistor whose source is given the ground potential, and a gate of the tenth field effect transistor connected to a gate and a drain to form a current mirror circuit, 14. The driving circuit according to claim 13, wherein the drain of the seventeenth field effect transistor is connected to the drain, and the source includes a P-channel type eighteenth field effect transistor to which the power supply potential is applied. . 15. The first active load is provided in parallel with each of the eleventh and twelfth field effect transistors, and is a P-channel type first transistor which is in a conductive state by applying a predetermined potential to each gate. The second active load is provided in parallel with the fifteenth and sixteenth field effect transistors, respectively, and a predetermined potential is applied to each gate so that the second active load becomes conductive. 15. The drive circuit according to claim 14, further comprising N-channel type 21st and 22nd field effect transistors. 16. The voltage follower circuit by applying the potential of the connection point to the gates of the second and seventh field effect transistors as the second input signal to form a voltage follower circuit. The drive circuit according to one.