JP2000339985A - Shift register and image display device using the same - Google Patents

Abstract

(57) [Problem] To realize a shift register which operates normally and consumes less power even when the amplitude of a clock signal is small. A level shifter for boosting a clock signal is provided for each of the SR flip-flops constituting a shift register. As a result, the transmission distance of the boosted clock signal can be reduced and the load capacity of the level shifter 13 can be reduced as compared with the case where the clock signal is boosted by only one level shifter and then transmitted to each flip-flop. Furthermore, each level shifter 13 operates while the preceding level shifter 13 outputs a pulse, and stops operating when the pulse output ends. Therefore, it is necessary to supply the clock signal CK to the corresponding SR flip-flop F1. Can only work if. As a result, even when the amplitude of the clock signal is small, the power consumption of the shift register that operates normally can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in, for example, a driving circuit of an image display device, and is capable of shifting an input pulse even when the amplitude of a clock signal is lower than a driving voltage. The present invention relates to an image display device using the same.

[0002]

2. Description of the Related Art For example, in a data signal line driving circuit and a scanning signal line driving circuit of an image display device, timing for sampling each data signal from a video signal is taken.
Shift registers are widely used to create scan signals to be applied to each scan signal line.

On the other hand, the power consumption of an electronic circuit depends on the frequency,
It increases in proportion to the load capacity and the square of the voltage. Therefore, for example, a circuit connected to the image display device, such as a circuit that generates a video signal to the image display device, or
In an image display device, a drive voltage tends to be set lower in order to reduce power consumption.

For example, a pixel, a data signal line driving circuit,
Alternatively, in a circuit in which a polycrystalline silicon thin film transistor is used to secure a large display area, such as a scanning signal line driving circuit, a difference in threshold voltage between substrates or within the same substrate is, for example, several [ V], it is difficult to say that the drive voltage has been sufficiently reduced. However, for example, in a circuit using a single crystal silicon transistor, such as the above-described video signal generation circuit, the drive voltage has been reduced. Is often set to, for example, 5 [V], 3.3 [V], or a value lower than that. Therefore, when a clock signal lower than the drive voltage of the shift register is applied, the shift register is provided with a level shifter that boosts the clock signal.

More specifically, for example, as shown in FIG.
When a clock signal CK having an amplitude of about [V] is given,
The level shifter 103 boosts the clock signal CK up to the driving voltage (15 [V]) of the shift register 101.
The boosted clock signal CK is supplied to each flip-flop F1.
To Fn, and the shift register unit 102 shifts the start signal SP in synchronization with the clock signal CK.

[0006]

However, in the conventional shift register 101, the clock signal CK is level-shifted and then transmitted to the flip-flops F1 to Fn. The longer the distance is, the longer the transmission distance becomes, and the more power consumption increases.

More specifically, as the transmission distance increases, the capacity of the signal line for transmission increases, so that the level shifter 103 needs to have a larger driving capability and the power consumption increases. Further, when the driving capability of the level shifter 103 is not sufficient, as in the case where the driving circuit including the level shifter 103 is formed using a polycrystalline silicon thin film transistor, a waveform without distortion is transmitted. , The level shifter 103
And a buffer 104 between each flip-flop F1 to Fn.
Needs to be provided, so that more power consumption is required.

In recent years, a demand has arisen for an image display device having a wider display screen and a higher resolution, and the number of stages of the shift register section 102 tends to increase more and more. Therefore, there is a strong demand for a shift register and an image display device that consume less power even when the distance between both ends of the flip-flops F1 to Fn increases.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a shift register which operates normally even when the amplitude of a clock signal is lower than a drive voltage and consumes less power. Another object is to realize an image display device using the same.

[0010]

In order to solve the above-mentioned problems, a shift register according to the present invention includes a plurality of flip-flops operating in synchronization with a clock signal and an amplitude larger than a driving voltage of the flip-flop. A shift register having a level shifter for boosting a small clock signal and applying the boosted clock signal to each of the flip-flops, and transmitting an input pulse in synchronization with the clock signal, is characterized by the following means.

That is, each of the flip-flops is divided into a plurality of blocks each including at least one flip-flop, and the level shifter is provided for each of the blocks. At least one of the level shifters corresponding to the blocks that do not require the input of the clock signal to transmit the input pulse is stopped.

Whether each block requires a clock signal to transmit an input pulse is determined by a flip-flop constituting a shift register. For example,
When a set / reset flip-flop that is set in response to a clock signal is used as the flip-flop, the block is connected between the time when a pulse is input to the block and the time when the last-stage flip-flop is set. When the flip-flop is a D flip-flop, the clock signal is required from the time when the pulse is input to the block to the time when the last flip-flop finishes the pulse output.
In either case, each block includes one flip-flop, and a level shifter may be provided for each flip-flop, or a level shifter may be provided for each of a plurality of flip-flops. Good.

In the above configuration, the clock signal is boosted by one of the plurality of level shifters and then applied to the flip-flop in the block corresponding to the level shifter, and the input pulse is synchronized with the boosted clock signal. , Are sequentially transmitted. In addition, of each level shifter,
At least one of the level shifters that does not need to output the clock signal stops operating.

Here, a block that does not require a clock signal is, for example, a block that does not transmit an input pulse. Even in a block transmitting an input pulse, for example, a flip-flop is set according to a clock signal, and is reset according to an output of a flip-flop at a later stage.
In the case of a flip-flop, no clock signal is required during the period after the last-stage flip-flop is set.

In the above configuration, since a plurality of level shifters are provided in the shift register, the distance from the level shifter to the flip-flop is smaller than when only one level shifter applies the clock signal after the level shift to all flip-flops. Can be shortened. As a result, the transmission distance of the clock signal after the level shift can be shortened, so that the load capacity of the level shifter can be reduced and the driving capability required for the level shifter can be suppressed. Accordingly, for example, even when the driving capability of the level shifter is small and the distance between both ends of the flip-flop is long, it is not necessary to provide a buffer between the level shifter and the flip-flop, and the power consumption of the shift register is reduced. Can be reduced. In addition, since at least one of the plurality of level shifters stops operating, power consumption of the shift register can be reduced as compared with a case where all the level shifters operate simultaneously. As a result, a shift register which can operate with a low-voltage clock signal input and consumes low power can be realized.

Further, the present invention can be applied not only to a case where a set / reset flip-flop is included as a flip-flop, but also to a case where a specific block among the blocks includes a D flip-flop as the flip-flop. In this case, the specific level shifter corresponding to the specific block starts operating when a pulse input to the specific block is started, and starts operating after the last-stage flip-flop of the specific block finishes pulse output. It is preferable to stop.

According to this configuration, since the specific block includes the D flip-flop as the flip-flop, the pulse width (number of clocks) of the input pulse changes unlike the case of the set / reset flip-flop. Even in this case, the input pulse can be transmitted without any trouble. Further, according to the above configuration, the specific level shifter
During a period required when the D flip-flop of the specific block operates, the clock signal after the level shift is supplied,
When the input of the clock signal to the flip-flop is unnecessary, the operation is stopped. As a result, a shift register that can transmit input pulses having different pulse widths and consumes less power can be realized.

In addition, the period from when a pulse is input to a specific block to when the last flip-flop outputs a pulse is, for example, a pulse signal input to the specific block, an output signal of the flip-flop of each stage, and , Or by latching a signal serving as a trigger. Therefore, in this case, the circuit configuration of the shift register can be more simplified than when the operation period is calculated separately from the input / output of the flip-flop.

Further, in the shift register having the above-mentioned configuration, when there are a plurality of the flip-flops in the specific block, the specific level shifter is configured to control a signal input to the specific block and a flip-flop of a last stage of the specific block. A latch circuit that changes the output according to the output signal may be included.

Further, in the shift register having the above-mentioned configuration, the level shifter may include a current-driven level shift section in which an input switching element for applying the clock signal is always conductive during operation.

According to this configuration, while the level shifter is operating, the input switching element of the level shifter is always conductive. Therefore, unlike a voltage-driven level shifter that conducts / cuts off the input switching element according to the level of the clock signal, no problem occurs even when the amplitude of the clock signal is lower than the threshold voltage of the input switching element. The clock signal can be level shifted.

Furthermore, the current-driven level shifter consumes more power than the voltage-driven level shifter during operation because the input switching element is conducting, but at least one of the plurality of level shifters stops operating. are doing. This makes it possible to realize a shift register that can perform level shift even when the amplitude of the clock signal is lower than the threshold voltage of the input switching element, and consumes less power than when all the level shifters operate simultaneously.

Further, in the shift register having the above configuration, an input signal control section for stopping the level shifter by providing a signal of a level cut off by the input switching element as an input signal to the level shift section. You may.

According to the above configuration, as an example, the case where the input switching element is a MOS transistor will be described. For example, when an input signal is applied to the gate, the level at which the drain-source is cut off is set. When an input signal is applied to the gate, the input switching element is shut off. Also, when the input signal is applied to the source,
For example, the input switching element is cut off by applying substantially the same input signal as that of the drain.

In any configuration, if the input signal control section controls the level of the input signal and cuts off the input switching element, the current-driven level shifter stops operating. Thus, the input signal control unit can stop the level shifter, and can reduce power consumption by the amount of current flowing to the input switching element during operation during the stop.

On the other hand, the shift register of each of the above configurations may include a power supply control unit that stops power supply to the level shift unit and stops the level shifter.

According to this configuration, the power supply control unit stops the power supply to each level shift unit and stops the level shifter. Accordingly, the power supply control unit can stop the level shifter, and can reduce power consumption by the amount of power consumed by the level shifter during operation while the operation is stopped.

By the way, if the output voltage of the level shifter becomes unstable while the operation of the level shifter is stopped, the operation of the flip-flop connected to the level shifter may be unstable.

Therefore, in the shift register of each configuration described above, it is preferable that the level shifter includes an output stabilizing means for maintaining the output voltage at a predetermined value when stopped.

According to this configuration, while the level shifter is stopped, the output voltage of the level shifter is maintained at a predetermined value by the output stabilizing means. As a result, it is possible to prevent a malfunction of the flip-flop due to the undefined output voltage,
A more stable shift register can be realized.

Further, a clock signal line for transmitting the clock signal is provided in the shift register of each configuration,
It is preferable that a switch provided between the level shift unit and open while the level shifter is stopped is provided. The switch can be realized as a part of the input signal control unit.

In the above configuration, unlike the case where all the level shifters are always connected to the clock signal line and the input switching elements of all the level shift units load the clock signal line, the input switching elements connected to the clock signal line are different. Are limited to those of the operating level shifter. In addition, even when the switch is opened during stop and the input of the level shifter becomes unstable, the output of the level shifter is maintained at a predetermined value by the output stabilizing means, so that the flip-flop does not malfunction. As a result, the load capacity of the clock signal line can be reduced, and the power consumption of a circuit for driving the clock signal line can be reduced.

On the other hand, in order to solve the above-mentioned problems, an image display device according to the present invention comprises a plurality of pixels arranged in a matrix, a plurality of data signal lines arranged in each row of the pixels, and A plurality of scanning signal lines arranged in each column of each pixel, and a scanning signal line drive for sequentially providing scanning signals at mutually different timings to the scanning signal lines in synchronization with a first clock signal having a predetermined period. Circuit, and sequentially from a video signal indicating the display state of each pixel in synchronization with a second clock signal having a predetermined cycle, and from the video signal to each pixel of the scanning signal line to which the scanning signal is applied. A data signal line driving circuit for extracting a data signal and outputting the data signal to each of the data signal lines, wherein at least one of the data signal line driving circuit and the scanning signal line driving circuit includes Alternatively and the second clock signal characterized in that it comprises a shift register of any of the above-described configuration according to the clock signal.

Here, in the image display device, as the number of data signal lines or the number of scanning signal lines increases, the number of flip-flops for generating timing for each signal line increases, and the number of flip-flops increases. The distance between both ends becomes longer. However, the shift register of each configuration described above can reduce the number of buffers and power consumption even when the driving capability of the level shifter is small and the distance between both ends of the flip-flop is long.

Therefore, by providing at least one of the data signal line driving circuit and the scanning signal line driving circuit with the shift register having the above-described configuration, an image display device with low power consumption can be realized.

Further, in the image display device having the above configuration, it is preferable that the data signal line driving circuit, the scanning signal line driving circuit, and each pixel are formed on the same substrate.

According to this configuration, the data signal line driving circuit, the scanning signal line driving circuit, and each pixel are formed on the same substrate, and the wiring between the data signal line driving circuit and each pixel, In addition, the wiring between the scanning signal line driving circuit and each pixel is disposed on the substrate, and does not need to be provided outside the substrate. As a result, even if the number of data signal lines and the number of scanning signal lines increase, the number of signal lines extending out of the substrate does not change, so that labor required for assembly can be reduced. In addition, since there is no need to provide terminals for connecting each signal line to the outside of the board,
It is possible to prevent an undesired increase in the capacitance of each signal line and to prevent a reduction in the degree of integration.

By the way, the polycrystalline silicon thin film can easily enlarge the substrate area as compared with the monocrystalline silicon, while the polycrystalline silicon transistor has, for example, a mobility and a threshold value as compared with the monocrystalline silicon transistor. Are inferior in transistor characteristics. Therefore, when each circuit is manufactured using a single crystal silicon transistor, it is difficult to increase the display area, and when each circuit is manufactured using a polycrystalline silicon thin film transistor, the driving capability of each circuit is reduced. When both the driving circuits and the pixels are formed on different substrates, it is necessary to connect the two substrates with each signal line,
This takes time and effort during manufacturing and increases the capacity of each signal line.

Therefore, in the image display device of each configuration described above, it is preferable that the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element composed of a polycrystalline silicon thin film transistor.

In this configuration, since the data signal line driving circuit, the scanning signal line driving circuit, and each pixel each include a switching element formed of a polycrystalline silicon thin film transistor, the display area can be easily enlarged. Furthermore, since it can be easily formed on the same substrate, the labor and the capacity of each signal line at the time of manufacturing can be reduced. In addition, since the shift registers having the above-described configurations are used, the clock signal after the level shift can be applied to each flip-flop without any problem even when the driving capability of the level shifter is low. As a result, an image display device with low power consumption and a large display area can be realized.

In addition, in the image display device of each configuration described above, the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element manufactured at a process temperature of 600 degrees or less. Is desirable.

According to this configuration, since the process temperature of the switching element is set to 600 ° C. or less, a normal glass substrate (a glass substrate having a strain point of 600 ° C. or less) is used as a substrate for each switching element. Also, no warping or warping due to processes above the strain point occurs. As a result, an image display device which is easier to mount and has a larger display area can be realized.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below with reference to FIGS. Note that the present invention can be widely applied to a shift register in which the amplitude of an input clock signal is smaller than a drive voltage. Hereinafter, a case where the present invention is applied to an image display device will be described as a preferable example.

That is, as shown in FIG. 2, the image display device 1 according to the present embodiment includes a display section 2 having pixels PIX arranged in a matrix, and a data signal line driving circuit 3 for driving each pixel PIX. And a scanning signal line driving circuit 4. When the control circuit 5 generates a video signal DAT indicating the display state of each pixel PIX, an image can be displayed based on the video signal DAT.

The display unit 2 and both driving circuits 3 and 4 are
They are provided on the same substrate in order to reduce the manufacturing time and the wiring capacitance. Further, in order to integrate more pixels PIX and increase the display area, each of the circuits 2 to 4
Is composed of a polycrystalline silicon thin film transistor formed on a glass substrate. Further, even when a normal glass substrate (a glass substrate having a strain point of 600 degrees or less) is used,
The polycrystalline thin-film silicon transistor is designed to prevent warping and warping caused by processes above the strain point.
Manufactured at a process temperature of 600 degrees or less.

Here, the display unit 2 includes l (L: hereinafter, upper case L is used for convenience of reference) data signal lines SL1 to SLL and each of the data signal lines SL1 to SLL.
And m scanning signal lines GL1 to GLm which intersect with each other. If any positive integer less than L is i and any positive integer less than m is j, a pixel PIX (i, j) is provided for each combination of the data signal line SLi and the scanning signal line GLj, Each pixel PIX (i, j) is arranged in a portion surrounded by two adjacent data signal lines SLi and SLi + 1 and two adjacent scanning signal lines GLj and GLj + 1.

On the other hand, the pixel PIX (i, j) is, for example,
As shown in FIG. 3, a field-effect transistor (switching element) SW whose gate is connected to the scanning signal line GLj and whose drain is connected to the data signal line SLi, and one electrode is connected to the source of the field-effect transistor SW A pixel capacitance CP. The other end of the pixel capacitance CP is connected to a common electrode line common to all the pixels PIX. The pixel capacitance CP is composed of a liquid crystal capacitance CL and an auxiliary capacitance CS added as needed.

When the scanning signal line GLj is selected in the pixel PIX (i, j), the field effect transistor SW is turned on, and the voltage applied to the data signal line SLi is applied to the pixel capacitance CP. On the other hand, while the selection period of the scanning signal line GLj ends and the field effect transistor SW is shut off, the pixel capacitance CP keeps holding the voltage at the time of shutting off. Here, the transmittance or the reflectance of the liquid crystal changes depending on the voltage applied to the liquid crystal capacitance CL. Therefore,
If the scanning signal line GLj is selected and a voltage corresponding to the video data is applied to the data signal line SLi, the pixel PIX (i, j)
Can be changed in accordance with the video data.

In the image display device 1 shown in FIG. 2, the scanning signal line driving circuit 4 selects the scanning signal line GL, and supplies the selected pixel to the pixel PIX corresponding to the combination of the scanning signal line GL and the data signal line SL. Video data is output to each data signal line SL by the data signal line drive circuit 3. As a result, the respective video data is written to the pixels PIX... Connected to the scanning signal line GL. Further, the scanning signal line driving circuit 4 sequentially selects the scanning signal lines GL, and the data signal line driving circuit 3 outputs video data to each data signal line SL. As a result, all pixels P of the display unit 2
Each video data is written to IX.

Here, between the control circuit 5 and the data signal line driving circuit 3, the video data to each pixel PIX is
The video signal DAT is transmitted in a time-division manner, and the data signal line driving circuit 3 converts each video signal from the video signal DAT at a timing based on a clock signal CKS having a predetermined cycle as a timing signal and a start signal SPS. Extracting data.

Specifically, the data signal line drive circuit 3
Is a shift register 3a that sequentially shifts the start signal SPS in synchronization with the clock signal CKS to generate output signals S1 to SL at different timings at predetermined intervals, and a timing indicated by the output signals S1 to SL. , The video signal DAT is sampled, and each data signal line SL1 is sampled.
To SLL to extract video data to be output to the video signal DAT from the video signal DAT. Similarly, the scanning signal line driving circuit 4 outputs scanning signals having different timings at predetermined intervals to the respective scanning signal lines GL1 to GLm by sequentially shifting the start signal SPG in synchronization with the clock signal CKG. The shift register 4a is provided.

Here, the image display device 1 according to the present embodiment
In this example, the display section 2 and both driving circuits 3 and 4 are formed of polycrystalline silicon thin film transistors.
The drive voltages Vcc of ~ 4 are set to, for example, about 15 [V]. On the other hand, the control circuit 5 is formed of a single crystal silicon transistor on a substrate different from each of the circuits 2 to 4, and the driving voltage is, for example, 5 [V] or
The drive voltage is set to a value lower than the drive voltage VCC, such as a voltage lower than that. Although the circuits 2 to 4 and the control circuit 5 are formed on different substrates, the number of signals transmitted between them is larger than the number of signals between the circuits 2 to 4. For example, the video signal DAT, each start signal SPS (SPG) or the clock signal CKS
(CKG). Further, since the control circuit 5 is formed of a single-crystal silicon transistor, it is easy to secure a sufficient driving capability. Therefore, even if they are formed on different substrates, an increase in the labor and the wiring capacity or the power consumption at the time of manufacture is suppressed to a level that does not cause a problem.

Here, in this embodiment, the shift register 11 shown in FIG. 1 is used as at least one of the shift registers 3a and 4a. In the following, in order to include the case of using as any shift register,
Each of the start signals SPS (SPG) is referred to as SP, the number of stages L (m) of the shift register 1 is referred to by n, and the output signal is S
1 to Sn.

Specifically, the shift register 11 has an n-stage set / reset flip-flop (SR
Flip-flop) F1 (1)... And the driving voltage VC
C, and a clock signal CK supplied from the control circuit 5 and having an amplitude smaller than the driving voltage VCC.
(1) include level shifters 13 (1).

In this embodiment, each level shifter 13 (1)
Are provided so as to correspond to the SR flip-flops F1 (1) on a one-to-one basis. As will be described later, even if the amplitude of the clock signal CK is smaller than the drive voltage VCC, there is no problem. It is configured as a current driven type level shifter so that the voltage can be boosted. When i is an integer equal to or less than n and equal to or greater than 1, each level shifter 13 (i) responds based on the clock signal CK and its inverted signal CK bar while the control signal ENAi instructs the operation. The boosted clock signal CKi can be applied to the SR flip-flop F1 (i). Further, while the control signal ENA instructs the operation stop, the operation is stopped and the corresponding S
The application of the clock signal CKi to the R flip-flop F1 (i) can be prevented, and the input switching element, which will be described later, can be shut off during operation stop, thereby reducing the power consumption of the level shifter 13 (i) due to the through current.

On the other hand, the flip-flop unit 12
The configuration is such that a start signal SP having a clock cycle width can be transmitted to the next stage at each edge (rising and falling) of the clock signal CK. Specifically, the output of each level shifter 13 (i) is applied to the SR flip-flop F1 (i) as a negative logic set signal S via the inverter I1 (i). The output Q of each SR flip-flop F1 (i) is output as the output Si of the shift register 11 and the level shifter 13 of the next stage.
(i + 1) is applied as a control signal ENAi + 1. It should be noted that the start signal SP from the control circuit 5 shown in FIG. 1 is applied as the control signal ENA1 to the level shifter 13 (1) in the first stage after being boosted. Further, to each SR flip-flop F1 (i), a signal delayed by the pulse width of the pulse to be transmitted among the set signals to the subsequent SR flip-flop F1 is applied as a reset signal R. In the present embodiment, since a pulse having one clock cycle width is transmitted,
The signal delayed by the clock cycle, that is, the clock signal CK (i + 2) to the SR flip-flop F1 (i + 2) two stages later,
This signal is applied as a positive logic reset signal.

The odd-numbered stage SR flip-flop F1
The clock signal CK is applied to the non-inverting input terminal of the odd-numbered level shifters 13 (1) so that (1), F1 (3)... Are set at the rising edge of the clock signal CK. The signal CK is applied to the inverting input terminal. Conversely, even-numbered level shifters 13 (2),
13 (4)... Have even-numbered stages of SR flip-flops F1 (2).
Are set at the falling edge of the clock signal CK, the clock signal CK is applied to the inverting input terminal, and the inverted signal CK bar is applied to the non-inverting input terminal.

According to the above configuration, as shown in FIG. 4, while the start signal SP is being pulsed, the level shifter 13 (1) at the forefront stage operates to convert the boosted clock signal CK1 to the SR flip-flop. Applied to the pump F1 (1). Thus, the SR flip-flop F1 (1) is set when the clock signal CK first rises after the start of the pulse input, and changes the output S1 to a high level.

The output S1 is used as a control signal ENA2 as
The voltage is applied to the second-stage level shifter 13 (2). As a result, the level shifter 13 (2)
While 1 (1) is outputting a pulse (control signal ENA2 = S1
Is high level), the clock signal CK2 is output.
However, the clock signal CK is applied to the level shifter 13 (2).
Is applied to the inverting input terminal, the level shifter 1
3 (2) outputs the boosted signal as the clock signal CK2, which is opposite in polarity to the clock signal CK. As a result, the SR flip-flop F1 (2) is set when the clock signal CK falls for the first time after the output S1 of the preceding stage goes to the high level, and changes the output S2 to the high level.

Each output signal Si is supplied to the level shifter 1 in the next stage.
3 (i + 1) as the control signal ENAi + 1, the SR flip-flops F1 (2).
Outputs S2... Are output with a delay of a half cycle of the clock signal CK from the outputs S1.

On the other hand, the level shifters 13 (i) of each stage include:
The output CKi + 2 of the level shifter 13 (i + 2) two stages later is applied as a reset signal R. Therefore, each output Si
Changes from high level to low level for one clock cycle. As a result, the flip-flop unit 12 outputs the start signal SP having one clock cycle width to each edge (rising and falling) of the clock signal CK.
Each time, it can be transmitted to the next stage.

Here, each level shifter 13 (i)
Since it is provided for each flip-flop F1 (i), S
Even when the number of stages of the R flip-flops F1 (i) is large, the clock signal CK is boosted by a single level shifter and then applied to all the flip-flops.
The distance between the level shifter and the flip-flop corresponding to each other can be reduced. Therefore, the boosted clock signal C
The transmission distance of Ki can be shortened, and each level shifter 1
3 (i) can reduce the load capacity. Further, since the load capacitance is small, for example, as in the case where the level shifter 13 (i) is configured by a polycrystalline silicon thin film transistor,
Even when it is difficult to ensure sufficient driving capability of the level shifter 13 (i), there is no need to provide a buffer. As a result, power consumption of the shift register 11 can be reduced.

Also, the start signal SP and the output Si-1 of the preceding stage are output.
Is low, each SR flip-flop F
If 1 (i) does not require input of clock signal CKi,
The operation of the level shifter 13 (i) is stopped. In this state, since the clock signal CKi is not driven, power consumption required for driving does not occur. Further, as described later, the power supply itself to the level shift unit 13a provided in each level shifter 13 (i) is stopped, the input switching element is shut off, and no through current flows. Therefore, despite the fact that a large number (n) of current-driven level shifters are provided, the operating level shifter 13
Only in (i), power is consumed. As a result, the power consumption of the shift register 11 can be significantly reduced.

In addition, the level shifter 1 according to the present embodiment
3 (i) is a period during which the SR flip-flop F1 (i) requires the clock signal CKi, that is, from the time when the start signal SP or the output Si-1 of the previous stage starts pulse output, the SR flip-flop F1 (i) The period until it is set,
The determination is made based only on the start signal SP or the output Si-1 of the preceding stage. As a result, the operation / stop of each level shifter 13 (i) can be controlled only by directly applying the start signal SP or the output Si-1 of the preceding stage, and compared with the case where a circuit for creating a new control signal is provided. , The circuit configuration of the shift register 11 can be simplified.

Furthermore, in this embodiment, while each level shifter 13 (i) is stopped, each SR flip-flop F
Clock input to 1 (i) is blocked. Therefore, the start signal SP can be transmitted correctly without providing a switch that conducts according to the necessity of clock input separately from the level shifter 13 (i).

Here, each SR flip-flop F1
For example, as shown in FIG. 5, a P-type MOS transistor P1, N-type MOS transistors N2 and N3 are connected in series between a drive voltage VCC and a ground level, and transistors P1 and N3 At the gate,
A negative logic set signal S is applied. Further, a positive logic reset signal R is applied to the gate of the transistor N2. Further, the drain potentials of the two transistors P1 and N2 connected to each other are equal to the inverter INV1.
At INV2, each is inverted and output as an output signal Q. On the other hand, between the drive voltage VCC and the ground level,
Further, P-type MOS transistors P4 and P5 and N-type MOS transistor N6 connected in series, respectively.
-N7 is provided. Both transistors P5 · N
The drain of the transistor 6 is connected to the input of the inverter INV1, and the gates of the transistors P5 and N6 are connected to the output of the inverter INV1. Further, a reset signal R is applied to the transistor P4, and a set signal S is applied to the gate of the transistor N7.

In the SR flip-flop F1, FIG.
When the set signal S changes to active (low level) while the reset signal R is inactive (low level), the transistor P1 conducts and the input of the inverter INV1 changes to high level. Let it. As a result, the output signal Q of the SR flip-flop F1 changes to a high level.

In this state, the transistors P4 and P4 are driven by the reset signal R and the output of the inverter INV1.
5 conducts. Further, the transistors N2 and N6 are shut off by the reset signal R and the output of the inverter INV1. Thereby, even if the set signal S changes to inactive, the input of the inverter INV1 is maintained at the high level, and the output signal Q is maintained at the high level.

Thereafter, when the reset signal R becomes active, the transistor P4 is turned off, and the transistor N2 is turned off.
Becomes conductive. Here, since the set signal S remains inactive, the transistor P1 is turned off and the transistor N3 is turned on. Therefore, the inverter IN
The input of V1 is driven to low level, and the output signal Q changes to low level.

On the other hand, the level shifter 13 according to this embodiment
For example, as shown in FIG. 7, a level shift unit 13a that shifts the level of a clock signal CK and a level shift unit 13a during a stop period when the supply of the clock signal CK is unnecessary.
Power supply control unit 13b for interrupting power supply to the power supply, and an input control unit (switch) 1 for interrupting the level shift unit 13a and the signal line through which the clock signal CK is transmitted during the suspension period.
3c, an input switching element cutoff control section (input signal control section) 13d for cutting off the input switching element of the level shift section 13a during the stop period, and maintaining the output of the level shift section 13a at a predetermined value during the stop period. Output stabilizing section (output stabilizing means) 13e.

The level shift section 13a is a P-type MO having sources connected to each other as a differential input pair of an input stage.
S transistors P11 and P12 and both transistors P1
1. A constant current source I for supplying a predetermined current to the source of P12
c and a current mirror circuit, and both transistors P
N-type MOS transistors N13 and N14 serving as active loads of P11 and P12, and CM for amplifying the output of the differential input pair
It has transistors P15 and N16 having an OS structure.

The gate of the transistor P11 is connected to a clock signal CK via a transistor N31 described later.
And the inverted signal CK of the clock signal is input to the gate of the transistor P12 via a transistor N33 described later. The transistor N13
The gates of N14 are connected to each other and further connected to the drains of the transistors P11 and N13.
On the other hand, the drains of the transistors P12 and N14 connected to each other are connected to the gates of the transistors P15 and N16. The sources of the transistors N13 and N14 are connected to an N-type MO as the power supply control unit 13b.
Grounded via S transistor N21.

On the other hand, in the input control section 13c on the transistor P11 side, an N-type MOS transistor N is connected between the clock signal CK and the gate of the transistor P11.
31 are provided. In the input switching element cutoff control section 13d on the transistor P11 side, a P-type transistor is connected between the gate of the transistor P11 and the drive voltage VCC.
An OS transistor P32 is provided. Similarly, the inverted signal CK bar of the clock signal is applied to the gate of the transistor P12 via the transistor N33 as the input control unit 13c, and the driving voltage is applied via the transistor P34 as the input switching element cutoff control unit 13d. VCC is provided.

The output stabilizing section 13e stabilizes the output voltage OUT of the level shifter 13 during the suspension period to the ground level. The output stabilizing section 13e is connected between the drive voltage VCC and the gates of the transistors P15 and N16. Type M
An OS transistor P41 is provided.

In this embodiment, the control signal ENA
Is set to indicate the operation of the level shifter 13 when it is at a high level. Therefore, the control signal ENA is applied to the gates of the transistors N21 to N41.

In the level shifter 13 having the above configuration, when the control signal ENA indicates an operation (when the control signal ENA is at a high level), the transistors N21, N31 and N33 are turned on,
The transistors P32, P34 and P41 are turned off. In this state, the current of the constant current source Ic is
After passing through transistors 1 and N13 or transistors P12 and N14, the current further flows through transistor N21. The clock signal CK or the inverted signal CK of the clock signal is applied to the gates of the transistors P11 and P12. As a result, a voltage of an amount corresponding to the ratio between the respective gate-source voltages flows through both transistors P11 and P12. On the other hand, since the transistors N13 and N14 work as active loads, the voltage at the connection point of the transistors P12 and N14 is
The voltage corresponds to the difference between the voltage levels of K bar. This voltage becomes the gate voltage of the CMOS transistors P15 and N16, is power-amplified by both transistors P15 and N16, and is output as the output voltage OUT.

The level shifter 13 outputs the clock signal C
The configuration in which conduction / cut-off of the input stage transistors P11 and P12 is switched by K, that is, unlike the voltage drive type, the input stage transistors P11 and P12
Is a current drive type in which the transistors P1 and P2 always conduct.
The level of the clock signal CK is shifted by dividing the current of the constant current source Ic according to the ratio of the gate-source voltage of 1 · P12. Thus, even when the amplitude of the clock signal CK is lower than the threshold values of the transistors P11 and P12 in the input stage, the level of the clock signal CK can be shifted without any problem.

As a result, as shown in FIG. 4, each level shifter 13 (i) controls the corresponding control signal ENAi.
Is a high level, the peak value of the clock signal CKi is lower than the drive voltage VCC (for example, about 5 [V]).
Of the same shape as the clock signal CK of FIG.
The output voltage O boosted to CC (for example, about 15 [V])
UT can be output.

On the contrary, when the control signal ENAi indicates that the operation is stopped (when it is at the low level), the constant current source I
c, the transistors P11 and N13, or
The current flowing through transistors P12 and N14 is cut off by transistor N21. In this state, the current supplied from the constant current source Ic is supplied to the transistor N2
1, the power consumption due to the current can be reduced. In this state, both transistors P1
Since no current is supplied to 1 · P12, both transistors P11 and P12 cannot operate as a differential input pair, and output terminals, that is, both transistors P12 · N1
4 cannot be determined.

Further, in this state, each input control unit 13
The transistors N31 and N33 of c are cut off. As a result, the signal line transmitting the clock signal CK (CK bar) is separated from the gates of the transistors P11 and P12 in the input stage, and the gate capacitance serving as the load capacitance of the signal line is changed by the level shifter 13 in operation. Limited to only things. As a result, a plurality of level shifters 13 are connected to the signal line.
Although (i) is connected, the load capacity of the signal line can be reduced, and the power consumption of a circuit for driving the clock signal CK (CK bar) can be reduced as in the control circuit 5 shown in FIG. .

During the stop, the transistors P32 and P34 of each input switching element cutoff control section 13d conduct, so that the gate voltages of the transistors P11 and P12 both become the drive voltage VCC, and the transistors P11 and P12 Is shut off. Thus, similarly to the case where the transistor N21 is cut off, the current consumption can be reduced by the current output from the constant current source Ic. In this state, since the transistors P11 and P12 cannot operate as a differential input pair, the potential of the output terminal cannot be determined.

In addition, when the control signal ENA indicates that the operation is stopped, the transistor P41 of the output stabilizing unit 13e is further turned on. As a result, the output terminal, that is, the gate potential of the CMOS transistors P15 and N16 becomes the drive voltage VCC, and the output voltage OUT becomes low. As a result, as shown in FIG.
When NAi indicates that the operation is stopped, the level shifter 13
The output voltage OUT (CKi) of (i) is maintained at a low level regardless of the clock signal CK. As a result, unlike the case where the output voltage OUT is indeterminate while the level shifter 13 (i) is stopped, malfunction of the SR flip-flop F1 (i) can be prevented, and the shift register 11 that can operate stably can be realized.

(Second Embodiment) In the present embodiment, the first
A case where the shift register is composed of a plurality of stages of D flip-flops, which is different from the first embodiment, will be described with reference to FIGS. In each of the following embodiments, members having the same functions as those of the above embodiments will be denoted by the same reference numerals and the description thereof will be omitted for convenience of description.

That is, as shown in FIG. 8, the shift register 21 according to the present embodiment includes a flip-flop unit 22 composed of a plurality of stages of D flip-flops F2 (1). , And has the same configuration as the level shifters 13 (1)... Shown in FIG.
3 (1) ...

Each of the D flip-flops F2 (i) is a D flip-flop that changes the output Q according to the input D while the clock signal CKi is at a high level and maintains the output Q while the clock signal CKi is at a low level. , Each D flip-flop F
The output Q of 2 (i) is output as the output Si and also input to the next-stage D flip-flop F2 (i + 1). The start signal SP is input to the foremost D flip-flop F2 (1).

As in FIG. 1, the odd-numbered level shifters 23 (1) output the boosted clock signal CK as the clock signal CK1 during operation, and the even-numbered level shifters 23 (2). , During operation, clock signal CK
CK2... Which are boosted with the opposite polarity are output. Note that the D flip-flop F2 (i)
Has a corresponding clock signal CKi and an inverter I2
The inverted signal of the clock signal CKi generated in (i) is applied.

Since the output Si of the D flip-flop F2 (i) does not change until the clock signal CKi rises, unlike the SR flip-flop F1 (i) shown in FIG. In addition, the clock signal CKi is required even at the falling point. Therefore, in the present embodiment, the OR circuit G1 (i) for calculating the logical sum of the input and output of each level shifter 23 (i) is provided, and the result of the operation is converted to the corresponding level shifter 23 (i).
As a control signal ENAi.

In the above configuration, as shown in FIG. 9, when the pulse of the start signal SP is inputted, the control signal ENA1 changes to the high level, and the D flip-flop F2 (1)
, The boosted clock signal CK1 is input. As a result, after the start signal SP is pulse-input, at the next rising edge of the clock signal CK1, the output S1 of the D flip-flop F2 (1) changes to the high level, and while the clock signal CK1 is at the low level. Is maintained at a high level even if the start signal SP changes to a low level.

When the clock signal CK1 first rises after the start signal SP changes to the low level,
The output S1 of the D flip-flop F2 (1) changes to a low level. Further, in this state, since both the start signal SP and the output S1 are at low level, the OR circuit G1 (1)
Changes the control signal ENA1 to low level and stops the level shifter 23 (1).

Here, the output Si of each D flip-flop F2 (i) is input to the next stage D flip-flop F2 (i + 1), and the adjacent D flip-flop F2 (i) .F2 (i + 1). )
, Clock signals CKi and CK + 1 having phases opposite to each other are input. As a result, the flip-flop unit 22 can transmit the start signal SP to the next stage at each edge (rising and falling) of the clock signal CK.

In the above configuration, each level shifter 23 (i)
While the corresponding D flip-flop F2 (i) requires the input of the clock signal CKi, that is, after the pulse input to the D flip-flop F2 (i) is started,
The operation is performed until the D flip-flop F2 (i) ends the pulse output, and the operation can be stopped during the remaining period.
As a result, similarly to the first embodiment, the shift register 21 operable with the clock signal CK having an amplitude smaller than the drive voltage VCC and consuming less power can be realized.

Further, unlike the first embodiment, the flip-flop unit 22 according to the present embodiment is constituted by a D flip-flop that changes the output Q based on the input D and the clock signal CK. Even if the pulse width (the number of clocks) of the start signal SP changes, the start signal SP can be transmitted without any problem.

For example, in the sampling section 3b shown in FIG. 2, when the driving capability of the sampling transistor for sampling the video signal DAT is low, a longer sampling period is required, and the output S1 having a longer pulse width (time). Requires Sn. On the other hand, even if the pulse width is the same, the number of clocks increases as the frequency of the clock signal CK increases. Therefore, the optimum value of the pulse width of the start signal SP changes depending on the driving capability of the sampling transistor and the frequency of the clock signal CK. Therefore, in the case of a configuration in which the connection destination of the reset signal R is set in accordance with the pulse width (the number of clocks) of the outputs S1... Like the shift register 11 shown in FIG. It is necessary to design a different circuit. Further, when the same data signal line driving circuit 3 is driven by clock signals CK having different frequencies or when diverted for driving different display units 2, an optimum pulse width cannot be secured, and display quality may be degraded. There is.

On the other hand, the shift register 21 according to the present embodiment can output the outputs S1 having a desired pulse width only by changing the pulse width of the start signal SP. Therefore, it is possible to reduce the time and effort for designing, and to realize the image display device 1 in which the display quality does not deteriorate even in the above case.

However, as shown in FIG. 5, the SR flip-flop F1 can be realized with fewer elements than the D flip-flop F2 shown in FIG. Can work. Further, since the operation / stop of the level shifter 13 (i) of the next stage can be directly controlled by the output Si-1 of the previous stage, the OR circuit G1 (i) is unnecessary. As a result, the optimum pulse width (number of clocks) can be determined in advance, and when a high-speed, small-scale circuit shift register is required, it is preferable to use the SR flip-flop F1.

Here, in each of the D flip-flops F2, for example, as shown in FIG. 10, a P-type MOS transistor P51 is connected between the drive voltage VCC and the ground level.
52, and N-type MOS transistors N53 and N5
4 are connected in series with each other. The above transistor P
The input signal D is applied to the gates of the transistors 52 and N53, and the drain potentials of the transistors P52 and N53 connected to each other are inverted as the output Q after being inverted by the inverter INV51. On the other hand, between the drive voltage VCC and the ground level, furthermore, P-type MOS transistors P55 and P56 and N-type M
OS transistors N57 and N58 are provided. The drains of the transistors P56 and N57 are connected to the input of the inverter INV51, and the respective gates are connected to the output of the inverter INV51. Further, the gates of the transistors P51 and N58 are
The inverted signal CK of the clock signal is applied, and the clock signal CK is applied to the gates of the transistors N54 and P55.

In the D flip-flop F2 having the above structure,
While the clock signal CK is at the high level, the transistor P5
1 · N54 conducts, and the transistors P55 · N58 are cut off. Thereby, the input D is connected to the transistor P52
After being inverted by N53, it is inverted by the inverter INV51. As a result, the output Q changes to the same value as the input D. Conversely, while the clock signal CK is at the low level, the transistors P51 and N54 are cut off, so that the transistors P52 and N53 cannot invert the input D.
In this state, the transistors P55 and N58 conduct, and the output of the inverter INV51 is fed back to the input. As a result, while the clock signal CK is at the low level, the output Q is maintained at the same value as the falling point of the clock signal CK even if the input D is at the high level. Therefore, as shown in FIG. 11, after the input D changes, the output Q of the D flip-flop F2 first
When K rises, it changes following the input D.

On the other hand, each OR circuit G1 has, for example,
As shown in FIG. 12, a series circuit including P-type MOS transistors P61 (1) corresponding to each input IN (1) and an N-type MOS transistor N62 (corresponding to each input IN (1). 1) a parallel circuit consisting of a P-type MOS transistor P63 and an N-type MOS transistor N6
4 CMOS inverters are provided. Here, since the OR circuit G1 is a two-input OR circuit,
The transistors P61 and N62 are provided two each, and the input IN (1) is applied to the gates of the transistors P61 (1) and N62 (1).
The input IN (2) is applied to the gate of N62 (2). The series circuit and the parallel circuit are connected in series with each other, and are arranged between the driving voltage VCC and the ground level. Further, the connection point between the series circuit and the parallel circuit is connected to the input terminal of the CMOS inverter, that is, both transistors P6
3. Connected to the gate of N64. As a result, the OR circuit G1 receives the input IN (1) from the drains of the transistors P63 and N64, which are the output terminals of the CMOS inverter.
-The logical sum of IN (2) can be output.

In FIG. 8, the input / output of each D flip-flop F2 (i) is logically ORed to form the level shifter 23 (i).
An OR circuit G1 (i) for instructing operation / stop is provided for each level shifter itself.
If the operation / stop can be determined by ORing the inputs and outputs of 2 (i), the OR circuit G1 (i) can be omitted.

More specifically, as shown in FIG. 13, in the shift register 21a according to this modification, the level shifter 23
Instead of (i), the level shifter 24 that operates when any of the control signals ENA1 and ENA2 is active (true)
(i) is provided. Accordingly, the OR circuit G1 (i) shown in FIG. 8 is omitted, and the input / output of the D flip-flop F2 (i) is directly input as the control signals ENA1 and ENA2 to the corresponding level shifters 24 (i). .

The level shifter 24 is, for example, as shown in FIG.
As shown in FIG. 7, the configuration is substantially the same as that of the level shifter 13 shown in FIG. 7. However, unlike the level shifter 13, the power supply control unit 24b to the output stabilization unit 24e have the same number in correspondence to the control signals ENA1 and ENA2. (In this case 2
) Of the transistors N21 to N41. Specifically, in the power supply control unit 24b, the transistors N21 (1) and N21 (2) are connected in parallel with each other. Similarly, in the input control unit 24c corresponding to the transistor P11, the transistors N31 (1) and N31 (2)
However, in the input control unit 24c corresponding to the transistor P12, the transistors N33 (1) and N33 (2) are connected in parallel with each other. On the other hand, in the output stabilizing unit 24e, the transistors P41 (1) and P41 (2) are connected in series with each other, and each input switching element cutoff control unit 24d
Is a transistor P32 (1).
P32 (2) or transistors P34 (1) and P34 (2) connected in series to each other. In this embodiment, the shift register 21a transmits a high-level pulse signal.
Of (1) to P41 (2), the gate corresponding to the control signal ENA1 (subscript (1)) is supplied with the control signal ENA1 and the gate corresponding to the control signal ENA2 (subscript is (( The corresponding control signal ENA2 is applied to the gate of (2)).

According to the above configuration, when at least one of the control signals ENA1 and ENA2 is at a high level, one of the transistors N21 (1) and N21 (2) and one of the transistors N31 (1) and N31 (2) are connected. And one of the transistors N33 (1) and N33 (2) conducts. Also,
One of the transistors P32 (1) and P32 (2), one of the transistors P34 (1) and P34 (2), and one of the transistors P41 (1) and P41 (2) are shut off.
As a result, the level shifter 24 operates similarly to the level shifter 13 described above. Conversely, when both of the control signals ENA1 and ENA2 are at the low level, all the N-type transistors N21 (1) to N34 (2) are shut off, and the P-type transistors P31 (1) to P41 (2 ) Since all are conductive, the level shifter 24 is similar to the level shifter 13 described above.
Stops working. As a result, like the level shifter 23 (i) shown in FIG. 8, the level shifter 24 (i)
The operation / stop can be performed according to the input / output of the flip-flop F2 (i), and the same effect can be obtained.

(Third Embodiment) In the first and second embodiments, a level shifter is provided for each flip-flop. However, if a reduction in circuit size is strongly required, the following each As described in the embodiment, a level shifter may be provided for each of the plurality of flip-flops. In the present embodiment, referring to FIGS.
A case where a level shifter is provided for each R flip-flop will be described.

That is, in the shift register 11a according to the present embodiment, as shown in FIG. 15, N SR flip-flops F1 are divided for each K SR flip-flops F1 and divided into a plurality of blocks B1 to BP. Has been split. Further, the level shifter 13 is provided for each block B. In the following, for convenience of explanation, if an integer not less than P is 1 or more and i is an integer not less than K and j is 1 or more, j-th SR flip-flop F1 is replaced with F1 (i , j).

Further, in this embodiment, each block Bi
Each time, an OR circuit G2 (i) for instructing the level shifter 13 (i) with the control signal ENAi is provided. The OR circuit G
2 (i) is an input signal to the block Bi and an SR flip-flop F1 (i, 1) excluding the last stage in the block Bi.
.. Is a K-input OR circuit that calculates a logical sum of each output signal of F1i, (K-1) and outputs the result to the level shifter 13 (i). Here, the input signal to the block Bi is the start signal SP in the foremost block B1, and is the output signal of the preceding block Bi-1 in the second and subsequent blocks Bi. In the OR circuit G2, for example, as shown in FIG. 16, the number of transistors P61 and the number of transistors N62 in the OR circuit G1 shown in FIG. 12 are increased to the number of inputs (in this case, K). It can be realized by a circuit.

As a result, as shown in FIG. 17, the output Si of the SR flip-flop F1 (i, (K-1)) immediately before the last stage from the time when the pulse input to the block Bi starts. , (K-1), the control signal ENAi to the level shifter 13 (i) becomes high level. As a result, the level shifter 13 (i)
SR flip-flop F1 (i, 1) in the block Bi.
While any one of the F1 (i, K) requires input of the clock signal CKi, that is, from the time when the pulse input is started to the time when the last-stage SR flip-flop F1 (i, K) is set In the meantime, the clock signal CKi can be output, and after the SR flip-flop F1 (iK) is set, the pulse of the output Si, (K-1) of the SR flip-flop F1 (i, (K-1)) is output. Operation can be stopped when output is completed.

Here, in this embodiment, the level shifter 1
3 (i) is the SR flip-flop F1 of the block Bi.
(i, j) If any one of them requires a clock input, the clock signal CKi is continuously output.
When the clock signal CKi is supplied to the flip-flop F1 (i, j) as it is, as shown by a broken line in FIG.
After the flip-flop F1 (i, j) is reset, the SR flip-flop F1 (i, j) is set again, so that a plurality of pulses are generated from one pulse of the start signal SP. Therefore, as shown in FIG. 15, the shift register 11a has the level shifter 13 (i) and each S
The switch SW is connected between the R flip-flop F1 (i, j).
i, j are provided, and the SR flip-flop F
The clock signal CKi is applied to the SR flip-flop F1 (i, j) only while 1 (i, (j-1)) is outputting a pulse. While the switch SWi, j is shut off,
In order to prevent the set input to each SR flip-flop F1 (i, j), a P-type MOS transistor Pi, j is connected to the negative logic set terminal S of each SR flip-flop F1 (i, j). The drive voltage VCC is applied via the switch. In the first stage of the shift register 11a, the start signal SP is applied to the gates of the transistors P1,1 and the gates of the remaining stages of the transistors Pi, j are connected to the SR flip-flop F1 (i, j-1) of the preceding stage. Output Si, j-1 is applied. As a result, while the switch SWi, j is shut off, the transistor Pi, j conducts, the set terminal S bar is fixed to a predetermined potential (in this case, the drive voltage VCC), and the set input is prevented. You. As a result, the start signal SP becomes:
It is transmitted without any hindrance. Note that, for example, S in the last stage
After the reset, such as the R flip-flop F1 (i, K), the SR flip-flop F1 to which the clock signal CKi is not supplied, directly passes through the switch SW without passing through the switch SW.
The clock signal CKi may be input.

In the above configuration, as shown in the first embodiment, the level shifter 13 is provided for each SR flip-flop F1.
Is provided, the distance between the level shifter 13 and the SR flip-flop F1 is longer. Since the number of buffers can be reduced and the number of buffers can be reduced, the shift register 11a with low power consumption can be realized in substantially the same manner as in the first embodiment.

Here, when the number of SR flip-flops F1 included in block B is increased, shift register 1
Since the number of level shifters 13 included in 1a can be reduced, the circuit configuration can be simplified. On the other hand, if the number of SR flip-flops F1 is excessively increased, the driving capability of the level shifter 13 becomes insufficient and a buffer is required, so that power consumption increases. Therefore, when it is required to reduce the circuit size without increasing power consumption excessively, without providing a buffer, each block B is provided within a range where the level shifter 13 (i) can supply the clock signal CK (i). SR in
It is desirable to set the number of flip-flops F1.

In the above embodiment, the case where the operation / stop of the level shifter 13 is controlled by the OR circuit G2 has been described as an example. However, similar to the level shifter 24 shown in FIG.
As shown in FIG. 18, the level shifter 14 itself may determine the operation / stop based on each input signal to the OR circuit G2. For example, as shown in FIG. 19, the level shifter 14 has the same number (K in this case) of transistors N in the level shifter 24 shown in FIG.
It can be realized by a circuit provided with 21 to P41.

(Fourth Embodiment) Hereinafter, with reference to FIGS. 20 to 24, for each of a plurality of D flip-flops,
A case where a level shifter is provided will be described.
That is, as shown in FIG. 20, the shift register 21b according to the present embodiment is similar to the shift register 21 shown in FIG. 8, but N D flip-flops F2 are provided every K D flip-flops F2. It is divided into a plurality of blocks B1 to BP. Furthermore, level shifter 2
3 is provided for each block B.

Further, in this embodiment, each block Bi
An OR circuit G3 (i) for instructing the level shifter 23 (i) with the control signal ENAi is provided for each. The OR circuit G
3i is an OR circuit of (K + 1) input, which calculates the logical sum of each input and output of the D flip-flops F2 (i, 1)... F2 (i, K) in the block Bi, and
Output to (i). Here, the input signal to the first-stage D flip-flop F2 (i, 1) is, in the first-stage block B1,
The start signal SP, and in the second and subsequent blocks Bi,
This is an output signal of the preceding block Bi-1. The OR circuit G3 is, for example, as shown in FIG.
In the R circuit G1, the number of transistors P61 and the number of transistors N62 are determined by the number of inputs (in this case, K +
(One).

Thus, as shown in FIG. 22, D flip-flops F2 (i, 1)... F2 (i,
K) requires the input of the clock signal CKi, that is, from the time when the pulse input to the block Bi starts, the D flip-flop F2 (i, K) at the final stage.
Until the end of the pulse output, the control signal ENAi to the level shifter 23 (i) becomes high level, and the level shifter 23 (i) can output the clock signal CKi.
In addition, since the control signal ENAi is at the low level during the remaining period, the operation of the level shifter 23 (i) can be stopped.

In the above configuration, the distance between the level shifter 23 and the D flip-flop F2 is longer than when the level shifter 23 is provided for each D flip-flop F2 as in the shift register 21 shown in the second embodiment. However, as compared with the conventional technology in which the clock signal CK is supplied from a single level shifter to all the D flip-flops, the distance between the two can be reduced and the number of buffers can be reduced, so that the power consumption is substantially the same as in the second embodiment. The shift register 21b with low power can be realized.

Further, as in the third embodiment, in the present embodiment, the number of the level shifters 23 can be reduced as compared with the shift register 21. Further, when it is required to reduce the circuit size without increasing power consumption excessively, the level shifter 23 (i) is provided with the clock signal C without providing a buffer.
It is desirable to set the number of D flip-flops F2 in each block Bi within a range where Ki can be supplied.

In FIG. 20, the case where the operation / stop of the level shifter 23 is controlled by the OR circuit G3 has been described as an example. However, like the shift register 11b shown in FIG. 18, like the shift register 21c shown in FIG. In addition, the level shifter 25 itself, based on each input signal to the OR circuit G3,
Operation / stop may be controlled. The level shifter 25
For example, as shown in FIG. 24, in the level shifter 14 shown in FIG. 19, the same number of inputs (in this case, K + 1
) Can be realized by a circuit provided with the transistors N21 to N41.

(Fifth Embodiment) By the way, in the third embodiment,
In the fourth embodiment, the case where the level shifter or the OR circuit ORs K and (K + 1) signals to control the operation / stop of the level shifter has been described. On the other hand, in the present embodiment, the case where the operation / stop of the level shifter is controlled using the latch circuit is shown in FIG.
This will be described with reference to FIGS.

Specifically, as shown in FIG. 25, in the shift register 11c according to the present embodiment, a latch circuit 31 (i) is provided instead of the OR circuit G2 (i) of the shift register 11a shown in FIG. Is provided. The latch circuit 31
Is configured to change the output by using a pulse input to the first-stage SR flip-flop F1 (i, 1) of the block Bi and a pulse output of the last-stage SR flip-flop F1 (i, K) as a trigger. The operation can be instructed to the level shifter 13 (i) from the time when the pulse input is started to the time when the pulse output is started.

In the latch circuit 31, for example, in the case of the first block B1, as shown in FIG. 26, the start signal SP inverted by the inverter 31a is applied as the negative logic set signal S, and Logic reset signal R
And an SR flip-flop 31b to which the output S1, K of the last-stage SR flip-flop F1 (1, K) is applied. In the subsequent blocks Bi, the output of the preceding block Bi-1 is applied instead of the start signal SP.

In the above configuration, as shown in FIG. 27, the latch circuit 31 (i) includes the first-stage SR flip-flop F1.
From the time when the input to (i, 1) changes to a high level until the output Si, K changes to a high level, the control signal E
Set NAi to high level. Thus, the level shifter 13 (i) can continue to supply the clock signal CKi during the period. When the output Si, K changes to the high level, the control signal ENAi changes to the low level, and the level shifter 13 (i) stops operating. As a result, similarly to the third embodiment, it is possible to realize the shift register 11c that consumes less power than the conventional case.

Further, the latch circuit 31 according to the present embodiment
(i) operates / stops the level shifters 13 (i) (14 (i)) based on K signals as in the OR circuit G2 (i) (level shifter 14 (i)) of the third embodiment. Unlike the determination, the control signal ENAi is generated using two signals as triggers regardless of the number K of stages of the SR flip-flop F1 in the block Bi. Therefore, the number of signal lines transmitting signals required for determination can be reduced to two. Here, when the number of signal lines for determination increases, the number of intersections with the signal lines transmitting the outputs Si, j and the clock signals CK, CKi increases, and the capacity of each signal line may increase. However, in the present embodiment, the number of signal lines for determination is reduced to two, so that an increase in wiring capacity due to the signal lines for determination can be suppressed more than in the third embodiment, and furthermore, power consumption is reduced. A small shift register 11c can be realized.

In FIG. 26, the case where the latch circuit 31 (i) is formed of an SR flip-flop has been described as an example, but the present invention is not limited to this. If the operation / stop of the level shifter 13 (i) can be controlled by using two signals as triggers, the same effect can be obtained by using, for example, a latch circuit 32 shown in FIG. 28 instead of the latch circuit 31 (i). can get.

The latch circuit 32 has two D flip-flops 32a and 32b constituting a frequency divider and N for calculating the negation of the logical sum of the start signal SP and the outputs S1 and K.
An OR circuit 32c and an inverter 32d for inverting the output of the NOR circuit 32c are provided. The output Q of the D flip-flop 32a is
Is input to the D flip-flop 32a. The output LSET of the inverter 32d is applied to the D flip-flop 32a as a clock, and the output of the NOR circuit 32c is applied to the D flip-flop 32b as a clock. Further, the output LOUT of the D flip-flop 32a is output as the control signal ENA1. As a result, as shown in FIG.
(i) is the same as the above-described latch circuit 31 (i).
From the start of the pulse input to the flip-flop F1 (i, 1) to the rising of the output Si, K, the control signal ENAi at a high level is output to instruct the level shifter 13 (i) to operate.

In this embodiment, the latch circuit (31
As the trigger of (32), the start of pulse input to the first-stage SR flip-flop F1 (i, 1) and the start of pulse output to the last-stage SR flip-flop F1 (i, K) are used. It is not limited to this. SR in block Bi
A signal capable of setting the control signal ENAi to active at a timing before the period when the flip-flop F1 requires the clock signal CKi, and a signal capable of setting the control signal ENAi to inactive at a timing after the period. The same effect can be obtained by using a trigger.

(Sixth Embodiment) In the present embodiment, a structure in which operation / stop of a level shifter is controlled by a latch circuit in a shift register using a D flip-flop will be described with reference to FIGS. .

That is, in the shift register 21d according to the present embodiment, the O of the shift register 21b shown in FIG.
Instead of the R circuit G3 (i), a latch circuit 31 shown in FIG.
In substantially the same manner as (i), the pulse input to the D flip-flop F2 (i, 1) at the first stage and the D flip-flop F2 (i,
A latch circuit 33 (i) triggered by the pulse output of K) is provided. However, as described above, in the case of the D flip-flop, the last stage D flip-flop F2
Since the clock signal CKi is required until (i, K) stops the pulse output, the latch circuit 33 (i) operates from the time when the pulse input is started to the time when the pulse output is stopped. During this period, the operation is instructed to the level shifter 23 (i).

More specifically, taking the first block B1 as an example, as shown in FIG. 31, for example, as shown in FIG. 31, in addition to the latch circuit 31 shown in FIG. A NOR circuit 33c for calculating the negation of the logical sum with the outputs S1 and K of the above, and an inverter 33d for inverting the calculation result. Note that the next and subsequent blocks Bi
In this case, the output of the preceding block Bi-1 is applied instead of the start signal SP.

In the above configuration, as shown in FIG. 32, the latch circuit 33 (1) includes the D flip-flop F2 (1,
When the input to 1) changes to high level, the output S
Until 1, K changes to low level, the control signal ENA1
Is set to high level. Thereby, the level shifter 2
3 (1) can continue to supply the clock signal CK1 during this period. When the outputs S1 and K change to low level, the control signal ENA1 changes to low level, and the level shifter 23 (1) stops operating. As a result, similarly to the fourth embodiment, it is possible to realize the shift register 21d that consumes less power than the conventional case.

Further, in the present embodiment, as in the fifth embodiment, the number of signal lines required to determine the operation / stop of the level shifter 23 can be reduced, so that the number of signal lines for determination is higher than in the fourth embodiment. Therefore, it is possible to suppress an increase in wiring capacitance due to the above, and to realize the shift register 21d with low power consumption.

In FIG. 31, latch circuit 33 is connected to SR
Although the description has been made by taking the case of the flip-flop as an example, the present invention is not limited to this. If the operation / stop of the level shifter 13 can be controlled by using two signals as triggers,
Similar effects can be obtained by using, for example, a latch circuit 34 shown in FIG. 33 instead of the latch circuit 31 (i).

In the latch circuit 34, N shown in FIG.
An OR circuit 33c and an inverter 33d are added to the latch circuit 32 shown in FIG. As a result, FIG.
As shown in FIG.
Similarly, from the time when the pulse input to the D flip-flop F2 (i, 1) at the first stage of the block Bi is started to the time when the D flip-flop F2 (i, K) at the last stage ends the pulse output, By outputting a high-level control signal ENAi, an operation can be instructed to the level shifter 23 (i).

In this embodiment, the latch circuit (33
-34), the start of the pulse input to the D flip-flop F2 (i, 1) at the front stage and the end of the pulse output of the D flip-flop F2 (i, K) at the last stage are used. It is not limited to this. A signal capable of setting the control signal ENAi to active at a timing before the period when the D flip-flop F2 in the block Bi requires the clock signal CKi, and setting the control signal ENAi to inactive at a timing after the period. A similar effect can be obtained if a possible signal is used as a trigger.

(Seventh Embodiment) Referring to FIG. 35, a level shifter 23 (24, 25) transmits a clock signal CK to a plurality of D flip-flops F2 as in the fourth and sixth embodiments. Shift register 21 for supplying
In b to 21d, a configuration capable of further reducing power consumption will be described.

More specifically, the shift register according to the present embodiment has the same configuration as the shift registers 21b to 21d, except that the clock signal control circuit 26 (i, j) is provided for each D flip-flop F2 (i, j). , j) are provided, and the level shifters 23 (i) (24 (i), 25 (i): hereinafter, 23 (i)
Supplies the boosted clock signal CK (i) only to the D flip-flop F2 which needs a clock input.

The clock signal control circuit 26 (i, j)
As shown in FIG. 35, a switch SW1 (i, j) provided on a signal line through which a clock signal CKi is transmitted, and a switch SW2 (i, j) provided on a transmission line of an inverted signal CKi bar of the clock signal CKi. ). Both switches S
W1 (i, j) · SW2 (i, j) is the level shifter 2 shown in FIG.
Similarly to 3 (i, j), the D flip-flop F2 (i, j) is controlled by an OR circuit G1 (i, j) that calculates the logical sum of the input and output of the D flip-flop F2 (i, j). Signal CKi
(CKi bar) conducts when required, and is cut off when clock input is not required. Further, the clock signal control circuit 26 (i, j) has a D flip-flop F
An N-type MOS transistor N71 (i, j) provided between the clock input terminal 2 (i, j) and the ground potential, an inverted clock input terminal of the D flip-flop F2 (i, j) and a drive voltage A P-type MOS transistor P72 (i, j) provided between the power supply and the power supply Vcc is provided. The above transistor N
The output of the OR circuit G1 (i, j) is applied to the gate of the transistor P72 (i, j) after being inverted by the inverter INV71 (i, j). Has O
The output of the R circuit G1 (i, j) is applied.

In the above configuration, the corresponding switch SW1 (i, j) (SW2) receives the boosted clock signal CKi (CKi bar) for a necessary period by the corresponding D flip-flop F2 (i, j).
(i, j)) conducts and applies the clock signal CKi (CKi bar) to the D flip-flop F2 (i, j). On the other hand, during a period in which no clock input is required, the switch SW1 (i, j)
SW2 (i, j) is cut off, for example, both switches SW1 (i, j) and SW2 (i, j) such as D flip-flop F2 (i, j).
The circuit after j) is separated from the level shifter 23 (i).
Further, during a period in which no clock input is required, the transistors N71 (i, j) and P72 (i, j) are turned on to connect the clock input terminal and the inverted input terminal of the D flip-flop F2 (i, j). Since each of them is maintained at a predetermined value (low level and high level), unlike the case where both input terminals are undefined, malfunction of the D flip-flop F2 (i, j) can be suppressed.

According to the above configuration, the circuit after the switches SW1 (i, j) and SW2 (i, j) and the level shifter 23 (i) are separated from each other during the period in which the clock input is not required. In (i), only the D flip-flop F2 (i, j) which needs the clock signal CK (i) at the present time needs to be driven. Therefore, the load capacity of the level shifter 23 (i) can be significantly reduced and power consumption can be reduced as compared with the case where all the D flip-flops F2 (i, 1) to F2 (i, K) in the block Bi are driven. . As a result, a shift register with low power consumption can be realized.

In the above description, the D flip-flop F2
The case where the clock signal control circuit 26 (i, j) is provided for each (i, j) has been described as an example, but the present invention is not limited to this. For example, the clock signal control circuit 26 (i, j) A control circuit 26 may be provided. In this case, both switches SW1 and SW2 are driven while the D flip-flop F2 connected to both switches SW1 and SW2 requires a clock input, that is, after the pulse input to the foremost D flip-flop F2 is started. For example, the same operation as the OR circuit G3 shown in FIG. 20 and the latch circuit 33 (34) shown in FIG. 30 (FIG. 33) is performed so that the D-flip-flop F2 of the last stage can conduct until the pulse output ends. Controlled by the circuit. In this case, although the load capacity of the level shifters 23 (24, 25) is increased as compared with the configuration in which the clock signal control circuit 26 is provided for each D flip-flop F2, the number of clock signal control circuits 26 can be reduced. The circuit configuration can be simplified.

(Eighth Embodiment) By the way, for example, in the data signal line driving circuit 3 and the scanning signal line driving circuit 4 shown in FIG.
The outputs of the stages 11a to 11c, 21 and 21a to 21d) may be directly used as signals indicating timing, or a signal obtained by performing a logical operation on outputs of a plurality of stages may be used as a timing signal. is there.

In the following, a structure suitable for performing a logical operation on outputs of a plurality of stages in a shift register using an SR flip-flop F1 as in the first, third and fifth embodiments will be described with reference to FIGS. This will be described with reference to FIG. It should be noted that any configuration using the SR flip-flop F1 can be applied to other embodiments, but the following description will be made by taking the case of the first embodiment as an example.

That is, the shift register 11d according to the present embodiment, in addition to the configuration of the shift register 11 shown in FIG. 1, calculates the logical product of two outputs Si and Si + 1 adjacent to each other, and determines the result of the calculation with the timing. An AND circuit G4 (i) for outputting the signal SMPi is provided. Further, an SR flip-flop F1 (0) is provided at a stage preceding the foremost SR flip-flop F1 (1), and calculates the logical product of the output S0 of the SR flip-flop F1 (0) and the output S1. And an AND circuit G4 (0) for output. Further, an inverted signal SP bar of the start signal SP is applied to the SR flip-flop F1 (0) as a negative logic set signal, and the output of the SR flip-flop F1 (0) is a level shifter of the next stage. 13 (1) is the control signal ENA1
Is entered as The SR flip-flop F1
(0) is similar to the SR flip-flop F1 (i) of the other stage,
The output CK2 of the level shifter 13 (2) after the number of stages (two stages in this case) corresponding to the pulse width of the pulse signal to be transmitted is applied.

Here, each SR flip-flop F1
(0), F1 (1)... Of outputs S0, S1,..., Only output S0 is connected to a single AND circuit G4 (0), and the other outputs Si are connected to two AND circuits G4 (0). i-1) .G4 (i). As a result, SR flip-flop F1
(0) and the remaining SR flip-flop F1 (i) have different output loads, and even if driven at the same timing, the output S0 and the remaining outputs S1...
Are different from each other. Therefore, when the frequency of the clock signal CK is high, the output signal of the AND circuit G4 (0) becomes a dummy signal DUMMY that is not used in a subsequent circuit in order to suppress timing variations due to the delay time shift. Only the remaining outputs SMP1 of the AND circuits G4 (1) are used for video signal extraction.

In the above configuration, unlike the other stages, the inverted signal SP bar not synchronized with the clock signal CK is applied to the SR flip-flop F1 (0) as a negative logic set signal. (Such as a rising edge and a pulse width) are determined by another SR flip-flop F1.
(1) are different from the output S1. However, as described above, the output S0 is not used as a dummy signal DUMMY in a subsequent circuit. Therefore, even if the timing of the output S0 is different, the shift register 11d
Can output timing signals SMP1... Having different timings at predetermined time intervals without any problem.

Further, in the above configuration, the inverted signal SP is applied to the SR flip-flop F1 (0), and the level shifter 13 is omitted. Therefore, the number of level shifters 13 can be reduced as compared with the case where the level shifters 13 are provided also in the SR flip-flop F1 (0).

In the first to eighth embodiments, the case where the level shifters (13, 14, 23 to 25) are of the current drive type has been described as an example. However, as shown in FIG. The level shifter 41 may be used. The level shifter 41a of the level shifter 41 is, as an input switching element, an N-type MOS transistor N81 which is turned on / off in response to a clock signal CK, and is turned on / off in response to an inverted signal CK bar of the clock signal CK. An N-type MOS transistor N82. A drive voltage VCC is applied to the drain of each transistor N81 (N82) via a P-type MOS transistor P83 (P84) as a load.
-The source of N82 is grounded. The potential at the connection point between the transistors N82 and P84 is output as the output OUT of the level shifter 41 and is applied to the gate of the transistor P83. Similarly, the potential at the connection point between the transistors N81 and P83 is output as the inverted output OUT bar of the level shifter 41 and is applied to the gate of the transistor P84.

On the other hand, the level shifter 41 includes an N-type MOS as an input open switch section (switch) 41b.
Transistors N91 and N92 are provided. During operation of the level shifter 41, a clock signal CK is applied to the gate of the transistor N81 via the transistor N91, and a gate of the transistor N82 is applied to the gate of the transistor N82 via the transistor N92. Thus, an inverted signal CK bar of the clock signal CK is applied.

The level shifter 41 includes an N-type MOS transistor N93 as an input stabilizing section 41c.
And a P-type MOS transistor P94. Thus, while the level shifter 41 is stopped, the gate of the transistor N81 is grounded via the transistor N93, and the driving voltage VCC is applied to the gate of the transistor N82 via the transistor P94.
The input stabilizing section 41c corresponds to the output stabilizing means described in the claims, and the input stabilizing section 41c includes the transistors N81.
The input voltage to N82 is controlled to stabilize the output. Here, the level shifter 41 is a voltage-driven type, and the output O
Since power is consumed only when changing the UT, no power consumption occurs even when the output voltage is controlled by the input voltage when the level shifter 41 is stopped.

In the present embodiment, when the control signal ENA is at the high level, the operation of the level shifter 41 is shown. Therefore, the control signal ENA is applied to the gates of the transistors N91, N92 and P94, and the transistor N93
Is applied after the control signal ENA is inverted by the inverter INV91.

In the above configuration, when the control signal ENA is at a high level, the transistors N91 and N92 conduct, and the transistors N81 and N82 control the clock signal CK and
Conduction / interruption is performed according to the inverted signal CK bar. Thus, the output OUT is boosted to the level of the drive voltage VCC when the clock signal CK is at the high level, and is at the ground level when the clock signal CK is at the low level.

Conversely, when the control signal ENA is at a low level, the transistors N93 and P94 are turned on, so that the transistor N81 is turned off and the transistor N82 is turned off.
Becomes conductive. As a result, the output OUT is maintained at the ground level, and the inverted output OUT is maintained at the drive voltage VCC. In this state, both transistors N91 and N9
2, the gate of the transistor N81 (N82) as an input switching element is disconnected from the transmission line of the clock signal CK (CK bar). Thereby, for example, the load capacitance and power consumption of the drive circuit for the clock signal CK (CK bar) such as the control circuit 5 shown in FIG. 2 can be reduced.

In FIG. 38, the level shifters 13.2
3, the operation / stop is controlled by one control signal ENA as an example.
Similarly to 24 and 25, if the number of transistors N91 to P94 and inverter INV91 is increased in accordance with the number of control signals ENA, operation / stop can be controlled by a plurality of control signals ENA.

Even when the level shifter 41 having the above configuration is used, a plurality of level shifters 41 are provided.
At least one of the level shifters 41 that do not require a clock output
In this case, the load capacity of each level shifter can be reduced and the power consumption of the shift register can be reduced as compared with the case where a single level shifter supplies a clock signal to all flip-flops of the shift register.

However, the current-driven level shifters 13 (14, 23 to 2) shown in the first to eighth embodiments are described.
5: In the following, the current is constantly flowing to the input switching elements (P11 and P12) during operation of the level shifter 13), so that the amplitude of the clock signal CK is smaller than that of the input switching elements (transistors N81 and N82). Even if it is lower than the threshold value and the level shifter 41 cannot operate, the clock signal CK can be boosted without any problem. Further, since the level shifter 13 is stopped according to the necessity of the clock output, the power consumption increases even if the output is not changed, despite the fact that there are a plurality of level shifters 13 consuming power. Can be suppressed. Therefore, it is desirable to use the current-driven level shifter 13.

In the third to seventh embodiments, the case where the level shifters (13, 14, 23 to 25) are provided for each of the K flip-flops (F1, F2) has been described as an example. If the register is divided into a plurality of blocks and a level shifter is provided for each block, substantially the same effect can be obtained even if the number of flip-flops included in each block is not the same.

Further, in each of the above-described embodiments, an image display device has been described as an example of application of the shift register. However, if the clock signal CK having an amplitude lower than the drive voltage of the shift register is applied, The shift register according to the present invention can be widely applied. However, in the image display device, since the improvement of the resolution and the enlargement of the display area are strongly required, the number of stages of the shift register is large, and the driving capability of the level shifter cannot be sufficiently secured in many cases.
Therefore, it is particularly effective when applied to a drive circuit of an image display device.

[0156]

As described above, in the shift register according to the present invention, the flip-flop is divided into a plurality of blocks each including at least one flip-flop, and the level shifter for boosting the clock signal having an amplitude smaller than the drive voltage is as follows. In addition to being provided for each block, at least one of the plurality of level shifters corresponding to a block that does not require the input of the clock signal for transmission of the input pulse at that time is stopped. is there.

In this configuration, since a plurality of level shifters are provided in the shift register, the distance from each level shifter to the flip-flop can be reduced. At least one of the plurality of level shifters has stopped operating. As a result, there is an effect that a shift register which can operate with a low-voltage clock signal input and consumes low power can be realized.

In the shift register according to the present invention, in the above configuration, the specific block includes a D flip-flop,
The specific level shifter is configured to start operating when a pulse input to the specific block is started, and to stop the operation after the last stage flip-flop of the specific block finishes pulse output.

According to this structure, the specific level shifter
During a period required when the D flip-flop of the specific block operates, the clock signal after the level shift is supplied,
When the input of the clock signal to the flip-flop is unnecessary, the operation is stopped, so that an input pulse having a different pulse width can be transmitted and a shift register with low power consumption can be realized.

The shift register according to the present invention, in the above configuration, includes a plurality of D flip-flops in a specific block, and the specific level shifter controls a signal input to the specific block and a flip-flop at the last stage of the specific block. And a latch circuit that changes the output in accordance with the output signal of FIG.

According to this configuration, the output of the latch circuit changes based on the two signals, and the operation / stop of the specific level shifter is controlled. Therefore, even when the number of flip-flops in the specific block is large, the shift register can be used. This has the effect of simplifying the circuit configuration.

In the shift register according to the present invention, in the above-mentioned configuration, the level shifter includes a current-driven type level shift section in which an input switching element for applying the clock signal is always conductive during operation.

According to this configuration, since at least one of the current-driven level shifters stops operating, the level can be shifted even when the amplitude of the clock signal is lower than the threshold voltage of the input switching element, and This has the effect of realizing a shift register with low power consumption.

The shift register according to the present invention, in the shift register having the above-described configuration, is provided with an input signal control section for supplying a signal of a level at which the input switching element is cut off to the level shift section to stop the level shifter. Configuration.

According to this configuration, since the input signal control section controls the level of the input signal to cut off the input switching element, the power consumption during the operation is reduced by the amount of current flowing to the input switching element during operation. The effect that it can reduce is produced.

The shift register according to the present invention, in the above configuration, includes a power supply control unit for stopping power supply to the level shift unit and stopping the level shifter.

According to this configuration, since the power supply to each level shift unit is stopped to stop the level shifter, the power consumption can be reduced by the amount of power consumed by the level shifter during stop and operation. It works.

In the shift register according to the present invention, in each of the above structures, the level shifter has an output stabilizing means for maintaining an output voltage at a predetermined value when the level shifter is stopped.

According to this configuration, while the level shifter is stopped, the output voltage of the level shifter is maintained at a predetermined value by the output stabilizing means, thereby preventing a malfunction of the flip-flop caused by the indefinite output voltage. This makes it possible to realize a more stable shift register.

In the shift register according to the present invention, in each of the above structures, a switch is provided between the level shift section and the clock signal transmission line, the switch being opened while the level shifter is stopped. It is.

In this configuration, the input switching elements connected to the clock signal line are limited to those of the operating level shifter, so that the load capacity of the clock signal line can be reduced, and the consumption of the circuit for driving the clock signal line can be reduced. This has the effect of reducing power consumption.

As described above, the image display device according to the present invention has a configuration in which at least one of the data signal line driving circuit and the scanning signal line driving circuit includes the shift register having any one of the above-described configurations.

According to this configuration, since at least one of the data signal line driving circuit and the scanning signal line driving circuit is provided with the shift register of each of the above-described configurations, it is possible to realize an image display device with low power consumption. Play.

In the image display device according to the present invention, in the above configuration, the data signal line driving circuit, the scanning signal line driving circuit and each pixel are formed on the same substrate.

According to this configuration, even if the number of data signal lines and the number of scanning signal lines increase, the number of signal lines extending out of the substrate does not change. In addition to this, there is an effect that the reduction in the degree of integration can be prevented.

In the image display device according to the present invention, in the above configuration, the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element made of a polycrystalline silicon thin film transistor.

In this configuration, since the data signal line driving circuit, the scanning signal line driving circuit, and each pixel each include a switching element formed of a polycrystalline silicon thin film transistor, the power consumption is small and the display area is small. This has the effect of realizing an image display device having a wide width.

In the image display device according to the present invention, the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element manufactured at a process temperature of 600 ° C. or less. It is.

According to this configuration, even when a normal glass substrate (a glass substrate having a strain point of 600 ° or less) is used, warpage or warpage due to a process at or above the strain point does not occur, so that mounting is easier. Thus, an effect that an image display device having a larger display area can be realized is achieved.

[Brief description of the drawings]

FIG. 1 illustrates one embodiment of the present invention, and is a block diagram illustrating a main configuration of a shift register including a set / reset flip-flop.

FIG. 2 is a block diagram showing a main configuration of an image display device using the shift register.

FIG. 3 is a circuit diagram illustrating a configuration example of a pixel in the image display device.

FIG. 4 is a timing chart showing an operation of the shift register.

FIG. 5 is a circuit diagram showing a configuration example of a set / reset flip-flop used in the shift register.

FIG. 6 is a timing chart showing the operation of the set / reset flip-flop.

FIG. 7 is a circuit diagram showing a configuration example of a level shifter in the shift register.

FIG. 8 illustrates another embodiment of the present invention, and is a block diagram illustrating a main configuration of a shift register including a D flip-flop.

FIG. 9 is a timing chart showing the operation of the shift register.

FIG. 10 is a circuit diagram showing a configuration example of the D flip-flop.

FIG. 11 is a timing chart showing the operation of the D flip-flop.

FIG. 12 is a circuit diagram illustrating a configuration example of an OR circuit used in the shift register.

FIG. 13 is a block diagram showing a modified example of the shift register.

FIG. 14 is a circuit diagram illustrating a configuration example of a level shifter in the shift register.

FIG. 15 illustrates still another embodiment of the present invention, and is a block diagram illustrating a shift register in which a level shifter is provided for each of a plurality of set / reset flip-flops.

FIG. 16 is a circuit diagram illustrating a configuration example of an OR circuit used in the shift register.

FIG. 17 is a timing chart showing the operation of the shift register.

FIG. 18 is a block diagram showing a modification of the shift register.

FIG. 19 is a circuit diagram showing a configuration example of a level shifter in the shift register.

FIG. 20 shows still another embodiment of the present invention, and is a block diagram illustrating a shift register provided with a level shifter for each of a plurality of D flip-flops.

FIG. 21 is a circuit diagram illustrating a configuration example of an OR circuit used in the shift register.

FIG. 22 is a timing chart showing the operation of the shift register.

FIG. 23 is a block diagram showing a modification of the shift register.

FIG. 24 is a circuit diagram showing a configuration example of a level shifter in the shift register.

FIG. 25, showing still another embodiment of the present invention, is a block diagram illustrating a shift register including a latch circuit for controlling the operation of a level shifter and a set / reset flip-flop.

FIG. 26 is a block diagram illustrating a configuration example of the latch circuit.

FIG. 27 is a timing chart showing the operation of the shift register.

FIG. 28 is a block diagram showing another configuration example of the latch circuit.

FIG. 29 is a timing chart showing the operation of the latch circuit.

FIG. 30 is a block diagram showing a shift register including the latch circuit and a D flip-flop according to still another embodiment of the present invention.

FIG. 31 is a block diagram illustrating a configuration example of the latch circuit.

FIG. 32 is a timing chart showing the operation of the shift register.

FIG. 33 is a block diagram showing another configuration example of the latch circuit.

FIG. 34 is a timing chart showing the operation of the latch circuit.

FIG. 35 shows still another embodiment of the present invention, and is a circuit showing a clock signal control circuit provided when a level shifter of each block selectively supplies a clock signal to a D flip-flop in the block. FIG.

FIG. 36 shows another embodiment of the present invention, and is a block diagram showing a main configuration of a shift register.

FIG. 37 is a timing chart showing the operation of the shift register.

FIG. 38, showing a modification of the present invention, is a circuit diagram illustrating a voltage-driven level shifter.

FIG. 39 shows a conventional example and is a block diagram showing a shift register including a level shifter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Image display device 3 Data signal line drive circuit 4 Scanning signal line drive circuit 11 ・ 11a-11d ・ 21 ・ 21a〜21c Shift register 13.14 ・ 23〜25 ・ 41 Level shifter 13a ・ 14a ・ 23a〜25a ・ 41a Level shift Units 13b, 14b, 23b to 25b Power supply control unit 13c, 14c, 23c to 25c Input control unit (switch) 13d, 14d Input switching element cutoff control unit (input signal control unit) 13e, 14e, 23e to 25e Output stabilization unit (Output stabilizing means) 23d to 25d Input switching element cutoff control section (input signal control section) 31 to 34 Latch circuit 41b Input open switch section (switch) 41c Input stabilizing section (output stabilizing means) B1 ... Block (specific block) F1 (1)… SR flip-flop (flip-flop) 2 (1) ... D flip-flop (flip-flop) P11 · P12 transistor (input switching element) PIX pixel

Continued on the front page (72) Inventor Kazuhiro Maeda 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation (72) Inventor Yasuka Kaise 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation (72) Inventor Michael James Brownlaw Ox4 4 UK Wix Oxford, Sandford On Thames, Church Road 124 (72) Inventor Graham Andrew Kerns Ox2 8N Oxford, Catteslow, Bonn Close 22

Claims (11)

[Claims] A plurality of flip-flops operating in synchronization with a clock signal; and a level shifter for boosting a clock signal having an amplitude smaller than a drive voltage of the flip-flop and applying the boosted clock signal to each of the flip-flops. In a shift register that transmits an input pulse in synchronization with the clock signal, each of the flip-flops is divided into a plurality of blocks each including at least one flip-flop, and the level shifter is provided for each of the blocks. At least one of the plurality of level shifters corresponding to a block that does not require the input of the clock signal to transmit the input pulse at that time is stopped, and a specific block of the blocks is: The flip-flop includes a D flip-flop. The specific level shifter corresponding to the specific block starts operating when a pulse input to the specific block is started, and operates after the last stage flip-flop of the specific block finishes pulse output. A shift register, wherein the shift register is stopped. 2. The method according to claim 1, wherein the plurality of flip-flops in the specific block include a plurality of flip-flops, and the specific level shifter responds to a signal input to the specific block and an output signal of a last-stage flip-flop of the specific block. 2. The shift register according to claim 1, further comprising a latch circuit for changing an output. A plurality of flip-flops operating in synchronization with a clock signal; and a level shifter for boosting a clock signal having an amplitude smaller than a driving voltage of the flip-flop and applying the boosted clock signal to each of the flip-flops. In a shift register that transmits an input pulse in synchronization with the clock signal, each of the flip-flops is divided into a plurality of blocks each including at least one flip-flop, and the level shifter is provided for each of the blocks. Wherein at least one of the plurality of level shifters corresponding to a block that does not require the input of the clock signal for transmission of the input pulse at that time is stopped, and the level shifter includes an input switching element. Includes current-driven level shift section Shift register, wherein the door. 4. The level shifter includes an input signal control unit that stops the level shifter by giving a signal of a level cut off by the input switching element as an input signal to the level shift unit. The shift register according to claim 3, wherein 5. The shift register according to claim 3, wherein the level shifter includes a power supply control unit that stops power supply to the level shift unit and stops the level shifter. 6. A multi-stage flip-flop which operates in synchronization with a clock signal, and a level shifter which boosts a clock signal having an amplitude smaller than a driving voltage of the flip-flop and applies the boosted clock signal to each of the flip-flops, In a shift register that transmits an input pulse in synchronization with the clock signal, each of the flip-flops is divided into a plurality of blocks each including at least one flip-flop, and the level shifter is provided for each of the blocks. At least one of the plurality of level shifters corresponding to a block that does not require the input of the clock signal to transmit the input pulse at that time is stopped, and each of the level shifters includes an output stabilizing unit. A shift register, comprising: 7. The level shifter further includes a switch disposed between a clock signal line for transmitting the clock signal and the level shift unit, the switch being opened while the level shifter is stopped. 7. The shift register according to claim 6, wherein: 8. A plurality of pixels arranged in a matrix, a plurality of data signal lines arranged in each row of each pixel, a plurality of scanning signal lines arranged in each column of each pixel, A scanning signal line driving circuit for sequentially applying scanning signals having different timings to the respective scanning signal lines in synchronization with a first clock signal having a predetermined period; and a scanning signal line driving circuit synchronizing with a second clock signal having a predetermined period. A data signal which is sequentially applied and which extracts a data signal to each pixel of a scanning signal line to which the scanning signal is applied from a video signal indicating a display state of each pixel, and outputs the data signal to each data signal line An image display device having a line driving circuit, wherein at least one of the data signal line driving circuit and the scanning signal line driving circuit uses the first or second clock signal as the clock signal. To the image display apparatus characterized by comprising a shift register 7, wherein. 9. The image display device according to claim 8, wherein said data signal line driving circuit, scanning signal line driving circuit and each pixel are formed on the same substrate. 10. The image display device according to claim 8, wherein said data signal line driving circuit, scanning signal line driving circuit and each pixel include a switching element made of a polycrystalline silicon thin film transistor. 11. The data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element manufactured at a process temperature of 600 ° C. or less. Image display device.