JPH0923009A - Method for manufacturing semiconductor device - Google Patents

Abstract

Kind Code: A1 Abstract: It is possible to easily and effectively suppress the rounding and thinning of the end portion of a gate electrode and reduce the size of the gate electrode regardless of lithography, exposure illumination system, resist, mask technology, or mask pattern design technology. Provided is a method for manufacturing a semiconductor device which can be expected to have high reliability. In a method of manufacturing a semiconductor device in which an end of a gate electrode is formed on an element isolation region by using photolithography, a width of a portion corresponding to an end of the gate electrode on a mask in a channel direction is reduced. And a step of exposing using a mask 8 laid out in a size exceeding the width of the gate electrode located on the active region in the channel direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device by a lithographic technique.

[0002]

2. Description of the Related Art In recent years, the miniaturization of MOS transistors forming integrated circuits has progressed, and it is about to enter the so-called deep submicron generation.
Transistors below 0.35 μm are about to be realized. However, in the deep sub-micron generation, since the lithography technique using the i-line (365 nm) stepper that has been conventionally used approaches the limit, for example, as shown in FIG. 7, a corner is rounded at the end of the gate electrode 1, A phenomenon occurs in which the finished shape of the end portion largely recedes from the layout shape of the gate electrode 1 (shown by the dotted line in the figure). In particular, when the end portion of the gate electrode 1 is on the element isolation region 2, the resist becomes thinner than the gate electrode portion on the active region, so that the finished shape of the end portion of the gate electrode 1 becomes thin.

Furthermore, for example, as shown in FIG. 8, when the end of the gate electrode 1 exists near the corner of the active region 3, in addition to the rounded or tapered end of the gate electrode 1, When the finished shape of the corner portion of the active region 3 becomes dull or misaligned, a leak similar to a short circuit may occur between the source and the drain.

While these various problems have been pointed out, attempts have been made to solve the above problems by improving the exposure illumination system, resist, mask technology, mask pattern design technology and the like.

[0005]

[Problems to be Solved by the Invention] For example, in "Science Forum latest edition VLSI process data handbook, March 1994, P121", excimer laser lithography using a KrF laser or ArF laser as a light source, EB ( Electron beam) Direct drawing technology or X
Line lithography techniques have been proposed.

However, such a technique has many unsolved problems, and further research is required before it can be developed into a technique which replaces the i-line stepper.

In the "Nikkei Microdevices April 1992 issue, P22", the sub-half-micron generation i
Techniques for improving the exposure illumination system technology such as the deformation irradiation method, the resist technology related to the new material design of the photosensitizer, or the mask technology such as the phase shift mask have been proposed as the technology to overcome with the line stepper. .

However, such a technique has some problems such as an increase in cost, a decrease in throughput, and a pattern dependence of the effect, so that the problem of rounding or thinning of the end portion of the gate electrode is simple. And it cannot be solved reliably.

In addition, "Proceedings of the 53rd Annual Meeting of the Applied Physics Society of Japan, 16P-L-10, Autumn 1992, P47
7 ”proposes an attempt to realize high resolution by a pattern design technique on a mask. This attempt is to automatically generate a mask pattern so that the light intensity distribution is optimized when a device pattern is given, and this automatic generation is realized by combining a light intensity distribution simulator and an optimization algorithm. FIG. 9A shows an example of a general mask pattern, whereas the mask pattern optimized and designed by the above method is as shown in FIG. 9B.

However, in such a technique, various patterns must be optimized by the above-mentioned program one by one when designing an integrated circuit. In addition, the optimally designed pattern is very complicated, which complicates layout work. Therefore, when it is used for an actual LSI design work, it is imagined that the throughput is significantly reduced, and further measures are required.

In view of the above circumstances, the present invention can easily and effectively suppress the rounding or narrowing of the end portion of the gate electrode without depending on the lithography, the exposure illumination system, the resist, the mask technology, or the mask pattern design technology. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be expected to be miniaturized and have high reliability.

[0012]

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which an end portion of a gate electrode is formed on an element isolation region by lithography. The method is characterized by including the step of exposing using a mask laid out so that the width of the portion corresponding to the end portion in the channel direction exceeds the width of the gate electrode located on the active region in the channel direction.

The widening in the channel direction of the portion corresponding to the end portion of the gate electrode on the mask may be realized by an extended pattern portion formed continuously with the main pattern. In this case, on the active region. The ratio may be 1/10 or more of the width of the positioned gate electrode in the channel direction. Further, the widening in the channel direction of the portion corresponding to the end portion of the gate electrode on the mask may be realized by a dummy pattern portion independent of the main pattern. In this case, the dummy pattern portion is formed by a polygon. In addition, the length parallel to the channel direction may be 1/10 or more of the width of the gate electrode located on the active region in the channel direction.

In the above method, the angle is about 27.
The end of the gate electrode may be formed in the vicinity of the corner of the element isolation region having the corner of 0 °, and
Another gate electrode may be formed near the tip of the end of the gate electrode.

According to the above structure, since the semiconductor device is manufactured by using the mask in which the portion corresponding to the end portion of the gate electrode on the mask is widened in the channel direction, the portion corresponding to the end portion of the gate electrode is manufactured. During exposure, it is possible to secure a necessary light intensity distribution and avoid rounding of the end portion of the gate electrode, and it is possible to prevent a phenomenon that the finish of the end portion largely recedes from the layout shape of the gate electrode. In particular, when the end of the gate electrode is on the element isolation region, the resist becomes thinner than the gate electrode portion on the active region, and the finished shape tends to become thin. Even in such a case, it is possible to prevent the end portion of the gate electrode from becoming thin. Further, it is possible to avoid the problem of short-circuiting when the misalignment occurs in addition to the thinning of the end portion of the gate electrode. Moreover, since a complicated method such as an exposure illumination system, a resist, a mask technique, or a mask pattern design technique is not involved, the manufacturing of the semiconductor device does not become complicated.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device in which an end portion of a gate electrode is formed on an element isolation region by using photolithography. As shown in FIG. 1 and the like, the mask is laid out so that the width in the channel direction of the portion corresponding to the end of the gate electrode on the mask exceeds the width in the channel direction of the gate electrode located on the active region. Is a method including the step of exposing using.

FIG. 1A shows a mask pattern 7 used in the method for manufacturing a semiconductor device of the present invention, and FIG. 1B shows a light intensity distribution by simulation when the mask pattern 7 is used. ing. Figure 1 above
In the pattern 7 of (a), the width of the portion of the mask corresponding to the end of the gate electrode 1 in the channel direction is increased by the main pattern 7
This is realized by the extended pattern portions 7b, 7b formed continuously with a. This extended pattern portion 7b, 7b
Have a square shape and are continuously formed at the corners of the ends of the main pattern 7a on the sides of the square.

FIG. 2A shows another pattern 7 used in the method of manufacturing a semiconductor device according to the present invention.
FIG. 6B shows a light intensity distribution by simulation when the mask pattern 7 is used. Figure 2 above
The pattern 7 of (a) is similar to that of FIG. 1 (a) in that the expanded pattern portion 7c is formed by continuously expanding the width of the main pattern 7a.
It was realized by. This extended pattern portion 7c
Has a rectangular shape and is continuously formed on the side of the end of the main pattern 7a at the side of the square. The length of the side of the extended pattern 7c in the channel direction is 1/10 of the width of the gate electrode 1 located on the active region 3 in the channel direction.
It is bigger than that. Therefore, for example, if the gate length is 0.
If the width is about 5 μm, the width is increased to 0.05 μm or more.

FIG. 3A shows another pattern 7 of the mask used in the method of manufacturing a semiconductor device of the present invention, and FIG. 3B shows the light intensity obtained by simulation when the mask pattern 7 is used. The distribution is shown. FIG. 3 above
The pattern 7 of (a) is similar to FIG. 1 (a), and the extended pattern portions 7d and 7d formed continuously with the main pattern 7a.
It was realized by. This extended pattern portion 7d,
7d has a square shape and is formed continuously at the corners of the end of the main pattern 7a at the corners of the square.

As is clear from the light intensity distributions of FIGS. 1B to 3B, in any of the mask patterns 7 described above, the change in the light intensity of the portion corresponding to the end of the gate electrode 1 is emphasized. Further, it is possible to suppress the rounding of the end portion of the gate electrode 1, and to prevent the phenomenon that the finish of the end portion largely recedes from the layout shape of the gate electrode 1. For comparison, the light intensity distribution according to the conventional pattern is shown in FIG. In these figures, the vertical scale is 0.5 μm and the horizontal scale is 0.1 μm.
m.

4 (a) to 4 (c), the width of the portion of the mask corresponding to the end of the gate electrode 1 in the channel direction is increased in the dummy pattern portion 8 independent of the main pattern 8a.
The mask pattern 8 realized by b (8c, 8d) is shown. The dotted line in the figure shows the finished shape of the gate electrode 1 by each mask pattern 8.

In FIG. 4A, the dummy pattern portions 8b,
8b has a square shape, and one side of the square shape is formed close to the corner of the end of the main pattern 8a. In the same figure (b), the dummy patterns 8c, 8c have a rectangular shape, and the long sides of the rectangular shape are formed close to both edges of the end of the main pattern 8a. In FIG. 7C, the dummy patterns 8d and 8d are formed in a square shape, and one corner of the square shape is formed close to the corner of the end portion of the main pattern 8a.

As described above, the dummy pattern portion 8b (8c, 8c, 8c, 8c) which is independent of the main pattern 8a is used to expand the width of the portion of the mask corresponding to the end portion of the gate electrode in the channel direction.
Also when the mask realized by d) is used, the change in the light intensity of the portion corresponding to the end of the gate electrode 1 is emphasized as in the case of the above-described embodiment, and the rounding of the end of the gate electrode 1 can be suppressed and It is possible to prevent the phenomenon that the finish of the end portion largely recedes from the layout shape of the gate electrode 1.

Of course, the pattern is not limited to the above-mentioned patterns, but the shapes of the extended pattern portion and the dummy pattern portion,
The number, arrangement, or the like may be different from the above pattern example as long as it can suppress the rounding or thinning of the end portion of the gate electrode. Further, the extended pattern and the dummy pattern may be arranged only at one (one side) corner portion of the gate electrode end portion.

Here, the amount of protrusion of the extended pattern portions 7d and 7d from the main pattern 7a and the width of the dummy pattern portions 8b (8c and 8d) in the channel direction are determined by the gate electrode 1 located on the active region 3. The width in the channel direction of 1
A size of / 10 or more was set so as not to affect the finished shape of the peripheral pattern. The width of the gate electrode 1 in the channel direction is limited to 1/10 or more, and even if the extended pattern portion and the dummy pattern portion are formed with a dimension significantly smaller than the limit resolution, mask formation is performed. This is because the cost increase in this case is not expected, and the effect of forming the pattern portion cannot be expected so much.

The commonly used lithography technique is a 5 times reticle (mask) reduction exposure using an i-line stepper, and the i-line lithography technique has reached its limit after the deep submicron generation where the minimum gate length is less than 0.5 μm. Although it is said to be coming, there is a possibility to use it up to the sub-half micron generation. The patterning of the reticle is performed by EB or direct writing with a laser. If the minimum grid on the layout is 0.05 μm, the minimum grid on the reticle is 0.25 μm. The direct writing technology of EB can realize a resolution of about 1/10, but the minimum grid is 0.25 μm.
Making the size smaller does not make much sense because the reticle manufacturing cost increases and the resolution of the i-line stepper cannot keep up. Therefore, when considering mass production using the existing technology, it is ideal that the minimum grid size of the layout is about 0.05 μm or more when laying out the extended pattern part and the dummy pattern part. Is.

The width of the portion of the mask corresponding to the end of the gate electrode in the channel direction has been described to be 1/10 or more of the width of the gate electrode 1 located on the active region 3 in the channel direction. Since this is a dimension on the layout, in the case of the dimension on the mask, the dimension of 5 times is used on the 5 × reticle in the reduction system stepper.

(Embodiment 2) Next, another embodiment of the present invention will be described.

The method of manufacturing the semiconductor device of this embodiment is a method of forming the end portion of the gate electrode 1 in the vicinity of the corner portion of the element isolation region 2 having an angle of 270 °, which has been described in the first embodiment. This is a method using a mask. That is, as shown in FIG. 5A, the width of the portion of the mask corresponding to the end of the gate electrode 1 in the channel direction exceeds the width of the gate electrode located on the active region 3 in the channel direction. A mask laid out in a size is used.

FIG. 3B shows a finished shape when the gate electrode 1 is formed using the above mask. As can be seen from this figure, the curling of the end portion of the gate electrode 1 is suppressed and the phenomenon that the finish of the end portion largely recedes from the layout shape of the gate electrode 1 is prevented, so that the source / drain not shown The risk of short circuit will be avoided.

(Third Embodiment) Next, another embodiment of the present invention will be described.

The method of manufacturing the semiconductor device of the present embodiment is the method of forming another gate electrode 1'in the vicinity of the tip of the end portion of the gate electrode 1 described in the first embodiment or the second embodiment. This is a method using a mask. That is, FIG.
As shown in (a), the width of the portion of the mask corresponding to the end of the gate electrode 1 in the channel direction exceeds the width of the gate electrode 1 located on the active region 3 in the channel direction. Use a laid out mask.

FIG. 3B shows a finished shape when the gate electrode 1 is formed using the above mask. When another gate electrode 1'exists at the end of the gate electrode 1, that is, when an electrode pattern is formed in close contact, the rounding or receding phenomenon of the end of the gate electrode 1 is particularly remarkable between the close contact patterns. However, with the method of this embodiment, even in such a case, as shown in FIG. 6B, the rounding or receding phenomenon of the end portion of the gate electrode 1 is suppressed. . In this embodiment,
Although "1 '" is expressed as a gate electrode for the sake of simplicity, the gate electrode material (for example, polysilicon) may also be used as a wiring, and the usage form of "1'" may be any.

As a result of verifying various patterns, the pattern of FIG. 1 (a) has an advantage that there is little influence of strain on the finished shape of the gate electrode, but the pattern of FIG. In the method of form 3,
There is a strong demand for surely suppressing the thinning of the end portion of the gate electrode, and in order to surely meet this requirement, the corner portion of the main pattern is not expanded, but the main pattern is formed as shown in FIG. It was most effective to use a mask having a pattern that extended the entire edge.

By the way, the layout on the mask for forming holes is described in the four corners of the conventional pattern in "Proceedings of the 54th JSAP Academic Lecture Proceedings 27a-SHF-21, Autumn 1993, P552". It has been proposed to add a supplemental pattern to correct the finished shape and improve the practical resolution limit. However, while the purpose of this proposal is to control the curvature of the corner portion, the present invention uses the above-mentioned FIG.
As can be seen from the mask layout that extends the entire end portion of the main pattern shown in (a), the curvature of the corner portion and distortion are not controlled, but the layout of the end portion is reduced because the finish of the end portion of the gate electrode is reduced. Is different from the above-mentioned proposal in that it is thickened in the channel direction.

In the case of the above-mentioned proposal, in order to obtain a shape close to the layout, it is necessary to optimize the size and arrangement of the auxiliary pattern depending on the hole diameter, the space between the holes, or the step difference of the ground. Although the work is complicated and the throughput is reduced, the present invention suppresses the rounding and thinning of the end portion of the gate electrode, and the curvature of the corner portion is not important. The layout has a considerable margin, does not require strict optimization, and does not complicate the design work or reduce the throughput.

Further, the present invention is a method for manufacturing a semiconductor device in which a gate electrode end portion rides on a thick insulating film for element isolation (for example, a so-called field oxide film formed by the LOCOS method), and is thick. Due to the effect of the step, the resist film becomes thinner on the insulating film than the active region,
The finish of the gate electrode is particularly thin. This phenomenon is essentially independent of resolution and proximity effects,
The present invention will focus on this closely as miniaturization progresses, and the present invention provides a method for manufacturing a semiconductor device in which an end portion of a gate electrode is formed on an element isolation region by using photolithography. Since the mask shown in FIG. 1A and the like is used, the effect can be said to be extremely large.

The semiconductor device is not limited to the MOS transistor, but may be a MIS (Metal Insulator Semiconducer).
tor), SOS (Silicon on Sapphire), SOI (Si
licon on Insulator), TFT (Thin Film Transisto)
It can be applied to all kinds of insulated gate transistors having a gate electrode, such as r), in which the gate electrode is patterned by a lithography process using a mask. Further, it goes without saying that the gate electrode material is not limited to polysilicon.

[0040]

As described above, according to the present invention, in the exposure of the portion corresponding to the end portion of the gate electrode, the necessary light intensity distribution can be secured and the rounding of the end portion of the gate electrode can be avoided. It is possible to prevent the phenomenon that the finish of the end portion largely recedes from the layout shape of the gate electrode.

In particular, when the end of the gate electrode is on the element isolation region, the phenomenon that the resist becomes thinner than the gate electrode portion on the active region and the finished shape becomes thin tends to be seen. If so, even in such a case, it is possible to prevent the end portion of the gate electrode from becoming thin. Further, it is possible to avoid a problem such as a short circuit when the misalignment occurs in addition to the thinning of the end portion of the gate electrode. Moreover, since complicated methods such as an exposure illumination system, a resist, a mask technique, a mask pattern design technique, etc. are not involved, the excellent effects that the manufacturing of the semiconductor device is not complicated are achieved.

[Brief description of drawings]

FIG. 1 (a) is an explanation showing a pattern of a mask used in the method for manufacturing a semiconductor device of the present invention, and FIG. 1 (b) is a light intensity distribution chart by the pattern.

FIG. 2 (a) is an explanation showing another pattern of a mask used in the method for manufacturing a semiconductor device of the present invention, and FIG. 2 (b) is a light intensity distribution chart by the pattern.

FIG. 3A is an explanation showing another pattern of a mask used in the method for manufacturing a semiconductor device of the present invention, and FIG. 3B is a light intensity distribution chart by the pattern.

4A to 4C are explanatory views showing another pattern of a mask and a finished shape of a gate electrode used in the method for manufacturing a semiconductor device of the present invention.

5A is an explanatory diagram showing a positional relationship between a mask pattern and an element isolation region in another embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 5B is the pattern. FIG. 6 is an explanatory view showing a finished shape of a gate electrode according to FIG.

6A is an explanatory diagram showing a positional relationship between a mask pattern and an element isolation region in another embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 6B is the pattern. FIG. 6 is an explanatory view showing a finished shape of a gate electrode according to FIG.

FIG. 7 is an explanatory diagram showing a mask pattern and a finished shape of a gate electrode in a conventional method for manufacturing a semiconductor device.

FIG. 8 is an explanatory diagram showing another example of the finished shape of the mask pattern and the gate electrode in the conventional method for manufacturing a semiconductor device.

9A is an explanatory diagram showing an example of a general mask pattern, and FIG. 9B is an explanatory diagram showing a mask pattern optimized and designed by a conventional method.

FIG. 10 is a light intensity distribution chart using a conventional mask pattern.

[Explanation of symbols]

 1 gate electrode 1'other gate electrode 2 element isolation region 3 active region 7 mask pattern 7a main pattern portion 7b extended pattern portion 7c extended pattern portion 7d extended pattern portion 8 mask pattern 8a main pattern portion 8b dummy pattern portion 8c dummy pattern portion 8d dummy pattern part

Front Page Continuation (72) Inventor Shigeru Kanehara 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Company (72) Inventor Yasuhiro Sato 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Company (72) Inventor Shizuichi Kato 1-3-6 Nakamagome, Ota-ku, Tokyo Within Ricoh Co., Ltd.

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device in which an end portion of a gate electrode is formed on an element isolation region by lithography, wherein a width in a channel direction of a portion of the mask corresponding to the end portion of the gate electrode is active. A method of manufacturing a semiconductor device, comprising: exposing using a mask laid out in a size exceeding a width of a gate electrode located on a region in a channel direction. 2. A widening in a channel direction of a portion corresponding to an end portion of the gate electrode on the mask is realized by an extended pattern portion formed continuously with the main pattern. Of manufacturing a semiconductor device of. 3. The semiconductor device according to claim 1, wherein widening in a channel direction of a portion corresponding to an end portion of the gate electrode on the mask is realized by a dummy pattern portion independent of a main pattern. Production method. 4. The width in the channel direction of the portion corresponding to the end of the gate electrode is set to be 1/10 or more of the width in the channel direction of the gate electrode located on the active region. Item 3. A method for manufacturing a semiconductor device according to item 2. 5. The dummy pattern portion is formed in a polygonal shape, and the length parallel to the channel direction is 1/10 or more of the width of the gate electrode located on the active region in the channel direction. The method for manufacturing a semiconductor device according to claim 3. 6. The method according to claim 1, wherein an end portion of the gate electrode is formed in the vicinity of the corner portion of an element isolation region having a corner portion having an angle of about 270 °. And a method for manufacturing a semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 1, wherein another electrode pattern is formed near the tip of the end of the gate electrode.