JPH0922108A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: A semiconductor device manufacturing method capable of easily and effectively suppressing the blunting of an active region and achieving miniaturization and high reliability without relying on lithography, exposure illumination system, resist, and mask technology. I will provide a. In a method of manufacturing a semiconductor device including a step of forming an active region 1 having a corner portion by lithography, a portion of the mask corresponding to the corner portion of the active region 1 having a size that is not resolved by lithography. It includes the step of exposing using the pattern 7 laid out so as to have the concave portion 7d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method for manufacturing a semiconductor device by a lithography technique.

[0002]

2. Description of the Related Art In recent years, the miniaturization of MOS transistors forming integrated circuits has progressed, and it is about to enter the so-called deep submicron generation.
A transistor whose gate width (channel width) is less than 0.35 μm and less than 1 to 2 μm is about to be realized. In a narrow channel transistor having a gate width of about 1 μm or less, for example, as shown in FIG. 10A, the width of the contact portion (contact hole) 4 for the source and drain electrodes and the active region around the contact portion 4 ( Considering the margin of the diffusion region 1, the width of the active region 1 which becomes the contact portion 4 is larger than the gate width, and the active region 1 has a shape called dogbone. In the figure, 2 represents an element isolation region, and 1, 3 and 4 represent mask patterns.

When a mask is formed in the above layout to form a transistor, the linearity of the gate width dependence on various characteristics of the transistor (eg, maximum transconductance gm _max ) is impaired as the gate width becomes narrower. Is "Proc, IEEE ICMT
S, Vo16, March 1993, P.M. 133 ”. FIG. 11 is a graph shown in this document and showing the gate width dependence on gm _max (when the gate length is 0.9 μm). According to this figure, it can be seen that the linearity is impaired in the region where the gate width is 2 μm or less.

FIG. 10B is an explanatory view showing the actual finished state of the transistor when it is formed by using the mask of the layout shown in FIG. It is considered that the above-mentioned deterioration of linearity is caused by an increase in the effective gate width due to the dull finish of the corner portion of the active region 1. The shorter or narrower the channel, the more the influence on the transistor characteristics. growing. Furthermore, when misalignment occurs, the transistor characteristics further fluctuate, causing variations. As a result of the survey,
When the distance d in 0 (a) is 0.7 μm or more, the influence of the bluntness of the corner portion of the active region 1 (deterioration of the linearity)
Although it was confirmed that there is almost no such problem, securing a distance d of 0.7 μm or more in this way impairs miniaturization, so it cannot be said to be a preferable solution.

Furthermore, after the deep submicron generation,
Since the lithographic technology using the i-line stepper that has been used in the past approaches the limit, there is a phenomenon that the end portion of the gate electrode having a short gate length is rounded or the finished shape is scraped toward the active region side as compared with the specified layout. Occurs. In particular, in the case where a transistor is actually manufactured using the mask having the layout shown in FIG.
As shown in FIG. 3, when the rounding of the end of the gate electrode, the blunting of the active region, and the misalignment occur together, there is a problem that a leak similar to a short circuit occurs between the source and the drain.

While these various problems have been pointed out, attempts have been made to solve the above problems by improving the exposure illumination system, resist, mask technology, mask pattern design technology and the like.

[0007]

[Problems to be Solved by the Invention] For example, in "Science Forum latest edition VLSI process data handbook, March 1994, P121", excimer laser lithography using a KrF laser or ArF laser as a light source, EB ( Electron beam) Direct drawing technology or X
Line lithography techniques have been proposed.

[0008] However, such a technique has many unsolved problems, and further research is needed before it can grow into a technique which replaces the i-line stepper.

In the "Nikkei Microdevices April 1992 issue, P22", the sub-half micron generation i
Techniques for improving the exposure illumination system technology such as the deformation irradiation method, the resist technology related to the new material design of the photosensitizer, or the mask technology such as the phase shift mask have been proposed as the technology to overcome with the line stepper. .

However, such a technique has some problems such as an increase in cost, a decrease in throughput, and a pattern dependence of the effect, and thus the problem of rounding or thinning of the end portion of the gate electrode is simple. And it cannot be solved reliably.

In view of the above circumstances, the present invention can easily and effectively suppress the blunting of the active region without depending on the lithography, exposure illumination system, resist, or mask technology, and is expected to be miniaturized and highly reliable. An object of the present invention is to provide a method of manufacturing a semiconductor device that can be manufactured.

[0012]

According to a method of manufacturing a semiconductor device of the present invention, a method of manufacturing a semiconductor device including a step of forming an active region having a corner portion by lithography corresponds to a corner portion of an active region on a mask. And a step of exposing using a mask laid out so as to have a concave portion or a convex portion having a size that is not resolved by lithography in a portion to be formed, or a dummy pattern portion in a portion corresponding to the vicinity of the corner portion. Characterize.

The method of manufacturing a semiconductor device according to the present invention corresponds to the corner portion of the active region on the mask in the method of manufacturing a semiconductor device including a step of forming an active region having a corner portion having an angle of approximately 270 °. And a step of exposing using a mask laid out so as to have a concave portion having a size not to be resolved by lithography in a portion to be formed, or a dummy pattern portion in a portion corresponding to the vicinity of the corner portion. .

Each side of the concave portion, the convex portion, or the dummy pattern portion may be 0.05 μm or more. Further, even if the end portion of the gate electrode is present on the element isolation region close to the corner portion of the active region, and the distance between the gate electrode and the side of the corner portion adjacent to the gate electrode is 0.7 μm or less. Good. The length of the channel portion in the gate width direction may be 2 μm or less. The gate length of the gate electrode may be 0.5 μm or less.

According to the above structure, it is possible to easily and effectively reduce the bluntness in the finished shape of the active region without adversely affecting the finish of the pattern around the active region.

The end of the gate electrode exists on the element isolation region near the corner of the active region, and the distance between the gate electrode and the side of the corner adjacent to the gate electrode is 0.7 μm or less. In addition, when the length of the channel portion in the gate width direction is set to 2 μm or less, or when the gate length of the gate electrode is set to 0.5 μm or less, the transistor due to the effective increase of the gate width tends to occur particularly remarkably. It is possible to prevent variations in characteristics.

Further, the gate length of the gate electrode is 0.5 μm.
In the following cases, the short portion of the gate electrode is likely to be rounded, and when the corner portion is blunted and misaligned, a leak similar to a short circuit between the source and the drain is generated, According to the present invention, this can be prevented.

When each side of the concave portion, the convex portion, or the dummy pattern portion is 0.05 μm or more, for example,
A 5 times reticle reduction exposure technique using an i-line stepper can be used, and a finished shape close to the layout shape can be realized without increasing cost.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a step of forming an active region having a corner portion by lithography. As shown in FIG. This is a method including a step of exposing using a mask 7 laid out so as to have a concave portion having a size that is not resolved by lithography in a portion corresponding to a corner portion of the region.

FIG. 1A shows a pattern 7 of an active region forming mask used in the method of manufacturing a semiconductor device of the present invention, and FIG. 1B shows a light intensity obtained by simulation when the pattern 7 is used. The distribution is shown. Figure 1 above
In the pattern 7 of (a), a concave portion 7b having a size not to be resolved by lithography is formed continuously with the main pattern 7a in a portion corresponding to a corner portion of the active region 1 on the mask where the angle is 270 °. It is a thing. The concave portion 7b has a square shape, and two sides sandwiching the right-angled portion are parallel to the two sides of the corner portion so that the concave portion 7b is somewhat deeply inserted into the corner portion.

FIG. 2A shows another pattern 7 of the mask used in the method for manufacturing a semiconductor device of the present invention, and FIG. 2B shows the light intensity distribution by simulation when the pattern 7 is used. Is shown. In the pattern 7 shown in FIG. 1A, the angle of the active region 1 on the mask is 270 °.
The concave portion 7c is formed in the main pattern 7 in the portion corresponding to the corner portion of
It is formed continuously from a. The concave portion 7c has a square shape whose side length is longer than that of the concave portion 7b, and the two sides sandwiching the right-angled portion are parallel to the two sides of the corner portion and are somewhat deeply inserted into the corner portion. .

FIG. 2A shows another pattern 7 of the mask used in the method for manufacturing a semiconductor device of the present invention, and FIG. 2B shows the light intensity distribution by simulation when the pattern 7 is used. Is shown. In the pattern 7 shown in FIG. 1A, the angle of the active region 1 on the mask is 270 °.
7d is the main pattern 7 in the portion corresponding to the corner of the
It is formed continuously from a. The concave portion 7c has a rectangular shape, and is deep in the corner portion in the longitudinal direction thereof.

As is clear from the light intensity distributions of FIGS. 1B to 3B, in any of the above patterns 7, the light intensity of the corner portion is sharp and the corner portion of the active region 1 becomes dull. Can be suppressed. For comparison, the light intensity distribution according to the conventional pattern is shown in FIG.

Further, the pattern is not limited to the above-mentioned concave portions 7b, 7c, 7d, and may have any shape, and a mask having a dummy pattern portion independent of the main pattern portion 7a is used. Is also good.

FIG. 4 shows the pattern 7 shown in FIG. 3 when the active region is formed when the end of the gate electrode 3 is formed on the element isolation region 2 adjacent to the corner of the active region 1. It is a figure showing the method using a mask, the figure (a) shows the layout of the above-mentioned pattern 7, etc., and the figure (b) shows the gate electrodes 3 and the gate electrodes 3 actually formed by the masks having the layout. The active region 1 is shown. The dotted line in the figure shows the layout of the conventional mask and the actual finished state of the conventional mask. Reference numeral 4 in the drawing denotes a source and drain electrode contact portion (contact hole).

When the end portion of the gate electrode 3 exists on the element isolation region 2 adjacent to the corner portion of the active region 1, the distance d between the gate electrode 3 and the side of the corner portion adjacent to the gate electrode 3 is set as follows. When the thickness is 0.7 μm or less, variations in transistor characteristics due to an effective increase in the gate width due to rounding and misalignment of the end portions of the gate electrode 3 and a short circuit between the source and drain as shown in FIG. Although it is more likely to occur, by using the mask of the pattern 7 shown in FIG. 3, even if the end portion of the gate electrode 3 is rounded or misaligned, as shown in FIG. Since the bluntness of the corner portion 1 is reduced, it is possible to prevent variations in transistor characteristics and to prevent a short circuit between the source and the drain. Further, the rounding of the end portion of the gate electrode becomes particularly remarkable when the gate length is less than 0.5 μm, and the present invention is particularly effective in the deep submicron generation as described above.

FIG. 5 is a view showing a method of manufacturing a narrow channel transistor having a dogbone-shaped active region 1 by using a mask having a pattern 8 having a recess 8a at the time of forming the active region. The same figure (a)
Shows the layout of the pattern 8 and the like, and FIG.
Shows the gate electrode 3 and the active region 1 actually formed by the masks having the layout. In addition,
The dotted line in the figure shows the layout of the conventional mask and the actual finished state of the conventional mask. Reference numeral 4 in the drawing denotes a source and drain electrode contact portion (contact hole).

The active region 1 has a dogbone shape, the distance d between the gate electrode 3 and the side of the corner portion adjacent thereto is 0.7 μm or less, and the gate length is 0.5 μm.
In the following, when the gate width is set to 2 μm or less, as described in the conventional example, the effective gate width may be increased due to the dull finish of the corner portion of the dogbone-shaped active region 1 or the misalignment. The short and narrow channels have a greater influence on the transistor characteristics. In this case, the problem of short-circuiting between the source and drain due to rounding of the short portion of the gate electrode is not highlighted.

However, as can be seen from FIG. 5B, according to the present invention, the dull finish of the corners of the active region is reduced, and the influence on the transistor characteristics can be minimized. That is, the present invention is particularly effective when the distance d is 0.7 μm or less, and the effect that the effective gate width increase has on the transistor characteristics becomes particularly remarkable when the gate length is 0.5 μm. When the gate width falls below 2 μm, the present invention is thus particularly effective in the deep submicron generation.

FIGS. 6A, 6B, and 6C are explanatory views showing other examples of mask patterns used in the method of the present invention. The pattern 9 shown in FIG. 6 is
The convex portions 9b, 9c, 9d of various shapes are continuously formed on the corner portion of the main pattern portion 9a at an angle of 90 °.
In addition, FIGS. 7A, 7B, and 7C are similar to FIGS.
It is explanatory drawing which showed the actual finished shape corresponding to each of (b) and (c).

FIGS. 8A, 8B and 8C are also explanatory views showing other examples of mask patterns used in the method of the present invention. The pattern 10 shown in FIG.
In this example, dummy pattern parts 10b, 10c and 10d of various shapes are independently formed at corners of the main pattern part 9a at an angle of 90 °. 9 (a), (b),
FIG. 8C is an explanatory diagram showing an actual finished shape corresponding to FIGS. 8A, 8B, and 8C, respectively. The dummy pattern portion may have any shape (not limited to a square or a rectangle), and two or more dummy pattern portions may be formed at each corner portion.

The pattern examples shown in FIGS. 6 and 8 are examples corresponding to the case where the corner portion of the active region 1 is 90 °, and as is clear from FIGS. It can be seen that the dullness in the finish is considerably suppressed. In these figures, the dotted line in the figures shows the conventional pattern and the actual finished shape of this conventional pattern.

The concave portions, convex portions, and dummy pattern portions of the mask described above can be laid out in a considerably wide range of dimensions as long as they are not resolved in the lithography process, and particularly on a grid of 0.05 μm or more. The layout can be easily applied to existing lithography technology.

That is, the existing lithographic technique is a 5 × reticle (mask) reduction exposure by an i-line stepper, and the patterning of this reticle is performed by EB or laser linear drawing. If the minimum grid on the layout is 0.05 μm, the minimum grid on the reticle is 0.25 μm. The possibility of the EB direct writing technology has a resolution of about 1/10, but making the minimum grid smaller than 0.25 μm increases the reticle manufacturing cost and reduces the i-line stepper. It is considered meaningless because the resolution cannot follow.

Therefore, considering the use of the present invention while utilizing the conventional mass production technology, it is effective to set the minimum grid on the layout to about 0.05 μm. However, the present invention is not limited to this, and when the lithography technique is improved and the grid of 0.05 μm or less is used for the layout, the size of the concave-convex portion or the dummy pattern portion is appropriately changed according to the resolution. You can reduce it.

Although the size of the uneven portion or the dummy pattern portion is described as the size on the layout, in the case of the size on the mask, for example, the size is 5 times on the 5 × reticle in the reduction system stepper. Will be used.

As the semiconductor device, a MOS transistor, MIS (Metal Insulator Semiconductor),
SOS (Silicon on Sapphire), SOI (Silicon on Sapphire)
Insulator), TFT (Thin Film Transistor),
Not only various types of insulated gate transistors having a gate electrode and patterning the gate electrode by a lithography process using a mask, but also an active region (impurity diffusion region) such as a bipolar transistor and using a mask A semiconductor device in which the active region (impurity diffusion region) is patterned by a lithography process.

[0039]

As described above, according to the present invention, it is possible to easily and effectively reduce the bluntness in the finished shape of the active region without adversely affecting the finish of the pattern around the active region, and to improve the layout shape. A close finished shape can be realized. As a result, even if misalignment occurs, fluctuations in transistor characteristics can be suppressed, and a short circuit between the source and drain, which tends to occur due to rounding of the end portion of the gate electrode, can be prevented. Further, there is an effect that a finished shape close to the layout shape can be realized without increasing the cost by using the 5 times reticle reduction exposure technique using the i-line stepper.

[Brief description of drawings]

FIG. 1 (a) is an explanation showing a pattern of a mask used in the method for manufacturing a semiconductor device of the present invention, and FIG. 1 (b) is a light intensity distribution chart by the pattern.

FIG. 2 (a) is an explanation showing another pattern of a mask used in the method for manufacturing a semiconductor device of the present invention, and FIG. 2 (b) is a light intensity distribution chart by the pattern.

FIG. 3A is an explanation showing another pattern of a mask used in the method for manufacturing a semiconductor device of the present invention, and FIG. 3B is a light intensity distribution chart by the pattern.

FIG. 4A is an explanatory diagram showing an example of a mask layout in a method for manufacturing a semiconductor device of the present invention, and FIG. 4B is an explanatory diagram showing a finished shape of an active region according to the layout.

5A is an explanatory diagram showing another mask layout example in the method for manufacturing a semiconductor device of the present invention, and FIG. 5B is an explanatory diagram showing a finished shape of an active region by the layout. is there.

6A to 6C are explanatory views showing another mask pattern in the method for manufacturing a semiconductor device of the present invention.

7A to 7C are explanatory views showing the finished shapes of the active region by the mask pattern of FIG. 6, respectively.

FIGS. 8A to 8C are explanatory views showing another mask pattern in the method for manufacturing a semiconductor device of the present invention.

9A to 9C are explanatory views showing the finished shapes of the active region by the mask pattern of FIG.

FIG. 10 is a diagram showing a conventional example, FIG. 10A is an explanatory diagram showing an example of a mask layout in a method of manufacturing a semiconductor device, and FIG. 10B is a finished shape of an active region and the like according to the layout. FIG.

FIG. 11: Maximum transconductance gm of transistor
It is a graph which showed the gate width dependence to _max .

FIG. 12 is a diagram showing a conventional example, FIG. 12A is an explanatory diagram showing an example of a mask layout in a method of manufacturing a semiconductor device, and FIG. 12B is a finished shape of an active region and the like according to the layout. FIG.

FIG. 13 is a light intensity distribution chart by a conventional mask pattern.

[Explanation of symbols]

 1 gate electrode 2 element isolation region 3 active region 4 contact hole 7 mask pattern 7a main pattern part 7b recess 7c recess 7d recess 8 mask pattern 8a recess 9 mask pattern 9a main pattern part 9b dummy pattern part 9c dummy pattern part 9d dummy pattern part 10 mask pattern 10a main pattern portion 10b dummy pattern portion 10c dummy pattern portion 10d dummy pattern portion

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device including a step of forming an active region having a corner portion by lithography, wherein a concave portion having a size that is not resolved by lithography in a portion corresponding to a corner portion of the active region on a mask. Alternatively, a method of manufacturing a semiconductor device, including a step of exposing using a mask laid out so as to have a convex portion or a dummy pattern portion. 2. A method of manufacturing a semiconductor device, which includes a step of forming an active region having a corner portion having an angle of about 270 °, to the extent that a portion corresponding to the corner portion of the active region on a mask is not resolved by lithography. A method of manufacturing a semiconductor device, which comprises the step of exposing using a mask laid out so as to have a concave portion or a dummy pattern portion having a size. 3. The method for manufacturing a semiconductor device according to claim 1, wherein each side of the concave portion, the convex portion, or the dummy pattern portion is 0.05 μm or more. . 4. An end portion of a gate electrode is formed on an element isolation region adjacent to a corner portion of the active region, and a distance between the gate electrode and a side of the corner portion adjacent to the gate electrode is 0.7 μm. The method of manufacturing a semiconductor device according to claim 2 or 3, wherein: 5. The method for manufacturing a semiconductor device according to claim 4, wherein the length of the channel portion in the gate width direction of the active region is 2 μm or less. 6. The gate length of the gate electrode is 0.5 μm
The method of manufacturing a semiconductor device according to claim 4, wherein: