JPH0923219A - Information transmitter / receiver - Google Patents
Information transmitter / receiverInfo
- Publication number
- JPH0923219A JPH0923219A JP7171059A JP17105995A JPH0923219A JP H0923219 A JPH0923219 A JP H0923219A JP 7171059 A JP7171059 A JP 7171059A JP 17105995 A JP17105995 A JP 17105995A JP H0923219 A JPH0923219 A JP H0923219A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- information
- controlled
- response
- transmitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Programmable Controllers (AREA)
- Bidirectional Digital Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
- Small-Scale Networks (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
(57)【要約】
【課題】 本発明は、情報送受信装置に関し、被制御側
から制御側への応答情報の衝突、その誤受信の回避、並
びにそれらの特定を達成することを目的とする。
【解決手段】 送信情報を送信装置の分岐装置2で被制
御装置数分だけ複写分岐して得られた送信情報を複数の
被制御装置へ送信し、識別情報を認識した被制御装置4
−i(iは1,2,・・・,N)から応答情報を送信装
置へ返送する情報送受信装置において、送信情報の識別
情報を抽出して当該識別情報対応の被制御装置からの応
答情報に対する有効信号を次の送信情報が発生されるま
で出力する信号出力装置6と、有効信号に応答して該有
効信号対応の被制御装置からの応答情報のみを前記送信
装置に受信させる受信装置8とを設けたことを特徴とす
る。
The present invention relates to an information transmitting / receiving apparatus, and an object thereof is to achieve collision of response information from a controlled side to a control side, avoidance of erroneous reception thereof, and identification thereof. SOLUTION: The controlled device 4 recognizes the identification information by transmitting the transmitted information to a plurality of controlled devices by copying and branching the transmitted information by a branching device 2 of the transmitting device by the number of controlled devices.
-I (i is 1, 2, ..., N), in the information transmitting / receiving device that returns the response information to the transmitting device, the identification information of the transmission information is extracted, and the response information from the controlled device corresponding to the identification information is extracted. Signal output device 6 which outputs a valid signal for the signal until the next transmission information is generated, and a receiving device 8 which causes the transmission device to receive only response information from the controlled device corresponding to the valid signal in response to the valid signal. And is provided.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、複写分岐されて送
信される送信情報の送信先識別情報を送信先から返送さ
れる応答情報の受信制御に用いる情報送受信装置に関す
る。通信システム等の大規模装置には、その装置が複数
のプリント基板から構成され、その複数のプリント基板
が1つの制御回路によって制御されるように構成された
ものがある。このような構成において、制御回路からの
制御信号が複数のプリント基板へ複写分岐されて送信さ
れる場合には、複数のプリント基板からの応答信号の衝
突、誤受信を回避する必要がある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information transmission / reception apparatus that uses transmission destination identification information of transmission information that is copied and branched and transmitted to control reception of response information returned from the transmission destination. Some large-scale devices such as communication systems are configured such that the device is composed of a plurality of printed circuit boards, and the plurality of printed circuit boards are controlled by one control circuit. In such a configuration, when the control signal from the control circuit is copied and branched to a plurality of printed circuit boards and transmitted, it is necessary to avoid collision and erroneous reception of response signals from the plurality of printed circuit boards.
【0002】[0002]
【従来の技術】従来の前述した情報送受信装置の構成を
図10に示す。100は制御盤で、前述した制御回路に
相当し、102−1、102−2、102−3、102
−4は被制御盤で、前述したプリント基板に相当する。
制御盤100は、信号分岐/集約盤101へ制御信号を
送出する。信号分岐/集約盤101は、被制御盤102
−1、102−2、102−3、102−4へ転送する
制御信号を複写分岐するデータ分岐部104と、被制御
盤102−1、102−2、102−3、102−4か
らの応答信号を受信するオア部106とを有する。2. Description of the Related Art FIG. 10 shows the configuration of a conventional information transmitting / receiving apparatus described above. Reference numeral 100 denotes a control panel, which corresponds to the control circuit described above and includes 102-1, 102-2, 102-3, 102.
-4 is a controlled board and corresponds to the above-mentioned printed circuit board.
The control board 100 sends a control signal to the signal branching / collecting board 101. The signal branching / collecting board 101 is a controlled board 102.
-1, 102-2, 102-3, 102-4, a data branching unit 104 for copying and branching a control signal, and responses from the controlled boards 102-1, 102-2, 102-3, 102-4. An OR unit 106 for receiving a signal.
【0003】制御盤100から被制御盤102−1、1
02−2、102−3、102−4へ制御信号を送信す
るとき、その制御信号は、データ分岐部104において
被制御盤数分の制御信号に複写分岐される。制御信号の
データフォーマットは、アドレス番号と送信データとか
ら成る(図11参照)。1つの制御信号に付加されるア
ドレス番号は、前記被制御盤102−1、102−2、
102−3、102−4のうちのいずれか1つの被制御
盤のアドレス番号である。From the control panel 100 to the controlled panels 102-1, 1
When transmitting control signals to 02-2, 102-3, and 102-4, the control signals are copied and branched into control signals for the number of controlled boards in the data branching unit 104. The data format of the control signal consists of an address number and transmission data (see FIG. 11). The address numbers added to one control signal are the controlled boards 102-1, 102-2,
The address number of any one of the controlled boards 102-3 and 102-4.
【0004】その複写分岐されたデータ信号は、各被制
御盤102−1、102−2、102−3、102−4
へ転送される。データ信号を受信した各被制御盤102
−1、102−2、102−3、102−4は、アドレ
ス信号を解析して自己に割り付けられているアドレス信
号と一致したとき受信したデータ信号が自己宛のもので
あるとしてそのデータ信号を取り込む。The copied and branched data signals are output to the controlled boards 102-1, 102-2, 102-3, 102-4.
Transferred to Each controlled panel 102 that has received the data signal
-1, 102-2, 102-3, and 102-4 analyze the address signal, and when it matches the address signal assigned to the self, the data signal received is regarded as being addressed to the self, and the data signal is take in.
【0005】データ信号を取り込みんだ被制御盤は、制
御盤100に対して応答信号を返す。応答信号は、アド
レス信号及びデータから成る(図11参照)。制御盤1
00は、そのオア部106により前記応答信号を受信す
る。The controlled panel that has received the data signal returns a response signal to the control panel 100. The response signal consists of an address signal and data (see FIG. 11). Control panel 1
00 receives the response signal by the OR unit 106.
【0006】[0006]
【発明が解決しようとする課題】前述のようなデータ信
号の送受信、そして応答信号の送受信が正常に行われて
いるときには、少しも問題は生じない。When the above-mentioned data signal transmission / reception and response signal transmission / reception are normally performed, no problem occurs.
【0007】しかしながら、前記アドレス信号を正しく
解析した第1の被制御盤のほかに、当該アドレス信号を
誤って解析した第2の被制御盤があると、その第1の被
制御盤及び第2の被制御盤から応答信号が、制御盤10
0へ返送されることになるので、オア部106で応答信
号の衝突が発生して誤った応答信号を受信してしまうこ
とになる。このような衝突を回避する手段は、従来装置
にはない。However, if there is a second controlled board that incorrectly analyzes the address signal in addition to the first controlled board that correctly analyzes the address signal, the first controlled board and the second controlled board Response signal from the controlled panel of the control panel 10
Since it is returned to 0, collision of response signals occurs in the OR unit 106, and an erroneous response signal is received. The conventional device has no means for avoiding such a collision.
【0008】又、前述の衝突は、2以上の被制御盤から
同時的に応答信号が返送されてしまう場合に生ずるもの
であるが、2以上の被制御盤から時間を異にして応答信
号が返送されて来るような場合には、前述したような衝
突は発生しない。しかし、正しい応答信号に対して誤応
答した被制御盤からの応答信号が早く、又は遅く返送さ
れて来る場合には、誤った応答信号を早く、又は遅く受
信してしまうことになる。従って、従来の装置において
は、誤った応答信号の受信を回避することができない。The above-mentioned collision occurs when the response signals are simultaneously returned from two or more controlled boards, but the response signals are transmitted from the two or more controlled boards at different times. If it is returned, the above collision does not occur. However, when the response signal from the controlled panel that responds erroneously to the correct response signal is returned early or late, the erroneous response signal is received early or late. Therefore, in the conventional device, reception of an incorrect response signal cannot be avoided.
【0009】又、前述のような衝突や、誤受信が発生し
たときの特定をする手段もない。本発明は、斯かる技術
的課題に鑑みて創作されたもので、被制御側から制御側
への応答信号の衝突、及びその誤受信、並びにそれらの
特定を達成し得る情報送受信装置を提供することをその
目的とする。Further, there is no means for identifying the above-mentioned collision or erroneous reception. The present invention was created in view of such technical problems, and provides an information transmitting / receiving device capable of achieving collision of response signals from a controlled side to a control side, erroneous reception thereof, and their identification. That is the purpose.
【0010】[0010]
【課題を解決するための手段】図1は、請求項1及び請
求項3記載の発明の原理ブロック図を示す。図2は、請
求項2及び請求項4記載の発明の原理ブロック図を示
す。FIG. 1 shows a block diagram of the principle of the invention described in claims 1 and 3. FIG. 2 shows a block diagram of the principle of the invention according to claims 2 and 4.
【0011】請求項1記載の発明は、図1に示すよう
に、被制御装置固有の識別情報を含む送信情報を送信装
置の分岐装置2で被制御装置数分だけ複写分岐して得ら
れた送信情報を複数の被制御装置へ送信し、前記識別情
報を認識した被制御装置4−i(iは1,2,・・・,
N)から応答情報を前記送信装置へ返送する情報送受信
装置において、前記送信情報の識別情報を抽出して当該
識別情報対応の被制御装置からの応答情報に対する有効
信号を次の送信情報が発生されるまで出力する信号出力
装置6と、前記有効信号に応答して該有効信号対応の被
制御装置からの応答情報のみを前記送信装置に受信させ
る受信装置8とを設けて構成したことを特徴とする。According to the first aspect of the present invention, as shown in FIG. 1, transmission information including identification information unique to the controlled device is obtained by copying and branching by the branching device 2 of the transmitting device by the number of controlled devices. Controlled device 4-i (i is 1, 2, ...,) that has transmitted the transmission information to a plurality of controlled devices and has recognized the identification information.
In the information transmission / reception device that returns response information from N) to the transmission device, the identification information of the transmission information is extracted, and the effective signal for the response information from the controlled device corresponding to the identification information is generated as the next transmission information. A signal output device 6 that outputs the response signal to the active signal and a receiving device 8 that causes the transmitting device to receive only the response information from the controlled device corresponding to the valid signal in response to the valid signal. To do.
【0012】請求項2記載の発明は、図2に示すよう
に、被制御装置固有の識別情報を含む送信情報を送信装
置の分岐装置2で被制御装置数分だけ複写分岐して得ら
れた送信情報を複数の被制御装置へ送信し、前記識別情
報を認識した被制御装置4−i(iは1,2,・・・,
N)から応答情報を前記送信装置へ返送する情報送受信
装置において、前記送信情報の識別情報を抽出して当該
識別情報対応の被制御装置からの応答情報に対する有効
信号を、前記識別情報に対応しない被制御装置からの応
答情報に対する無効信号をそれぞれ次の送信情報が発生
されるまで出力する信号出力装置12と、前記有効信号
に応答して該有効信号対応の被制御装置からの応答情報
のみを前記送信装置に受信させる受信装置8と、前記無
効信号及び該無効信号対応の被制御装置からの応答情報
に応答して検出信号を出力する検出装置10とを設けて
構成したことを特徴とする。According to a second aspect of the present invention, as shown in FIG. 2, transmission information including identification information unique to the controlled device is obtained by copying and branching by the branching device 2 of the transmitting device by the number of controlled devices. Controlled device 4-i (i is 1, 2, ...,) that has transmitted the transmission information to a plurality of controlled devices and has recognized the identification information.
In the information transmitting / receiving device that returns response information from N) to the transmitting device, the identification information of the transmission information is extracted, and the valid signal for the response information from the controlled device corresponding to the identification information does not correspond to the identification information. A signal output device 12 that outputs an invalid signal corresponding to the response information from the controlled device until the next transmission information is generated, and only the response information from the controlled device corresponding to the valid signal in response to the valid signal. A receiver 8 for receiving the transmitter and a detector 10 for outputting a detection signal in response to the invalid signal and response information from the controlled device corresponding to the invalid signal are provided. .
【0013】請求項3記載の発明は、図1に示すよう
に、請求項1記載の情報送受信装置において、前記有効
信号は2値信号の低レベル、又は高レベルであり、受信
装置8は、前記被制御装置対応毎の受信回路を有し、該
受信回路の各々は、前記2値信号の有効信号に応答して
該有効信号に対応する被制御装置からの応答情報を取り
込むことを特徴とする。According to a third aspect of the present invention, as shown in FIG. 1, in the information transmitting / receiving apparatus according to the first aspect, the valid signal is a low level or a high level of a binary signal, and the receiving device 8 is A receiving circuit corresponding to each of the controlled devices, each receiving circuit receiving response information from the controlled device corresponding to the valid signal of the binary signal in response to the valid signal of the binary signal. To do.
【0014】請求項4記載の発明は、図2に示すよう
に、請求項2記載の情報送受信装置において、前記有効
信号は2値信号の低レベル、又は高レベルであり、前記
無効信号は2値信号の高レベル、又は低レベルであり、
受信装置は、前記被制御装置対応毎の受信回路を有し、
該受信回路の各々は、前記2値信号の有効信号に応答し
て該有効信号に対応する被制御装置からの応答情報を取
り込み、前記検出装置は、前記被制御装置対応毎の検出
回路を有し、該検出回路の各々は、前記2値信号の無効
信号及び該無効信号対応の被制御装置からの応答情報に
応答して前記検出信号を出力することを特徴とする。According to a fourth aspect of the present invention, as shown in FIG. 2, in the information transmitting / receiving apparatus according to the second aspect, the valid signal is a low level or a high level of a binary signal, and the invalid signal is 2. The high or low level of the value signal,
The receiving device has a receiving circuit for each of the controlled devices,
Each of the receiving circuits receives response information from the controlled device corresponding to the valid signal in response to the valid signal of the binary signal, and the detection device has a detection circuit for each corresponding controlled device. However, each of the detection circuits outputs the detection signal in response to an invalid signal of the binary signal and response information from the controlled device corresponding to the invalid signal.
【0015】[0015]
【作用】請求項1記載の発明によれば、複数の被制御装
置4−1乃至4−Nへ送信情報を複写分岐して送信する
際に、該送信情報の識別情報が信号出力装置で抽出され
て抽出された識別情報対応の被制御装置から返送されて
来る応答情報に対する有効信号が信号出力装置6から次
の送信情報が発生されるまで出力される。According to the present invention, when the transmission information is copied and branched and transmitted to the plurality of controlled devices 4-1 to 4-N, the identification information of the transmission information is extracted by the signal output device. The valid signal corresponding to the response information returned from the controlled device corresponding to the extracted identification information is output from the signal output device 6 until the next transmission information is generated.
【0016】従って、前記送信情報に正しく応答した被
制御装置からの応答情報のみが受信装置8によって受信
され、誤応答した被制御装置から返送されて来る応答情
報は、受信されない。応答情報の衝突を回避することが
できるし、又応答情報の誤受信を回避することができ
る。請求項2記載の発明によれば、複数の被制御装置4
−1乃至4−Nへ送信情報を複写分岐して送信する際
に、該送信情報の識別情報が信号出力装置で抽出されて
抽出された識別情報対応の被制御装置から返送されて来
る応答情報に対する有効信号、及び前記識別情報に対応
しない被制御装置からの応答情報に対する無効受信が信
号出力装置6から次の送信情報が発生されるまで出力さ
れる。Therefore, only the response information from the controlled device that correctly responds to the transmission information is received by the receiving device 8, and the response information returned from the controlled device that has made an incorrect response is not received. Collision of response information can be avoided, and erroneous reception of response information can be avoided. According to the invention described in claim 2, the plurality of controlled devices 4
-1 to 4-N, when the transmission information is copied and branched and transmitted, the identification information of the transmission information is extracted by the signal output device and is returned from the controlled device corresponding to the extracted identification information. Valid signal and invalid reception for response information from the controlled device that does not correspond to the identification information are output until the next transmission information is generated from the signal output device 6.
【0017】従って、前記送信情報に正しく応答した被
制御装置からの応答情報のみが受信装置8によって受信
され、誤応答した被制御装置から返送されて来る応答情
報は、受信されない。応答情報の衝突を回避することが
できるし、又応答情報の誤受信を回避することができ
る。又、前記無効信号及び該無効信号対応の被制御装置
からの応答情報に応答して検出信号が検出装置から出力
される。出力される検出信号は、衝突を生じさせること
なく、衝突を検出し、又該検出を生ぜしめた被制御装置
を特定する。Therefore, only the response information from the controlled device that correctly responds to the transmission information is received by the receiving device 8, and the response information returned from the controlled device that has made an incorrect response is not received. Collision of response information can be avoided, and erroneous reception of response information can be avoided. A detection signal is output from the detection device in response to the invalid signal and the response information from the controlled device corresponding to the invalid signal. The output detection signal detects a collision without causing a collision and also identifies the controlled device that caused the detection.
【0018】請求項3記載の発明は、有効信号を2値信
号とし、前記受信装置を被制御装置毎に受信回路を設
け、該受信回路を2値信号に応答させるように構成して
請求項1と同様の作用を生じさせ、応答情報の衝突、及
び応答情報の誤受信を回避することができる。請求項4
記載の発明は、有効信号及び無効信号を2値信号とし、
前記受信装置を被制御装置毎に受信回路を設け、該受信
回路を2値信号の有効信号に応答させるように構成する
と共に、前記検出装置を前記被制御装置毎に検出回路を
設け、該検出回路の各々を前記2値信号の無効信号及び
該無効信号対応の被制御装置からの応答情報に応答させ
るように構成して請求項2と同様の作用を生じさせ、応
答情報の衝突、及び応答情報の誤受信を回避し、併せて
衝突を生じさせることなく、衝突の検出、及び該検出を
生ぜしめた被制御装置の特定を為し得るようにしたもの
である。According to a third aspect of the present invention, the effective signal is a binary signal, the receiving device is provided with a receiving circuit for each controlled device, and the receiving circuit is configured to respond to the binary signal. It is possible to prevent the collision of the response information and the erroneous reception of the response information by producing the same operation as that of 1. Claim 4
In the invention described, the valid signal and the invalid signal are binary signals,
The receiving device is provided with a receiving circuit for each controlled device, the receiving circuit is configured to respond to a valid signal of a binary signal, and the detecting device is provided with a detecting circuit for each of the controlled devices. Each of the circuits is configured to respond to the invalid signal of the binary signal and the response information from the controlled device corresponding to the invalid signal so as to produce the same operation as that of claim 2, collision of response information, and response It is possible to prevent the erroneous reception of information and also to detect the collision and to identify the controlled device that has caused the detection without causing the collision.
【0019】[0019]
【発明の実施の形態】図3は、請求項1乃至請求項4記
載の発明の一実施例を示す。この実施例は、図10に示
す従来装置に制御信号のアドレス番号を抽出して被制御
盤に割り付けられたアドレス番号であるとき有効信号
を、そうでないとき無効信号を各被制御盤毎に出力する
アドレス抽出部32と、前記有効信号に応答して応答信
号を取り込み、前記無効信号及び該無効信号対応の被制
御盤からの応答信号に応答して検出信号を出力するゲー
ト部34とを設けて構成される。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows an embodiment of the invention described in claims 1 to 4. In this embodiment, when the address number of the control signal is extracted to the conventional device shown in FIG. 10 and the address number is assigned to the controlled panel, a valid signal is output, and otherwise an invalid signal is output for each controlled panel. And an address extracting unit 32 for receiving the response signal in response to the valid signal, and a gate unit 34 for outputting a detection signal in response to the invalid signal and the response signal from the controlled panel corresponding to the invalid signal. Consists of
【0020】アドレス抽出部32は、制御信号からアド
レス番号を抽出する抽出部と、抽出されたアドレス番号
をデコードして次の制御信号が来るまで2値信号を出力
するデコーダとから成るが、図示しない。デコーダの2
値信号の例えば低レベルが前述の有効信号で、高レベル
が前述の無効信号である。図4に示す2値信号*DEC1は
被制御盤102−1に、図4に示す2値信号*DEC2は被
制御盤102−2に、図4に示す2値信号*DEC3は被制
御盤102−3に、図4に示す2値信号*DEC4は被制御
盤102−4に対応している。The address extractor 32 comprises an extractor for extracting an address number from the control signal and a decoder for decoding the extracted address number and outputting a binary signal until the next control signal arrives. do not do. Decoder 2
For example, the low level of the value signal is the valid signal described above, and the high level is the invalid signal described above. The binary signal * DEC1 shown in FIG. 4 is sent to the controlled board 102-1, the binary signal * DEC2 shown in FIG. 4 is sent to the controlled board 102-2, and the binary signal * DEC3 shown in FIG. -3, the binary signal * DEC4 shown in FIG. 4 corresponds to the controlled board 102-4.
【0021】ゲート部34の詳細構成を図4に示す。図
4において、被制御盤毎に、アンド回路40、インバー
タ回路42、ナンド回路44、及びラッチ回路46が設
けられている。但し、それらの参照番号に、−1、−
2、−3、−4を付加して被制御盤102−1、102
−2、102−3、102−4のそれぞれに対応してい
ることを示す。The detailed structure of the gate section 34 is shown in FIG. In FIG. 4, an AND circuit 40, an inverter circuit 42, a NAND circuit 44, and a latch circuit 46 are provided for each controlled panel. However, in those reference numbers, -1,-
Controlled boards 102-1 and 102 by adding 2, -3 and -4
-2, 102-3, 102-4, respectively.
【0022】いずれの被制御盤に対応するアンド回路4
0−1乃至40−4も、当該被制御盤からのデータ及び
インバータ回路42−1乃至42−4を経たデコーダか
らの2値信号を入力されてその出力信号はオア部106
へ供給される。同様に、ナンド回路44−1乃至44−
4は対応する被制御盤からの応答信号及び前記2値信号
を入力されてその出力信号はラッチ回路46−1乃至4
6−4へ供給される。An AND circuit 4 corresponding to any controlled board
0-1 to 40-4 are also input with the data from the controlled panel and the binary signal from the decoder via the inverter circuits 42-1 to 42-4, and the output signal is the OR unit 106.
Supplied to Similarly, the NAND circuits 44-1 to 44-
Reference numeral 4 is a response signal from the corresponding controlled panel and the binary signal, and its output signal is the latch circuits 46-1 to 4-4.
6-4 is supplied.
【0023】図3及び図4において、図3のアドレス抽
出部32は、図1の信号出力装置6及び図2の信号出力
装置12に対応し、データ分岐部104は、図1及び図
2の分岐装置2に対応する。被制御盤102−1乃至1
02−4は、図1及び図2の被制御装置4−1乃至4−
Nに対応し、アンド回路40−1乃至40−4、インバ
ータ42−1乃至42−4及びオア部106は、図1及
び図2の受信装置8に対応する。ナンド回路44−1乃
至44−4、ラッチ回路46−1乃至46−4は、図1
及び図2の検出装置10に対応する。3 and 4, the address extraction unit 32 of FIG. 3 corresponds to the signal output device 6 of FIG. 1 and the signal output device 12 of FIG. 2, and the data branching unit 104 of FIG. 1 and FIG. Corresponds to the branching device 2. Controlled boards 102-1 to 1
02-4 is the controlled devices 4-1 to 4- of FIG. 1 and FIG.
Corresponding to N, the AND circuits 40-1 to 40-4, the inverters 42-1 to 42-4, and the OR unit 106 correspond to the receiving device 8 in FIGS. 1 and 2. The NAND circuits 44-1 to 44-4 and the latch circuits 46-1 to 46-4 are shown in FIG.
2 corresponds to the detection device 10 of FIG.
【0024】以上のように構成される請求項1乃至請求
項4記載の発明実施例の動作を以下に説明する。従来と
同様にして、制御盤100から被制御盤102−1、1
02−2、102−3、102−4に対して制御信号
(その信号フォーマットは図11参照)を送信したとす
る。The operation of the embodiment of the invention according to claims 1 to 4 configured as above will be described below. From the control panel 100 to the controlled panels 102-1 and 1-1,
It is assumed that a control signal (refer to FIG. 11 for the signal format) is transmitted to 02-2, 102-3, and 102-4.
【0025】その送信に際して、前記制御信号のアドレ
ス番号がアドレス抽出部32で抽出判定されて当該アド
レス番号に対応するデコーダの出力端には、低レベルの
2値信号(有効信号)が次の制御信号が発生されるまで
出力され、前記当該アドレス番号に対応しないデコーダ
の出力端には、高レベルの2値信号(無効信号)が次の
制御信号が発生されるまで出力される。At the time of the transmission, the address number of the control signal is extracted and determined by the address extracting unit 32, and a low level binary signal (valid signal) is output to the output terminal of the decoder corresponding to the address number for the next control. A signal is output until the signal is generated, and a high-level binary signal (invalid signal) is output to the output terminal of the decoder that does not correspond to the address number until the next control signal is generated.
【0026】従って、前記制御信号が従来と同様にして
データ分岐部104で複写分岐されて被制御盤102−
1、102−2、102−3、102−4へ供給された
場合に、前記アドレス番号対応の被制御盤からのみ応答
信号が返送されて来たときは、返送されて来た応答信号
は、前記低レベルの2値信号に対応するアンド回路、オ
ア部106を経て正常に受信することができる。Therefore, the control signal is copied and branched by the data branching unit 104 in the same manner as in the conventional case, and the controlled panel 102-
1, 102-2, 102-3, 102-4, when the response signal is returned only from the controlled panel corresponding to the address number, the response signal returned is The signal can be normally received via the AND circuit and the OR unit 106 corresponding to the low level binary signal.
【0027】これに対して、前記制御信号のアドレス番
号が割り付けられている被制御盤が正しい応答信号を返
送して来たのに対し、前記制御信号のアドレス番号が割
り付けられている被制御盤以外の被制御盤が、誤った応
答信号を返送して来たとしても、応答信号を誤って返送
してきた被制御盤に対応するデコーダの2値信号は、高
レベルの2値信号(無効信号)となっており、この高レ
ベルの2値信号に対応するアンド回路は、インバータ回
路によりゲートされない状態に置かれているから、前記
制御信号のアドレス番号が割り付けられている被制御盤
以外の被制御盤から返送されて来た応答信号は、対応す
るアンド回路、オア部106を経て誤って受信されてし
まうことはなくなる。On the other hand, the controlled board to which the address number of the control signal is assigned returns a correct response signal, whereas the controlled board to which the address number of the control signal is assigned. Even if a controlled board other than the above returns an erroneous response signal, the binary signal of the decoder corresponding to the controlled board that erroneously returned the response signal is a high level binary signal (invalid signal). ) And the AND circuit corresponding to this high-level binary signal is placed in a state in which it is not gated by the inverter circuit, and therefore, the AND circuit other than the controlled panel to which the address number of the control signal is assigned is set. The response signal returned from the control panel will not be erroneously received via the corresponding AND circuit and OR unit 106.
【0028】これを具体的に示したのが、図5乃至図9
である。図5は、期待する被制御盤からの正しい応答信
号と、誤った被制御盤からの誤った応答信号とが同時に
受信される場合を示している。例えば、制御信号が被制
御盤102−1に対して送信されて被制御盤102−1
から応答信号が制御盤100へ返送されると同時に、被
制御盤102−4からも誤って応答信号が制御盤100
へ返送されたとする。そうすると、*DEC1は低レベ
ルの2値信号となるが、*DEC4は高レベルの2値信
号となるから、被制御盤102−1からの応答信号はア
ンド回路40−1、オア部106を経て制御盤100へ
転送されるが、被制御盤102−4からの応答信号はア
ンド回路40−4、オア部106を経て制御盤100へ
転送されることはない。従って、制御盤100へ取り込
まれる応答信号の衝突を回避することか゛できる。又、
ナンド回路44−4が信号をラッチ回路46−4へ供給
してラッチ回路46−4にセットし、アラーム信号を発
生するが、ナンド回路44−1は信号をラッチ回路46
−4に供給しないからラッチ回路46−はセットされ
ず、ラッチ回路46−1からはアラーム信号は発生しな
い。誤って応答信号を返送して来ている被制御盤102
−4の特定、即ち衝突発生の原因を衝突を生じさせこと
なく検出することができる。This is specifically shown in FIGS. 5 to 9.
It is. FIG. 5 shows a case where the expected correct response signal from the controlled panel and the incorrect response signal from the incorrect controlled panel are received at the same time. For example, a control signal is transmitted to the controlled panel 102-1 to control the controlled panel 102-1.
At the same time that the response signal is sent back to the control panel 100 from the controlled panel 102-4, the response signal is erroneously sent from the controlled panel
Suppose it was sent back to. Then, * DEC1 becomes a low-level binary signal, but * DEC4 becomes a high-level binary signal. Although transferred to the control panel 100, the response signal from the controlled panel 102-4 is not transferred to the control panel 100 via the AND circuit 40-4 and the OR unit 106. Therefore, it is possible to avoid the collision of the response signals taken into the control panel 100. or,
The NAND circuit 44-4 supplies a signal to the latch circuit 46-4 and sets it in the latch circuit 46-4 to generate an alarm signal, but the NAND circuit 44-1 outputs the signal to the latch circuit 46-4.
-4 is not supplied, the latch circuit 46- is not set and the latch circuit 46-1 does not generate an alarm signal. Controlled panel 102 that has returned a response signal by mistake
-4, that is, the cause of the collision occurrence can be detected without causing a collision.
【0029】又、図6に示すように、期待する被制御盤
からの正しい応答信号の期間内であって該正しい応答信
号よりも遅れて誤った応答信号が返送されて来た場合
も、前述の期待する被制御盤からの正しい応答信号と誤
応答した被制御盤からの誤った応答信号とが同時に返送
されて来た場合と同様に、応答信号の衝突回避、及び衝
突発生原因の検出を行うことができる。Also, as shown in FIG. 6, even when an incorrect response signal is returned within the expected period of the correct response signal from the controlled panel and later than the correct response signal, In the same way as when the expected correct response signal from the controlled panel and the incorrect response signal from the controlled panel that made an erroneous response are returned at the same time, avoid the collision of the response signal and detect the cause of the collision. It can be carried out.
【0030】又、図7に示すように、期待する被制御盤
からの正しい応答信号の期間内であって該正しい応答信
号よりも早く誤った応答信号が返送されて来た場合も、
前述の期待する被制御盤からの正しい応答信号と誤応答
した被制御盤からの誤った応答信号とが同時に返送され
て来た場合と同様に、応答信号の衝突回避、及び衝突発
生原因の検出を行うことができる。Also, as shown in FIG. 7, when an incorrect response signal is returned earlier than the correct response signal within the expected period of the correct response signal from the controlled panel,
Similar to the case where the expected correct response signal from the controlled panel and the incorrect response signal from the controlled panel that made an incorrect response are returned at the same time, the collision avoidance of the response signal and the detection of the cause of the collision occurrence are performed. It can be performed.
【0031】又、図8に示すように、期待する被制御盤
からの正しい応答信号の期間の経過後であって該正しい
応答信号よりも遅れて誤った応答信号が返送されて来た
場合も、前述の期待する被制御盤からの正しい応答信号
と誤応答した被制御盤からの誤った応答信号とが同時に
返送されて来た場合と同様に、応答信号の衝突回避、及
び衝突発生原因の検出を行うことができるし、応答信号
の誤受信も回避することができる。Also, as shown in FIG. 8, when an incorrect response signal is returned after the expected period of the correct response signal from the controlled panel has elapsed and later than the correct response signal. As with the case where the expected correct response signal from the controlled panel and the incorrect response signal from the controlled panel that made an incorrect response are returned at the same time, the collision avoidance of the response signal and the cause of the collision occurrence are Detection can be performed, and erroneous reception of a response signal can be avoided.
【0032】又、図9に示すように、期待する被制御盤
からの正しい応答信号の期間前であって該正しい応答信
号よりも早く誤った応答信号が返送されて来た場合も、
前述の期待する被制御盤からの正しい応答信号と誤応答
した被制御盤からの誤った応答信号とが同時に返送され
て来た場合と同様に、応答信号の衝突回避、及び衝突発
生原因の検出を行うことができるし、応答信号の誤受信
も回避することができる。Further, as shown in FIG. 9, when an incorrect response signal is returned earlier than the expected correct response signal from the controlled panel and earlier than the correct response signal,
Similar to the case where the expected correct response signal from the controlled panel and the incorrect response signal from the controlled panel that made an incorrect response are returned at the same time, the collision avoidance of the response signal and the detection of the cause of the collision occurrence are performed. And it is possible to avoid erroneous reception of the response signal.
【0033】なお、制御信号、応答信号は、ビット並列
でもよい。The control signal and the response signal may be bit-parallel.
【0034】[0034]
【発明の効果】以上説明したように本発明によれば、制
御装置から複写分岐して複数の被制御装置へ制御情報を
送信して前記複数の被制御装置のうちの前記制御情報内
の識別情報対応の被制御装置からの応答情報を該識別情
報を用いて取り込むようにしたので、前記制御情報に誤
応答した被制御装置からの応答情報との衝突や、その誤
受信を除くことができる。誤応答した被制御装置の特定
をすることができる。As described above, according to the present invention, control information is copied and branched, control information is transmitted to a plurality of controlled devices, and the control information is identified among the plurality of controlled devices. Since the response information from the controlled device corresponding to the information is fetched by using the identification information, it is possible to eliminate the collision with the response information from the controlled device that erroneously responds to the control information and the erroneous reception thereof. . It is possible to specify the controlled device that made an erroneous response.
【図1】請求項1及び請求項3記載の発明の原理ブロッ
ク図である。FIG. 1 is a block diagram of the principle of the invention according to claim 1 and claim 3;
【図2】請求項2及び請求項4記載の発明の原理ブロッ
ク図である。FIG. 2 is a principle block diagram of the invention according to claims 2 and 4.
【図3】請求項1乃至請求項4記載の発明の一実施例を
示す図である。FIG. 3 is a diagram showing an embodiment of the invention described in claims 1 to 4.
【図4】図3の実施例で用いるゲート部の具体例を示す
図である。FIG. 4 is a diagram showing a specific example of a gate unit used in the embodiment of FIG.
【図5】図3に示す実施例の第1の動作説明例を示す図
である。5 is a diagram showing a first operation explanation example of the embodiment shown in FIG.
【図6】図3に示す実施例の第2の動作説明例を示す図
である。FIG. 6 is a diagram showing a second operation explanation example of the embodiment shown in FIG. 3;
【図7】図3に示す実施例の第3の動作説明例を示す図
である。FIG. 7 is a diagram showing a third operation explanation example of the embodiment shown in FIG. 3;
【図8】図3に示す実施例の第4の動作説明例を示す図
である。FIG. 8 is a diagram showing a fourth operation explanation example of the embodiment shown in FIG. 3;
【図9】図3に示す実施例の第5の動作説明例を示す図
である。FIG. 9 is a diagram showing a fifth operation explanation example of the embodiment shown in FIG. 3;
【図10】従来の情報送受信装置の構成例を示す図であ
る。FIG. 10 is a diagram showing a configuration example of a conventional information transmitting / receiving apparatus.
【図11】制御信号及び応答信号の信号フォーマットを
示す図である。FIG. 11 is a diagram showing a signal format of a control signal and a response signal.
2 分岐装置 4−1 被制御装置 4−N 被制御装置 6 信号出力装置 8 受信装置 10 検出装置 32 アドレス抽出部 34 ゲート部 40−1 アンド回路 40−4 アンド回路 42−1 インバータ回路 42−4 インバータ回路 44−1 ナンド回路 44−4 ナンド回路 46−1 ラッチ回路 46−4 ラッチ回路 102−1 被制御盤 102−4 被制御盤 104 データ分岐部 106 オア部 2 Branching device 4-1 Controlled device 4-N Controlled device 6 Signal output device 8 Reception device 10 Detection device 32 Address extraction unit 34 Gate unit 40-1 AND circuit 40-4 AND circuit 42-1 Inverter circuit 42-4 Inverter circuit 44-1 NAND circuit 44-4 NAND circuit 46-1 Latch circuit 46-4 Latch circuit 102-1 Controlled board 102-4 Controlled board 104 Data branching section 106 OR section
Claims (4)
報を送信装置の分岐装置で被制御装置数分だけ複写分岐
して得られた送信情報を複数の被制御装置へ送信し、前
記識別情報を認識した被制御装置から応答情報を前記送
信装置へ返送する情報送受信装置において、 前記送信情報の識別情報を抽出して当該識別情報対応の
被制御装置からの応答情報に対する有効信号を次の送信
情報が発生されるまで出力する信号出力装置と、 前記有効信号に応答して該有効信号対応の被制御装置か
らの応答情報のみを前記送信装置に受信させる受信装置
とを設けて構成したことを特徴とする情報送受信装置。1. Transmission information including identification information unique to a controlled device is copied and branched by a branching device of a transmitting device by the number of controlled devices, and the transmission information is transmitted to a plurality of controlled devices, and the identification information is transmitted. In an information transmitting / receiving device that returns response information from the controlled device that has recognized the information to the transmitting device, the identification information of the transmission information is extracted, and the effective signal for the response information from the controlled device corresponding to the identification information is A signal output device that outputs until transmission information is generated, and a receiving device that responds to the valid signal and that causes the transmitting device to receive only response information from the controlled device corresponding to the valid signal. An information transmitting and receiving device characterized by.
報を送信装置の分岐装置で被制御装置数分だけ複写分岐
して得られた送信情報を複数の被制御装置へ送信し、前
記識別情報を認識した被制御装置から応答情報を前記送
信装置へ返送する情報送受信装置において、 前記送信情報の識別情報を抽出して当該識別情報対応の
被制御装置からの応答情報に対する有効信号を、前記識
別情報に対応しない被制御装置からの応答情報に対する
無効信号をそれぞれ次の送信情報が発生されるまで出力
する信号出力装置と、 前記有効信号に応答して該有効信号対応の被制御装置か
らの応答情報のみを前記送信装置に受信させる受信装置
と、 前記無効信号及び該無効信号対応の被制御装置からの応
答情報に応答して検出信号を出力する検出装置とを設け
て構成したことを特徴とする情報送受信装置。2. The transmission information including identification information unique to the controlled device is copied and branched by a branching device of the transmitting device by the number of controlled devices, and the transmission information is transmitted to a plurality of controlled devices, and the identification information is transmitted. In an information transmission / reception device that returns response information from the controlled device that has recognized information to the transmission device, the identification information of the transmission information is extracted, and a valid signal for the response information from the controlled device corresponding to the identification information, A signal output device that outputs an invalid signal for response information from the controlled device that does not correspond to the identification information until the next transmission information is generated, and a controlled device from the controlled device that supports the valid signal in response to the valid signal. A receiving device that causes the transmitting device to receive only response information, and a detection device that outputs a detection signal in response to the invalid signal and the response information from the controlled device corresponding to the invalid signal are provided. An information transmitting and receiving device characterized by being configured.
て、 前記有効信号は2値信号の低レベル、又は高レベルであ
り、受信装置は、前記被制御装置対応毎の受信回路を有
し、該受信回路の各々は、前記2値信号の有効信号に応
答して該有効信号に対応する被制御装置からの応答情報
を取り込むことを特徴とする情報送受信装置。3. The information transmitting / receiving device according to claim 1, wherein the valid signal is a low level or a high level of a binary signal, and the receiving device has a receiving circuit for each of the controlled devices, An information transmitting / receiving device, wherein each of the receiving circuits takes in response information from the controlled device corresponding to the valid signal of the binary signal in response to the valid signal of the binary signal.
て、 前記有効信号は2値信号の低レベル、又は高レベルであ
り、前記無効信号は2値信号の高レベル、又は低レベル
であり、受信装置は、前記被制御装置対応毎の受信回路
を有し、該受信回路の各々は、前記2値信号の有効信号
に応答して該有効信号に対応する被制御装置からの応答
情報を取り込み、前記検出装置は、前記被制御装置対応
毎の検出回路を有し、該検出回路の各々は、前記2値信
号の無効信号及び該無効信号対応の被制御装置からの応
答情報に応答して前記検出信号を出力することを特徴と
する情報送受信装置。4. The information transmitting / receiving apparatus according to claim 2, wherein the valid signal is a binary signal low level or high level, and the invalid signal is a binary signal high level or low level. The device has a receiving circuit for each controlled device, and each of the receiving circuits receives response information from the controlled device corresponding to the valid signal in response to the valid signal of the binary signal, The detection device has a detection circuit corresponding to each controlled device, and each of the detection circuits responds to an invalid signal of the binary signal and response information from the controlled device corresponding to the invalid signal. An information transmitting / receiving apparatus, which outputs a detection signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17105995A JP3174246B2 (en) | 1995-07-06 | 1995-07-06 | Monitoring device and information transmitting / receiving device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17105995A JP3174246B2 (en) | 1995-07-06 | 1995-07-06 | Monitoring device and information transmitting / receiving device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0923219A true JPH0923219A (en) | 1997-01-21 |
| JP3174246B2 JP3174246B2 (en) | 2001-06-11 |
Family
ID=15916310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17105995A Expired - Fee Related JP3174246B2 (en) | 1995-07-06 | 1995-07-06 | Monitoring device and information transmitting / receiving device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3174246B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003018237A (en) * | 2001-06-29 | 2003-01-17 | Maspro Denkoh Corp | Data distribution device and noise elimination device |
-
1995
- 1995-07-06 JP JP17105995A patent/JP3174246B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003018237A (en) * | 2001-06-29 | 2003-01-17 | Maspro Denkoh Corp | Data distribution device and noise elimination device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3174246B2 (en) | 2001-06-11 |
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