JPH0923250A - CN ratio detection means for digital demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of an LSI and to improve the calculation accuracy of the C/N by the C/N detection means of the digital demodulation circuit. SOLUTION: A square mean value calculation circuit 40 calculates a value K1 *(C+N) proportional to a sum (C+N) between a carrier power C and a noise power N. An absolute value mean calculation circuit 30 calculates a carrier amplitude Vc(=K2 *√C) and the calculated values are stored in a register file 4. Then a microprocessor 5 reads the calculated values stored in the register file 4 and the C/N is calculated from (K2 *√C)<2> /K1 *(C+N)*(K2 <2> / K1 )-(K2 *√C)<2> ). The calculation of the sum of the carrier power C and the noise power N by the square mean value calculation circuit 40 and the calculation of the carrier amplitude by the absolute value mean calculation circuit 30 are processed in an LSI and the C/N is calculated by the microprocessor 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CN ratio detecting means of a digital demodulation circuit for demodulating a digital modulation signal.

[0002]

2. Description of the Related Art Recently, digital broadcasting has been considered for terrestrial broadcasting and satellite broadcasting. Digital modulation uses digital modulation. This digital modulation signal demodulation circuit is an LSI
It is possible to realize the digital demodulation circuit at low cost by implementing.

It is considered that the CN ratio detecting means of the digital demodulation circuit is used for monitoring the receiving condition of digital broadcasting and appropriately adjusting the direction of the antenna in the arrival direction of the radio wave.

FIG. 5 shows CN ratio detecting means of a conventional digital demodulation circuit. The carrier wave reproducing circuit 1 is composed of a complex multiplier 2 and a reproduced carrier wave 3. The I and Q digital input signals and the reproduced carrier wave 3 are input to the complex multiplier 2, and the I and Q demodulated output signals are output from the complex multiplier 2.

The Q demodulation output signal is a carrier signal plus noise. The Q demodulated output signal is input to the carrier power calculation circuit 10 and the noise power calculation circuit 20. These carrier power calculation circuit 10 and noise power calculation circuit 2
0 operates at the baud rate clock rate of the Q demodulated output signal. In the carrier power calculation circuit 10, the absolute value of the Q demodulation output signal is input to the integration circuit 12 and then squared by the square calculation circuit 13. The number M of integration of the absolute value of the Q demodulation output signal by the integration circuit 12 is constant. It is set to the number of times, and the number M of times of integration is usually controlled by a counter.

In the noise power calculation circuit 20, the Q demodulated output signal is squared in the square calculation circuit 21 and integrated in the integration circuit 22, and the carrier power calculation circuit 1 is calculated from the output value of the integration circuit 22.
The output value of 0 is subtracted, and the number of times the square value of the Q demodulation output signal by the integrating circuit 22 is set to a fixed number M, like the integrating circuit 12.

The carrier power value calculated by the carrier power calculation circuit 10 and the noise power value calculated by the noise power calculation circuit 20 are temporarily stored in the register file 4.

The microprocessor 5 reads the data of the carrier power value C and the noise power value N in the register file 4 when necessary and, for example, when expressing the CN ratio by a decibel value, 10 * log (C / N) is used. The CN ratio data is calculated as a decibel value by arithmetic processing.

[0009]

DISCLOSURE OF THE INVENTION The conventional CN described above
In the ratio detection means, since the carrier signal power and the noise power are all calculated inside the LSI, it is necessary to configure the multiplier 13 and the subtractor 23 with the LSI, which results in a large circuit scale of the LSI. There is a point. Furthermore, in order to increase the CN ratio detection accuracy, it is necessary to increase the number of bits of the output data of the integrating circuits 12 and 22, but if the number of bits is increased, the processing time of the squaring calculation circuit 13 becomes longer, and the carrier power is increased. There is a problem that the processing speed of the calculation circuit 10 becomes slow, the baud rate clock speed of the demodulation circuit is limited, and the speed cannot be increased.

The present invention has been made in view of the above points, and eliminates the drawbacks of the above-described conventional example, and converts the average value processing, which requires high-speed repetitive calculation, into an LSI, and the calculation processing after the average value processing is averaged. The microprocessor calculates the CN ratio based on the data obtained by the value processing, which reduces the circuit scale of the LSI and improves the calculation accuracy of the CN ratio, and the baud rate clock speed of the demodulation circuit. It aims to be able to cope with the speedup of.

[0011]

In order to achieve this object, in the CN ratio detecting means of the present invention, the I, Q digital input signal and the reproduced carrier are input to a complex multiplier to output the I, Q demodulated output signal. Carrier wave reproducing means and digitalized I
Alternatively, a mean square value calculating means for accumulating the squared operation output of the amplitude value of the Q demodulated output signal a fixed number of times, and an absolute value average calculation for accumulating the absolute value of the digitized amplitude value of the I or Q demodulated output signal a fixed number of times. Means, storage means for temporarily storing the mean square value data by the mean square value calculation means and the mean absolute value data by the mean absolute value calculation means, respectively, and mean square value data and mean absolute value data from the storage means Respectively into the microprocessor, and the microprocessor is configured to calculate the CN ratio of the I and Q signals.

[0012]

The root mean square value calculating means calculates the added value A (= C + N) of the carrier power C and the noise power N, the absolute value average calculating means calculates the carrier wave amplitude Vc, and each calculated value is stored in the register file. Retained. Then, the microprocessor reads out the calculated value held in the register file, and from K * Vc ² / (A−K * Vc ² ) (where K is a constant and expressed as K * Vc ² = C) Calculate the CN ratio. Here, the carrier power C by the root mean square calculation means
Since calculation of the added value A of the noise power N and calculation of the carrier amplitude by the absolute value average calculation means requires high-speed calculation processing, the calculation processing is performed in the LSI, and K * Vc ² / (A−K *) V
Since the calculation of the CN ratio by c ² ) does not require repeated calculation at the baud rate clock speed of the demodulation circuit, it is calculated by the microprocessor.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a CN ratio detecting apparatus according to a first embodiment of the present invention. The same parts as those of the embodiment of FIG. The orthogonal baseband I and Q digital input signals and the reproduced carrier wave 3 reproduced by the carrier wave reproduction circuit 1 are input to the complex multiplier 2, and the I and Q demodulated output signals from the complex multiplier 2 are used as the baud rate clock. It is output in synchronization. For example, in the QPSK modulation signal, the Q (or I) demodulation output signal is expressed as a signal of an amplitude voltage Vc + Vn in which the noise amplitude voltage Vn is superimposed on the carrier amplitude voltage Vc (= constant).

In the mean square value calculation circuit 40, the input Q
In the (or I) demodulation output signal, (Vc + Vn) ² is calculated at high speed in synchronization with the baud rate clock, and the squared value is continuously M in the integrating circuit 42 in synchronization with the baud rate clock.
It is added twice. The number of additions M is controlled by a counter, but if M is made sufficiently large, the average value ΣVn of the noise voltage Vn can be approximated to zero, so Σ (Vc * Vn) ≈0.
And can be expressed as Σ (Vc + Vn) ² ≈M * Vc ² + ΣVn ² . That is, in the root mean square calculation circuit 40, the noise power N (proportional to the average value of Vn ² and expressed as ΣVn ² / M) is added to the carrier power C (proportional to the average value of Vc ² ) to obtain the total power C + N. A proportional value K ₁ * (C + N) is obtained. In this way, the root mean square value calculation circuit 40 performs high-speed calculation in synchronization with the baud rate clock.

In the absolute value average calculation circuit 30, the input Q
An absolute value circuit 31 calculates an absolute value | Vc + Vn | of the (or I) demodulated output signal, and the absolute value is continuously added M times in the integrating circuit 32 in synchronization with the baud rate clock. Under the condition that M is sufficiently large, the noise level is smaller than the carrier level, and Vc> 0 and Vc + Vn ≧ 0 or Vc <0 and Vc + Vn ≦ 0 are approximately satisfied, M * | Vc + Vn | ≈ It can be expressed as M * | Vc |. That is, in the absolute value average calculation circuit 30, the carrier power C
A value K ₂ * √C proportional to the square root of is obtained. In this way, the absolute value average calculation circuit 30 performs high-speed calculation in synchronization with the baud rate clock.

The calculation results calculated by the square mean value calculation circuit 40 and the absolute value mean calculation circuit 30 are temporarily held in the register file 4. Then, the microprocessor 5 reads out the calculation result held in the register file 4 when necessary, and calculates (K ₂ * √C) ² / (K ₁
* (C + N) * ( K 2 2 / K 1) - (K 2 * √C) 2) from calculating a CN ratio.

Here, the root mean square calculation circuit 40 for calculating the total power C + N obtained by adding the noise power N to the carrier power C
And the absolute value average calculating circuit 30 for calculating a value proportional to the square root of the carrier power C is placed in the LSI because high-speed arithmetic processing synchronized with the baud rate clock is required, and (K ₂ * √)
_{^{C) 2 / (K 1 *}} (C + N) * (K 2 2 / K 1) - (K 2 * √
The calculation of the C / N ratio by the calculation of C) ² ) can be performed by the microprocessor 5 because it is possible to perform the calculation processing asynchronous with the baud rate clock in the LSI. Here, the integrating circuit 3
In the counting process of the number of integrations M by 2, 42, for example, the microprocessor 5 issues a start signal to the CN ratio detection circuit to start the calculation process, and the register of the counter in the integration circuits 32, 42 is reset in accordance with this start signal. Then, the calculation by the integrating circuits 32 and 42 is started. Then, when the count value reaches M, a ready signal indicating that the integrating operation is completed is output. The microprocessor 5 confirms that this ready signal is output and reads out the calculation result held in the register file 4.

In the first embodiment of the present invention described above, only the root mean square value calculation circuit 40 and the absolute value mean value calculation circuit 30 which require high-speed arithmetic processing in synchronization with the baud rate clock are LS.
The circuit scale of the LSI can be reduced by using I and allowing the microprocessor 5 to perform calculations that do not require high-speed arithmetic processing. Further, the accuracy of the calculation of the CN ratio can be increased by increasing the number of additions M and increasing the number of bits in the integrating circuits 32 and 42. Therefore, the CN ratio is directly calculated from the highly accurate output data of the integrating circuits 32 and 42. In this method, the accuracy of calculating the CN ratio does not deteriorate. Further, since the calculation process for squaring the output of the integration circuit 32 having a large number of bits (the calculation process by the square calculation circuit 13 in FIG. 5) is not necessary, the clock can be speeded up.

FIG. 2 shows a CN ratio detector according to the second embodiment of the present invention. In the embodiment of FIG. 2, the same parts as those of the embodiment of FIG. In the embodiment shown in FIG. 1, carrier reproduction is realized in the baseband, and the orthogonal baseband I and Q digital input signals and the baseband reproduced carrier 3 are complex multiplications which are frequency conversion means in the baseband. The complex multiplier 2 outputs baseband I and Q demodulated output signals in synchronization with the baud rate clock. On the other hand, in the carrier reproduction according to the embodiment of FIG. 2, a digital modulated signal having a center frequency in the IF frequency band and a reproduced carrier 53 in the IF frequency band
(Normally composed of a voltage controlled oscillator, the oscillation frequency of this voltage controlled oscillator is the same frequency as the center frequency of the digital modulation signal) is input to the quadrature detector 52, and the baseband I and Q analog output signals are output. Is output. This I,
Q The analog output signal is A synchronized with the baud rate clock.
The absolute value average calculation circuit 30 and the root mean square value calculation circuit 4 are converted into digital signals by the D converter 54 and digitized as I demodulation output signals or Q demodulation output signals.
0 is provided. The other configuration is the same as that of FIG.

In the second embodiment of the present invention, as in the embodiment of FIG. 1, only the root mean square value calculating circuit 40 and the absolute value average value calculating circuit 30 which require high-speed arithmetic processing synchronized with the baud rate clock are constructed by LSI. However, the circuit scale of the LSI can be reduced by causing the microprocessor 5 to perform calculations that do not require high-speed arithmetic processing. Further, the accuracy of the calculation of the CN ratio can be increased by increasing the number of additions M and increasing the number of bits in the integrating circuits 32 and 42. Therefore, the CN ratio is directly calculated from the highly accurate output data of the integrating circuits 32 and 42. In this method, the accuracy of calculating the CN ratio does not deteriorate.
Further, since the calculation process for squaring the output of the integration circuit 32 having a large number of bits (the calculation process by the square calculation circuit 13 in FIG. 5) is unnecessary, the baud rate clock can be made high speed.

FIG. 3 shows a CN ratio detecting apparatus according to a third embodiment of the present invention. In the embodiment of FIG. 3, the same parts as those of the embodiment of FIG. The orthogonal baseband I and Q digital input signals and the reproduced carrier wave 3 reproduced by the carrier wave reproduction circuit 1 are inputted to the complex multiplier 2.
The I / Q demodulation output signal is output from the complex multiplier 2 in synchronization with the baud rate clock, but the amplitude level of the I / Q demodulation output signal is set to the code point of the digital modulation signal by AGC control (not shown). It is controlled to the corresponding predetermined amplitude level. For example, in a QPSK modulation signal, when the Q (or I) demodulation output signal is expressed as a signal of an amplitude voltage Vc + Vn in which a noise amplitude voltage Vn is superimposed on a carrier amplitude voltage Vc (= constant), Vc is a predetermined amplitude level corresponding to a code point. Becomes

In the mean square value calculation circuit 40, the input Q
In the (or I) demodulation output signal, (Vc + Vn) ² is calculated at high speed in synchronization with the baud rate clock, and the squared value is continuously M in the integrating circuit 42 in synchronization with the baud rate clock.
It is added twice. The number of additions M is controlled by a counter, but if M is made sufficiently large, the average value ΣVn of the noise voltage Vn can be approximated to zero, so Σ (Vc * Vn) ≈0.
And can be expressed as Σ (Vc + Vn) ² ≈M * Vc ² + ΣVn ² . That is, in the root mean square calculation circuit 40, the noise power N (proportional to the average value of Vn ² and expressed as ΣVn ² / M) is added to the carrier power C (proportional to the average value of Vc ² ) to obtain the total power C + N. A proportional value K ₁ * (C + N) is obtained. In this way, the root mean square calculation circuit 40 performs high-speed calculation in synchronization with the baud rate clock.

By the AGC control, the amplitude levels of the I and Q demodulated output signals are controlled to a predetermined amplitude level Vc corresponding to the code points of the digital modulation signal and are stable. Therefore, FIG.
A value K ₂ * √C proportional to the square root of the carrier power C in the absolute value average data obtained by the absolute value average calculating circuit 30 is a predetermined amplitude level corresponding to the code point without being obtained by the absolute value average calculating circuit 30. It can be calculated directly from Vc and the number of additions M.

The calculation result K ₁ * (C + N) calculated by the root mean square calculation circuit 40 is temporarily stored in the register file 4. Then, in the microprocessor 5, the calculation result K ₁ held in the register file 4 when needed
* (C + N) is read out, and the value of K ₂ * √C whose value has already been calculated is used to calculate (K ₂ * √C) ² /
_{(K 1 * (C + N} ) * (K 2 2 / K 1) - (K 2 * √C) 2)
Calculate the CN ratio from

Here, the noise power N is added to the carrier power C.
Root mean square value calculation circuit 40 for calculating the total power C + N
Requires high-speed arithmetic processing synchronized with the baud rate clock
Therefore, it is placed in the LSI, and (K_Two* √C)^Two/ (K₁* (C
+ N) * (K_Two ^Two/ K₁)-(K _Two* √C)^Two)
The calculation of the CN ratio is different from the baud rate clock in the LSI.
Since it can be done by synchronous arithmetic processing, the microprocessor 5
Is calculated. Here, the number of integrations M by the integration circuit 42
The counting process is performed, for example, from the microprocessor 5 to the CN.
A start signal is issued to the ratio detection circuit to start arithmetic processing.
In accordance with this start signal, the cow in the integrating circuit 42
Register is reset, and the totalizing circuit 42
Calculation is started. When the count value reaches M, the product
A ready signal indicating that the arithmetic operation is completed is output.
In the microprocessor 5, this ready signal is output
Make sure that it is stored in register file 4
I will read out the calculation results.

In the third embodiment of the present invention described above, the absolute value average calculation circuit 30 is unnecessary, and only the root mean square value calculation circuit 40, which requires high-speed calculation processing in synchronization with the baud rate clock, is composed of an LSI, and high-speed calculation is performed. By causing the microprocessor 5 to perform calculations that do not require processing, the circuit scale of the LSI can be reduced. Further, the CN ratio is calculated directly from the output data of the integrating circuit 42, and the calculation accuracy of the CN ratio can be increased as the number of additions M is increased and the number of bits in the integrating circuit 42 is increased. Does not reduce the calculation accuracy. Further, since the arithmetic processing for squaring the output of the integrating circuit 32 having a large number of bits is unnecessary, the clock can be speeded up.

FIG. 4 shows a CN ratio detecting apparatus according to a fourth embodiment of the present invention. In the embodiment of FIG. 4, the same parts as those of the embodiment of FIG. In the embodiment of FIG. 1, the integrating circuit 32 of the absolute value average calculating circuit 30 and the integrating circuit 42 of the root mean square calculating circuit 40 are separately configured, but in the embodiment of FIG. 4, only one integrating circuit 42 is used. The point is different. In the embodiment of FIG. 4, the square operation circuit 41 has a larger number of output bits (11 bits) than the number of input bits (6 bits, for example), but the absolute value circuit 31 has the same number of output bits as the number of input bits. . Therefore, the number of output bits of the squaring calculation circuit 41 is larger, so that the common integrating circuit has the same number of bits as the integrating circuit 42 of the square mean value calculating circuit 40. . In the integrating circuit 42, for example, the absolute value average is calculated for odd-numbered clocks and the root mean square value is calculated for even-numbered clocks, so that the absolute value mean and the root mean square value are calculated at the baud rate clock speed. Switching control is performed by the switches 43 and 44 so that the integration process is performed by alternately dividing the time.

In the fourth embodiment of the present invention described above, in addition to the effect of the embodiment of FIG.
By effectively lowering the processing speed for calculating the absolute value average and calculating the root mean square value, the circuit scale of the LSI can be further reduced compared to FIG.

In each of the above-described embodiments of the present invention, the integration circuit 3 of the mean square value calculation circuit 40 and the absolute value average calculation circuit 30.
Although the processing speeds of 2 and 42 have been described as the baud rate clock speed, it is not always necessary to operate the integrating circuits 32 and 42 at the baud rate clock speed, and the processing speed may be reduced to an integer fraction of the baud rate clock speed. .
By lowering the processing speed of the integrating circuits 32 and 42 in this manner, it becomes possible to cause the integrating circuits 32 and 42 having a large number of bits to function even if the baud rate clock speed is increased.

In the fourth embodiment of the present invention, the integrating circuit 42 for calculating the root mean square value and the absolute value average is used by alternately dividing the time by the baud rate clock speed. It is not necessary to alternately use time division at the baud rate clock speed, and in the calculation of the root mean square value, the integrating circuit 42 is operated continuously M times at the baud rate clock speed to perform integration processing, and when the calculation of the root mean square value is completed, Alternatively, the method of calculating the absolute value average may be performed by causing the integrating circuit 42 to work continuously M times at the baud rate clock speed to perform the integrating process.

In each of the embodiments of the present invention described above, the QPSK modulation signal is described as an example of the digital modulation signal, but the QPSK modulation signal is not necessarily required.
It goes without saying that a digital modulation signal such as QAM or MSK other than the QPSK modulation signal may be used.

[0032]

As described above, the present invention has the following effects. (1) By configuring only the root mean square value calculation circuit 40 and the absolute value average calculation circuit 30 that require high-speed arithmetic processing in synchronization with the baud rate clock with an LSI, and the microprocessor 5 performs calculations that do not require high-speed arithmetic processing. , LS
The circuit scale of I can be reduced. (2) Further, since it is not necessary to perform the calculation process for squaring the calculation result by the absolute value average calculation circuit 30 within the baud rate clock, the calculation accuracy of the CN ratio is not deteriorated, and further, the input bit number The restriction on increasing the baud rate clock speed by many square circuits is relaxed, and the baud rate clock speed can be increased. (3) Absolute value average calculation circuit 30 and root mean square value calculation circuit 4 at a processing speed that is an integer fraction of the baud rate clock speed
By operating 0, the integrating circuits 32 and 42 having a large number of bits can be made to function even if the baud rate clock speed is increased, and the baud rate clock speed is increased without lowering the calculation accuracy of the CN ratio. It becomes possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a CN ratio detection device of a digital demodulation circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a CN ratio detection device of a digital demodulation circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a CN ratio detection device of a digital demodulation circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a CN ratio detection device of a digital demodulation circuit according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a CN ratio detection device of a digital demodulation circuit according to a conventional example.

[Explanation of symbols]

 1, 51 Carrier wave regeneration circuit 2 Complex multiplier 3, 53 Regenerated carrier wave 4 Register file 5 Microprocessor 30 Absolute value average calculation circuit 31 Absolute value circuit 32, 42 Accumulation circuit 40 Square mean value calculation circuit 41 Square calculation circuit 43, 44 Switch 52 quadrature detector 54 AD converter

Claims (5)

[Claims] 1. A carrier reproducing means for inputting a baseband I, Q digital input signal and a reproduced carrier into a complex multiplier and outputting an I, Q demodulated signal, and a digitized I demodulated signal or a Q demodulated signal. A mean square value calculating means for accumulating the squared output of the amplitude value a fixed number of times; an absolute value average calculating means for accumulating the absolute value of the amplitude value of the digitized I demodulated signal or the Q demodulated signal a fixed number of times; Mean square value data obtained by the mean square value calculating means, storage means for temporarily storing the mean absolute value data obtained by the mean absolute value calculating means, and mean square value data and absolute from the storing means Each value average data is taken into a microprocessor, and the C / N ratio of the I and Q digital input signals is arithmetically processed by this microprocessor to obtain the CN ratio. CN ratio detecting means of a digital demodulation circuit characterized by: 2. Carrier recovery means for inputting a digital modulated signal in the IF frequency band and a reproduced carrier into a quadrature detector to output a baseband I, Q analog output signal, and a digital signal for the I, Q analog output signal. AD conversion means for converting into a digital signal and outputting a digitized I, Q demodulated signal, and a mean square value for accumulating a squared arithmetic output of the amplitude value of the digitized I demodulated signal or the Q demodulated signal for a certain number of times. Calculating means, absolute value average calculating means for integrating the absolute value of the amplitude value of the digitized I demodulated signal or the Q demodulated signal for a predetermined number of times, and the mean square value data obtained by the mean square value calculating means A storage unit for temporarily storing the absolute value average data obtained by the absolute value average calculation unit; and a mean square value data and an absolute value average data from the storage unit. The data are taken into the microprocessor, the I, CN ratio detecting means of the digital demodulation circuit, characterized in that the CN ratio of the Q digital input signal as obtained by processing in the microprocessor. 3. Carrier recovery means for inputting a baseband I, Q digital input signal and a reproduced carrier into a complex multiplier and outputting an I, Q demodulated signal whose amplitude level is controlled, and a digitized I demodulation. A mean square value calculating means for accumulating the squared arithmetic output of the amplitude value of the signal or the Q demodulated signal a certain number of times; a storage means for temporarily storing the mean square value data obtained by the mean square value calculating means; A CN ratio detecting means of a digital demodulation circuit, wherein the root mean square value data is taken into the microprocessor from the means and the CN ratio of the I and Q digital input signals is arithmetically processed by the microprocessor. 4. A mean square value calculating means for accumulating the squared operation output of the amplitude value of the I demodulated signal or the Q demodulated signal for a predetermined number of times.
And the integration calculation processing speed of the absolute value average calculating means for integrating the absolute value of the amplitude value of the I demodulated signal or the Q demodulated signal a fixed number of times is 1 / R (R) of the output speed of the I demodulated signal or the Q demodulated signal. = 2,3, ...), the CN ratio detecting means of the digital demodulation circuit according to claim 1, 2 or 3. 5. An integrating circuit of a mean square value calculating means for integrating a squared operation output of an amplitude value of an I demodulated signal or a Q demodulated signal a fixed number of times, and an absolute value of an amplitude value of the I demodulated signal or the Q demodulated signal. 2. An integrating circuit of an absolute value average calculating means for integrating a certain number of times is shared.
Alternatively, the CN ratio detecting means of the digital demodulation circuit described in 2.