JPH09237231A - Backup device - Google Patents

Abstract

(57) Abstract: In a backup device, downsizing of the entire system and reduction of manufacturing cost and power consumption are realized. A DRAM (4) built in an integrated circuit (1) and based on a clock signal from a clock signal generation unit (46).
2. A backup refresh control signal generator 45 for generating a backup refresh control signal for backing up 2 and a non-backup refresh control from the DRAM controller circuit 2 which is built in the integrated circuit 1 and is not backed up. Signal to DRAM4
2 and supplies the backup refresh control signal from the backup refresh control signal generator 45 to the DRAM 42 during backup, the clock signal generator 46, and the backup refresh control signal generator 45. And a backup power supply means for supplying backup power supplies Vcc1 and Vcc2 to the selector circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (hereinafter referred to as "DR
AM)) and the like for a backup device that backs up a storage element that requires refreshing.

[0002]

2. Description of the Related Art A storage element is often used for storing data in various electronic devices such as a communication device such as a facsimile device and an information processing device.

There are various types of such storage elements, but a random access memory (hereinafter referred to as "RAM") is a storage element that is writable and readable and has a high access speed. It is used a lot. In particular, when processing a large amount of data, a relatively inexpensive DRAM is often used among the RAMs.

However, the contents of the RAM are lost when the power is cut off, so that the RAM must be backed up as a measure against power failure. In particular, the DRAM needs to be refreshed, as is well known, and therefore a control signal for refreshing must be supplied also at the time of backup.

Therefore, conventionally, as a backup device, a timer IC, a delay circuit, a logic circuit, a selector, and the like are specially provided for backup, and these are driven by a backup power supply at the time of backup, thereby providing a refresh control signal. Was generated and supplied to the DRAM.

That is, when the power is cut off, a clock signal generated by the timer IC is delayed by a delay circuit to generate a delayed clock signal, and a logical product of the delayed clock signal and the clock signal is calculated to perform refreshing. By generating a CAS signal and a RAS signal as control signals for the
M was refreshing. In short, even when an integrated circuit having a clock signal generation unit is used, a timer IC with large power consumption is separately provided without using the clock signal generation unit.

[0007]

However, in the conventional backup device, when the DRAM is controlled by an integrated circuit including a clock signal generation unit for generating a clock signal, such as an integrated circuit including a CPU, for example. However, since a timer IC and the like are separately provided for backup, there is a problem that the substrate area becomes large, which hinders downsizing of the entire system, and the manufacturing cost becomes high. In this case, the backup timer IC consumes a lot of power,
There was also a problem that power consumption during backup increased.

The present invention has been proposed in view of the above points, and it is an object of the present invention to provide a backup device capable of downsizing the entire system and reducing manufacturing cost and power consumption. There is.

[0009]

In order to achieve the above object, a backup device according to the invention described in claim 1 includes an integrated circuit and a storage element that needs refreshing, and at least the non-backup device in the integrated circuit. In a system that includes a refresh control signal generation unit that generates a non-backup refresh control signal for refreshing the storage element at times and a clock signal generation unit that generates a clock signal of a predetermined cycle, the storage element when the power is cut off And a backup-refresh-time control signal generating means for generating a backup-time-refresh control signal for backing up a storage element based on a clock signal from a clock signal generator, and a clock signal generator. For department and backup refresh To a control signal produced unit is provided with a the backup power supply means for supplying a backup power.

According to this backup device, the control signal generating means for refreshing at backup is refreshed at backup time for backing up the storage element at the time of backup based on the clock signal from the clock signal generating section built in the integrated circuit. Since the timer control IC is generated, it is not necessary to provide the timer IC separately from the integrated circuit. Therefore, the installation area of the timer IC on the substrate is not required, and the entire system can be downsized and the timer IC can be achieved. It is possible to reduce the manufacturing cost of the entire system by eliminating the manufacturing or purchasing cost. Moreover, since the timer IC that consumes a large amount of power is not needed by using the clock signal generator that has been provided conventionally, low power consumption can be realized.

The integrated circuit generates a clock signal and refreshes the DRAM or the like, such as an integrated circuit including a CPU that controls the entire facsimile machine. However, the integrated circuit does not necessarily include the CPU. Of course, you don't have to. Further, not limited to the facsimile device, it goes without saying that it may be an integrated circuit used in various electronic devices such as other communication devices and information processing devices. Further, the storage element is not limited to DRAM, and includes, for example, all that need refreshing, such as pseudo SRAM.

As the backup power source means, for example, a rechargeable battery or a dry battery can be used.

A backup device of the invention described in claim 2 includes an integrated circuit and a storage element that needs refreshing, and the integrated circuit has at least a non-backup time for refreshing the storage element during non-backup time. A backup device for backing up a storage element when power is cut off in a system including a non-backup refresh control signal generation unit for generating a refresh control signal and a clock signal generation unit for generating a clock signal of a predetermined cycle. , Built-in integrated circuit, and a backup-refresh-time control signal generator for generating a backup-time-refresh control signal for backing up a memory element based on a clock signal from a clock signal generator, and an integrated circuit Being backed up, non backup Switching that supplies the non-backup refresh control signal from the backup refresh control signal generator to the storage element, and supplies the backup refresh control signal from the backup refresh control signal generator to the storage element during backup And a clock signal generation unit, a backup refresh control signal generation unit, and a switching unit.

According to this backup device, since the backup refresh control signal generating section and the switching section are also incorporated in the integrated circuit, not only the timer IC but also
It is not necessary to separately provide a control signal generating unit for refreshing at backup and a switching unit, and therefore, the size reduction of the entire system and the reduction of manufacturing cost can be more significantly realized. That is, it is not necessary to separately provide a timer IC, a delay circuit, a logic circuit, a selector, etc., unlike the conventional backup device.

Further, the backup device of the invention described in claim 3 is the backup device according to claim 2, wherein the clock signal generator uses a crystal oscillator installed outside the integrated circuit to generate a clock signal. It is for generating a signal.

According to this backup device, since the clock signal is generated by using the crystal oscillator, the storage element can be refreshed accurately and the power consumption can be reduced. This is because the precision of the clock signal is high and the precision of the backup refresh control signal generated using the clock signal is also high, so that the refresh can be reliably performed with the minimum necessary number of refreshes. That is, general D
It takes about 15.6 μs to refresh the RAM
DR the CAS signal and RAS signal one or more times per ec
Must be supplied to AM. However, the conventional timer I
In the case of a backup device using C, the accuracy of the clock signal obtained by the timer IC is low and the variation is large. Therefore, if it is not adjusted to generate the CAS signal and the RAS signal every 8 to 9 μsec on average, 15 .6
The generation of the CAS signal and the RAS signal cannot be guaranteed once or more every μsec, and there is a possibility that the stored contents may be lost due to a refresh error. Therefore, the number of times of refreshing is unnecessarily increased, and the power consumption increases accordingly.

Further, the backup device of the invention described in claim 4 is the backup device according to claim 2 or 3, wherein the clock signal generating section uses, as a clock signal, a basic frequency clock signal and the basic frequency clock signal. A frequency-divided frequency clock signal obtained by frequency-dividing the frequency clock signal is selectively supplied to the backup-time refresh control signal generator.

According to this backup device, since the basic frequency clock signal and the divided frequency clock signal can be selectively used, it is possible to switch the cycle of the refresh-time control signal at the time of backup, so that the storage elements having different refresh cycles can be used. It is possible. That is, in the case of a low power consumption type DRAM, refreshing may be performed at a cycle eight times that of a normal DRAM. Therefore, the basic frequency clock signal is divided by 8 to generate a divided frequency clock signal. To generate a CAS signal and a RAS signal. Of course, the frequency-divided frequency clock signal is not limited to a cycle eight times as long as the basic frequency clock signal, and may be appropriately determined according to the refresh cycle of the storage element used. Further, by generating a plurality of divided frequency clock signals having mutually different cycles by dividing the basic frequency clock signal, it is possible to cope with three or more kinds of memory elements having mutually different refresh cycles.

Further, the backup device of the invention described in claim 5 is the backup device according to any one of claims 2 to 4, wherein the control signal generating section for refreshing at backup is a clock signal generating section. And a delayed clock signal obtained by delaying this clock signal by an external delay element installed outside the integrated circuit to generate a backup refresh control signal.

According to this backup device, since the delay element for delaying the clock signal to generate the backup refresh control signal is provided outside the integrated circuit, the delay element is formed inside the integrated circuit. As described above, the circuit scale is not increased, and the integrated circuit can be downsized. That is, the delay time by this delay element is required to be about 100 to 200 nsec when a general DRAM refresh control signal is generated, and an attempt is made to incorporate a delay element for realizing this in an integrated circuit. If this is done, the circuit scale will become large, but when it is provided outside the integrated circuit, it is only necessary to externally attach a resistor and a capacitor to the integrated circuit, and this can be realized very easily.

A backup device according to a sixth aspect of the present invention is the backup device according to any one of the second to fifth aspects, in which the backup voltage from the backup power supply means is reduced to a predetermined value or less. sometimes,
The backup power is supplied only to the clock signal generator.

According to this backup device, the clock signal generator can be backed up even in a situation where the backup voltage has dropped to the extent that backup of the memory circuit is impossible. For example, a clock function for measuring the present time. Can only hold. That is, a general inexpensive DRA
Although a voltage of about 4 to 5 volts is required to back up M, the clock signal generation unit and the clock circuit using the clock signal can operate at a voltage of about 1 to 2 volts, so the backup is performed. Even if the backup voltage drops due to a long time, only the clock function can be prevented from being lost, and as a result, time adjustment is not required when power is restored, and the timer function that uses the clock function can be maintained. .

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a circuit block diagram of a main part of an integrated circuit including a backup device according to the present invention. The integrated circuit 1 includes a DRAM controller circuit 2, a clock circuit 3, a frequency dividing circuit 4, and a register. 5, selector circuit 6, delay circuit 7, selector circuit 8, inverters 10 to 12, AND circuit 13, exclusive OR circuit 14, and OR circuit 1
5, 16 are built in, and terminals 21-35 are further provided. One end of the crystal oscillator 41 and one end of the capacitor C1 are connected to the terminal 24, and the terminal 25
Is connected to the other end of the crystal oscillator 41 and one end of the capacitor C2. The other ends of the capacitors C1 and C2 are grounded. One end of the resistor R1 is connected to the terminal 27, and the other end of the resistor R1 and one end of the capacitor C3 are connected to the terminal 28. The other end of the capacitor C3 is grounded. The terminals 32 to 35 are connected to the DRAM 42.

The integrated circuit 1 includes, for example, a CPU (not shown) that controls the entire facsimile apparatus, and DR
Data is read from and written into the AM 42. DR
The AM controller circuit 2 uses a READ signal, a WRITE signal, a CA signal for reading and writing data to the DRAM 42 and for refreshing when not backing up.
The S signal and the RAS signal are output. The clock circuit 3 measures the current time based on the clock signal from the frequency dividing circuit 4,
Furthermore, the clock signal from the frequency dividing circuit 4 is supplied to a required place as it is or after being processed. The frequency divider circuit 4 divides the clock signal supplied via the inverter 11 into eight times the period. The register 5 stores a numerical value corresponding to the refresh cycle of the DRAM 42 as a select signal. The selector circuit 6 selectively outputs the clock signal from the inverter 11 and the clock signal from the frequency dividing circuit 4 according to the select signal from the register 5. The delay circuit 7 outputs the output from the exclusive OR circuit 14 by 10 to 10.
A predetermined time of about 20 nsec is delayed. The selector circuit 8 receives the D signal in response to the select signal SEL from the terminal 29.
CAS signal from RAM controller circuit 2 and RA
The S signal, the CAS signal from the exclusive OR circuit 14 and the RAS signal from the delay circuit 7 are selectively output.

A power supply Vcc0 is supplied to the terminal 21,
This power supply Vcc0 is supplied to a circuit that is not backed up in the integrated circuit 1, such as the DRAM controller circuit 2. The power supply Vcc1 is supplied to the terminal 22, and the power supply Vcc1 is supplied with the delay refresh circuit 7, the inverter 12, the exclusive OR circuit 14, and the OR circuit 15, 16 for the backup time refresh control signal generator 45.
And the switching unit including the selector circuit 8 and the DRAM 42. The power supply Vcc2 is supplied to the terminal 23, and the power supply Vcc2 is supplied to the clock signal generation unit 46 including the clock circuit 3, the frequency dividing circuit 4, the register 5, the selector circuit 6, the inverters 10 and 11, and the AND circuit 13. Supplied. The state control signal MC1 is supplied to the terminal 26, and the state control signal MC1 is input to one input terminal of the AND circuit 13. The terminal 30 has a state control signal M
C2 is supplied, and the state control signal MC2 is input to one input terminal of the OR circuit 16. The state control signal MC3 is supplied to the terminal 31, and the state control signal MC3 is input to one input terminal of the OR circuit 15. Terminal 32
, The selector circuit 8 outputs a CAS signal, and the CAS signal is supplied to the DRAM 42. The RAS signal is output from the selector circuit 8 to the terminal 33.
The AS signal is supplied to the DRAM 42. The terminal 34 has
A READ signal is output via the OR circuit 16, and this READ signal is supplied to the DRAM 42. A WRITE signal is output to the terminal 35 via the OR circuit 15, and the WRITE signal is supplied to the DRAM 42.
Inverter 10, crystal oscillator 41, capacitors C1, C
2 constitutes an oscillation circuit, and this oscillation circuit oscillates at an oscillation frequency of 32.768 KHz, like the oscillation section of a real-time clock circuit for a general clock circuit. The resistor R1 and the capacitor C3 constitute a delay circuit as an external delay element, and this delay circuit is 100 to 200n.
The output of the AND circuit 13 is delayed for a predetermined time of about sec.

Next, the operation of the backup device thus constructed will be described. First, at the time of non-backup, the power supply Vcc0 applied to the terminal 21, the power supply Vcc1 applied to the terminal 22, and the power supply Vcc2 applied to the terminal 23 are all 5 volts, and the select signal SEL input to the terminal 29 is High level, terminals 30, 31
The state control signals MC2 and MC3 input to are at low level. Therefore, the RAS signal and the CAS signal from the DRAM controller circuit 2 are selected by the selector circuit 8 and are supplied to the DRAM 42.
READ signal from the M controller circuit 2 and WRI
The TE signal is appropriately supplied to the DRAM 42, and the DRAM 42
Read and write operations are performed as necessary.

On the other hand, the clock signal from the oscillation circuit including the crystal oscillator 41 is inverted by the inverter 11, divided by the frequency dividing circuit 4 into a cycle of 8 times, and supplied to the clock circuit 3 for the current time. The timekeeping operation is executed and is supplied from the clock circuit 3 to a predetermined circuit in the integrated circuit 1.

At the time of backup, the power supply Vcc0 applied to the terminal 21 is 0 V, the power supply Vcc1 applied to the terminal 22 and the power supply Vcc2 applied to the terminal 23 are 4.5 V, and the select input to the terminal 29 is selected. The signal SEL is at low level, and the state control signals MC1, MC2, MC3 input to the terminals 26, 30, 31 are at high level. Here, when the DRAM 42 is a normal type other than the low power consumption type, the register 5 is set to, for example, "1".
Are stored in the selector 11 and the selector circuit 6
And outputs it to the other input terminal of the AND circuit 13. Since the high-level state control signal MC1 is input to one input terminal of the AND circuit 13 via the terminal 26, the AND circuit 13 outputs the clock signal from the selector circuit 6 as it is. This clock signal is input to one terminal of the exclusive OR circuit 14, delayed by a delay circuit including the resistor R1 and the capacitor C3 for a predetermined time of about 100 to 200 nsec, and further inverted by the inverter 12 to be exclusive. It is input to the other input terminal of the logical OR circuit 14.

Here, if the clock signal from the AND circuit 13 has a waveform as shown in FIG. 2A, the inverted and inverted waveform thereof is as shown in FIG. 2B. Therefore, the output of the exclusive OR circuit 14 has a waveform as shown in FIG. Since the frequency of the clock signal shown in (a) of FIG. 2 is 32.768 KHz, (c) of FIG.
The waveform shown in (1) has a frequency of 65.536 KHz, and this period is approximately 15.26 μsec.

The output of the exclusive OR circuit 14 is supplied to the selector circuit 8 as a CAS signal at the time of backup, and is 10 to 20 nsec by the delay circuit 7.
R is delayed at the time of backup for a certain time.
The AS signal is supplied to the selector circuit 8. here,
Since the select signal SEL supplied to the selector circuit 8 via the terminal 29 is at a low level, the selector circuit 8 causes the CAS signal during backup from the exclusive OR circuit 14 and the RAS signal during backup from the delay circuit 7. Is selected and supplied to the DRAM 42. Further, since the state control signals MC2 and MC3 input to one terminal of the OR circuits 15 and 16 are at the high level, the high level signals are supplied from the OR circuits 15 and 16 to the DRAM 42 as the WRITE signal and the READ signal. To be done. As a result, the DRAM 42 is refreshed at a predetermined cycle by the CAS signal and the RAS signal at the time of backup. Here, the exclusive OR circuit 14
Clock signal from C, ie C at backup
The period of the AS signal is approximately 15.26 μse as described above.
c, which means that one or more refreshes are surely performed every 15.6 μsec required for the DRAM 42,
Moreover, many refreshes are not wasted. The DRAM 42 is refreshed in the normal CBR.
The READ signal at the time of refreshing may be at a low level or at a high level, but is set at a high level in order to improve the reliability of the refresh.

When a low power consumption type DRAM is used as the DRAM 42, "0" is stored in the register 5, for example. As a result, the selector circuit 6
Selects the clock signal from the frequency dividing circuit 4 and outputs it to the other input terminal of the AND circuit 13, so that the CAS signal and RA at the time of backup supplied to the DRAM 42 are supplied.
Low power consumption type DRA with 8 times longer S signal cycle
Optimal refresh is performed for M42. That is, the contents stored in the DRAM 42 can be reliably held, and a large number of refreshes will not be unnecessarily performed.

If the backup voltage becomes lower than the voltage required for refreshing the DRAM 42 due to the backup taking a long time, the power supply Vcc0 applied to the terminal 21 remains at 0 volt, and the terminal 22 is maintained. The power supply Vcc1 applied to the terminal 23 is 0V, and the power supply Vcc2 applied to the terminal 23 is 2V. Further, the state control signal MC1 input to the terminal 26 becomes low level. As a result, the DRAM 42 is not refreshed, but the clock circuit 3 and the frequency dividing circuit 4 can be operated with a power supply of 2 volts, so that the clock circuit 3 functions normally. The output of the AND circuit 13 is set to the low level by the state control signal MC1 in order to reduce the power consumption.

By the way, the power supplies Vcc0 to Vcc2 supplied to the terminals 21 to 31 of the integrated circuit 1 and the state control signal MC.
1 to MC3 and the select signal SEL are generated by a power supply control circuit provided outside the integrated circuit 1 as shown in FIG. That is, DC voltage of 5 V obtained from a commercial power source (not shown) and 4.
The 5-volt DC power is input to the power supply switching circuit 52. The power supply switching circuit 52 detects the DC power of 5 V obtained from the commercial power supply, and supplies the DC power to the terminals 21 to 23 of the integrated circuit 1 as the power supplies Vcc0 to Vcc2 if the DC power is input. To do. Further, when the 5V DC power obtained from the commercial power supply is not input due to a power failure or the like, the 4.5V DC power from the battery 51 is output to the voltage detection circuit 53. The voltage detection circuit 53
The voltage of the DC power from the power supply switching circuit 52 is detected, and if it exceeds a predetermined value, the DC power is supplied to the power supply Vcc.
1, Vcc2 to the terminals 22 and 23 of the integrated circuit 1, and if the voltage is less than or equal to a predetermined value, the DC power is supplied to the constant voltage circuit 5
4 is output. The constant voltage circuit 54 converts the DC power from the voltage detection circuit 53 into 2 V DC power, and supplies the DC power to the terminal 23 of the integrated circuit 1 as the power supply Vcc2. The power supply Vcc2 from the power supply switching circuit 52, the voltage detection circuit 53, and the constant voltage circuit 54 is also supplied to the control logic circuit 55 as a power supply, and the control logic circuit 55 has the power supply switching circuit 52 and the voltage detection circuit 53. According to the detection result by the selection signal S
The EL is output to the terminal 29 of the integrated circuit 1, and the status control signals MC1 to MC3 are output to the terminals 26 and 3 of the integrated circuit 1.
Output to 0, 31. The control logic circuit 55 may be formed inside the integrated circuit 1. FIG.
In, the control signal line is indicated by a chain line.

[0035]

As described above, according to the backup apparatus of the invention described in claim 1, the backup refresh control signal for backing up the memory element is provided on the basis of the clock signal from the clock signal generating section. Since the backup refresh control signal generating means and the backup power supply means for supplying the backup power to the clock signal generating section and the backup refresh control signal generating section are provided, the backup refresh control signal generating means is provided. , Based on the clock signal from the clock signal generator built into the integrated circuit,
Since a control signal for refreshing at the time of backup for backing up the storage element at the time of backup is generated, it is not necessary to provide a timer IC separately from the integrated circuit, the installation area of the timer IC is unnecessary, and the entire system can be downsized. In addition, it is possible to reduce the manufacturing cost of the entire system because the cost of manufacturing or purchasing the timer IC is unnecessary. Moreover, since the conventional clock signal generation unit is used to eliminate the need for a timer IC that consumes a large amount of power, the power consumption during backup can be favorably reduced.

Further, according to the backup device of the invention described in claim 2, the backup refresh control for backing up the memory element is built in the integrated circuit, and backs up the memory element based on the clock signal from the clock signal generating section. A backup refresh control signal generator that generates a signal and a built-in integrated circuit that supplies a non-backup refresh control signal from the non-backup refresh control signal generator to the storage element when not backing up, During backup, backup power is supplied to the switching unit that supplies the backup refresh control signal from the backup refresh control signal generator to the storage element, the clock signal generator, the backup refresh control signal generator and the switch unit. Backup power supply to supply Since the backup refresh control signal generator and the switching unit are incorporated in the integrated circuit, it is necessary to separately provide the backup refresh control signal generator and the switching unit in addition to the timer IC. Therefore, the overall size of the system can be reduced, and the manufacturing cost and power consumption can be significantly reduced.

Further, according to the backup device of the invention described in claim 3, since the clock signal generating section generates the clock signal by utilizing the crystal oscillator installed outside the integrated circuit, In addition to the effect of the backup device described above, since the clock signal is generated using the crystal oscillator, the storage element can be refreshed accurately and the power consumption can be reduced.

Further, according to the backup device of the invention described in claim 4, the clock signal generation unit, as the clock signal, the basic frequency clock signal and the divided frequency clock signal obtained by dividing the basic frequency clock signal. Is selectively supplied to the control signal generator for refreshing during backup, so that in addition to the effect of the backup device according to claim 2 or 3, the basic frequency clock signal and the divided frequency clock signal are selectively used. As a result, the cycle of the backup-time refresh control signal can be switched, and it is possible to accommodate storage elements having different refresh cycles.

Further, according to the backup apparatus of the invention described in claim 5, the backup refresh control signal generating section is provided with the clock signal from the clock signal generating section and the clock signal outside the integrated circuit. The control signal for refreshing during backup is generated by using the delayed clock signal delayed by the external delay element. Therefore, in addition to the effect of the backup device according to any one of claims 2 to 4, Since the delay element for delaying and generating the control signal for refreshing at backup is provided outside the integrated circuit, the circuit scale does not increase as in the case where the delay element is configured inside the integrated circuit, The circuit can be miniaturized.

Further, according to the backup device of the invention described in claim 6, when the backup voltage from the backup power supply means drops below a predetermined value, the backup power is supplied only to the clock signal generating section. In addition to the effect of the backup device according to any one of claims 2 to 5, the clock signal generation unit can be backed up even in a situation where the backup voltage drops to such an extent that backup of the memory circuit is impossible. Yes,
For example, only the clock function for measuring the current time can be retained.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a main part of an integrated circuit including a backup device according to the present invention.

FIG. 2 is a signal waveform diagram of a main part of the integrated circuit shown in FIG.

FIG. 3 is a circuit block diagram of a power supply control circuit that supplies power to the integrated circuit shown in FIG.

[Explanation of symbols]

 1 integrated circuit 2 DRAM controller circuit 3 clock circuit 4 frequency divider circuit 5 register 6 selector circuit 7 delay circuit 8 selector circuit 41 crystal oscillator 42 DRAM 51 battery

Claims (6)

[Claims] 1. A non-backup time, which includes an integrated circuit and a storage element requiring refresh, and which generates at least a non-backup refresh control signal for refreshing the storage element in the integrated circuit during non-backup time. In a system having a refresh control signal generation unit and a clock signal generation unit that generates a clock signal of a predetermined cycle, a backup device that backs up the storage element when the power is cut off, and a clock from the clock signal generation unit. A backup-time refresh control signal generating means for generating a backup-time refresh control signal for backing up the storage element based on a signal, and a backup to the clock signal generator and the backup-time refresh control signal generator. Supply power Backup unit, characterized in that provided a backup power supply means for. 2. A non-backup time, which includes an integrated circuit and a storage element that needs refreshing, and which generates at least a non-backup time refresh control signal for refreshing the storage element in the integrated circuit in the non-backup time. In a system including a refresh control signal generation unit and a clock signal generation unit that generates a clock signal of a predetermined cycle, a backup device that backs up the storage element when power is cut off, and is incorporated in the integrated circuit, A backup-time refresh control signal generation unit for generating a backup-time refresh control signal for backing up the storage element based on a clock signal from the clock signal generation unit, and a non-backup function built in the integrated circuit. Sometimes, the above A non-backup refresh control signal from the reshuffle control signal generator is supplied to the storage element, and a backup refresh control signal from the backup refresh control signal generator is supplied to the storage element during backup. A backup device comprising: a switching unit, a clock signal generation unit, a backup refresh control signal generation unit, and a backup power supply unit that supplies backup power to the switching unit. 3. The backup device according to claim 2, wherein the clock signal generating unit generates the clock signal by using a crystal oscillator installed outside the integrated circuit. 4. The clock signal generation unit selectively generates, as the clock signal, a basic frequency clock signal and a divided frequency clock signal obtained by dividing the basic frequency clock signal by the backup refresh control signal. The backup device according to claim 2 or 3, wherein the backup device is supplied to a unit. 5. The backup-time refresh control signal generating section delays the clock signal from the clock signal generating section and the clock signal by an external delay element provided outside the integrated circuit. 5. The backup device according to claim 2, wherein the backup refresh control signal is generated by using and. 6. The backup power supply is supplied only to the clock signal generator when the backup voltage from the backup power supply unit drops below a predetermined value. Backup device described in.