JPH09237242A - Port expansion method and port expansion method - Google Patents

Abstract

(57) An object of the present invention is to provide a port expansion method and a port expansion method capable of being normally accessed from a system even if a plurality of IDE ports exist in the same I / O address space. Is an issue. An IDE port (IDE-Po) to which a window of the same I / O address space is assigned on the system.
circuit (A) 1 for opening / closing a window of the same I / O address space in each of the integrated circuit (CHIP2) 14 and the integrated circuit (CHIP3) 17 having rt).
6 and a circuit (B) 118 are provided so that access to any IDE port can be selectively permitted by opening / closing a window.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a port expansion method and a port expansion method applied to a computer system, and more particularly to an IDE port in a system configuration in which an expansion unit is connected to a computer main body having a port address,
The present invention relates to a port expansion method and a port expansion method suitable for port expansion such as I / O port, IDE port in bridge connection configuration of PCI bus, port expansion such as I / O port, and the like.

[0002]

2. Description of the Related Art Conventionally, in a personal computer, an I / O device controlled by the computer main body is assigned as an I / O port in an I / O address space (1024 bytes) in the system.

Here, a conventional technique is considered with respect to the expansion of the IDE port allocated in this I / O port. Here, IDE (Integrated Drive Electroni
The port called cs) is used as an interface for connecting a hard disk drive (HDD) or the like on a personal computer.

In controlling the system, the personal computer controls a hard disk drive and the like by means of an IDE port assigned in the I / O address space in the system.

The IDE port has a port assigned to a predetermined I / O address space, but the system accesses the connected device (hard disk or the like) from this assigned port. 1
One IDE port will be able to control only one device.

A conventional IDE method in this case will be described with reference to FIG.

The CPU 71 controls the entire computer system.

The integrated circuit (CHIP1) 72 has a CPU 7
1 and an internal bus (I-BUS) 73, which is a system controller.

The integrated circuit (CHIP2) 74 controls the I / O, and the IDE port (IDE-Por).
t) is an address decoding controller.

The device (DV # 1) 75 is an IDE port (IDE-Por) of the integrated circuit (CHIP2) 74.
It is a device such as a hard disk drive connected to t).

When the system accesses the device (DV # 1) 75, the system uses the integrated circuit (CHIP) from the CPU 71.
1) IDE port (ID of integrated circuit (CHIP2) 74 connected to internal bus (I-BUS) 73 via 72
E-Port) to access the device (DV # 1)
Control 75.

In other words, the system does not have two IDE ports assigned with the same I / O address. At this time, the I / O address in which the IDE port is cracked must be placed in a pre-defined address space in order to maintain design and compatibility. Therefore, the I / O address unique to the extended IDE port can be easily used. It cannot be assigned.

In personal computer systems, the demand for expandability is increasing year by year.

In particular, an expansion system (expansion unit) called a desk station or a docking station
With notebook-type and book-type personal computers that are used by connecting to the
There was a demand to add more DE-connected devices and connect multiple devices.

However, in the prior art, as described above, when there are two or more (plural) IDE ports assigned to the same I / O address space, the ports collide with each other from the system perspective ( The I / O address spaces collide with each other), and the IDE ports assigned to the same address space cannot be controlled at all.

That is, even if a plurality of IDE ports exist in the same I / O address space, they cannot be accessed normally from the system, and even if different devices are attached to the respective ports, they cannot be controlled correctly.

[0017]

As described above, in the related art, there is a problem in that even if a plurality of IDE ports are assigned to the same I / O address space, the system cannot normally access them, and it is desired to expand the IDE ports. I could not meet the request.

The present invention has been made in view of the above circumstances,
An object of the present invention is to provide a port expansion method and a port expansion method that allow normal access from the system even if a plurality of IDE ports exist in the same I / O address space.

[0019]

The present invention is a system configuration in which a plurality of IDE ports to which windows of the same I / O address space are allocated are present on the system,
The same I / O is assigned to each of the devices having the IDE ports.
It is characterized by a port expansion method in which a circuit for opening / closing the window of the address space is provided, and it is possible to selectively permit access to any IDE port by opening / closing the window.

Further, according to the present invention, a plurality of I / Os to which windows of the same I / O address space are allocated on the system.
A system configuration in which a port exists, and each I / O
Each device having a port is provided with a circuit for opening / closing the window of the same I / O address space, and only the device having the circuit having the window opened is I
It is characterized by a port expansion method that permits access to the / O port.

Further, the present invention is a system configuration in which a plurality of IDE ports controlled by the same I / O address space are present on the system body side and the expansion board side, respectively.
A circuit that opens / closes a window of the I / O address space in all of the integrated circuits when at least one integrated circuit having an IDE port controlled by the same address exists on the system body side and the expansion board side, respectively. It is characterized by the port expansion method.

Further, the present invention is a system configuration in which a plurality of I / O ports controlled by the same I / O address space exist on the system body side and the expansion board side, respectively.
When there is at least one integrated circuit having I / O ports controlled by the same I / O address on the system body side and the expansion board side, respectively, the I / Os are provided on all of the integrated circuits.
It features a port expansion method with a circuit for opening / closing the address space window.

Further, according to the present invention, a window having the same I / O address space is assigned to each of a computer main body having a PCI bus and an expansion unit connected to the PCI bus of the computer main body through an expansion connector. At least one IDE port, and at least the device connected to the IDE port of the computer main body is
The port expansion method is characterized by providing a circuit for opening / closing the window of the / O address space.

Further, according to the present invention, a plurality of I's having windows of the same I / O address space allocated on a single system configuration (including a system configuration in which function expansion units are combined) are assigned.
A DE port is made to exist, and a circuit which becomes inaccessible by inserting a window in the same I / O address space is inserted into a device connected to these IDE ports,
It features a port expansion method that selectively accesses the address space you want to use.

By providing the port expansion function of the present invention as described above, even if a plurality of IDE ports exist in the same I / O address space, normal access from the system is possible.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of the main part according to the first embodiment of the present invention.

In FIG. 1, reference numeral 11 is a CPU that controls the entire system. 12 is a CPU 11 and an internal bus (I
-BUS) 13, which is an integrated circuit (CHIP1) having a function of a system controller which serves as a bridge.

Reference numeral 13 is an internal bus (I-BUS) to which various devices are connected via a bridge.
A plurality of IDE ports (IDE-Port) existing in a common I / O address space are connected to the internal bus (I-BUS) 1
3 (1) provided via the bridges (14, 17) respectively, and a plurality of IDE ports (IDE-Port) existing in a common I / O address space have internal bus (I-BUS) 13 (1) and this bus (I-BUS) 1
External bus (EB) connected to 3 (1) via a bridge
US) 13 (2) and bridges (14, 17) respectively
Assuming that the bus is installed via
And 13 (2) are shown separately.

Reference numeral 14 is an internal bus (I-BUS) 13 and ID
For example, an integrated circuit (CHIP2) having a function of controlling I / O, which serves as a bridge to an E device, and an IDE port (IDE-Por) allocated to the same I / O address space as an integrated circuit (CHIP3) 17 described later.
It has the address decoding function of t).

Reference numeral 15 is a circuit (A) provided in the integrated circuit (CHIP2) 14 for controlling the window of the I / O address space, and here, based on a window control signal (WIC) given from the outside. Open / close the above window to control the IDE port (IDE-Por)
The use of t) is permitted / prohibited and its internal circuit configuration will be described later with reference to FIG.

Reference numeral 16 is an ID of the integrated circuit (CHIP2) 14.
For example, a device (DV #) such as a hard disk drive (HDD) connected to the E port (IDE-Port)
1).

Reference numeral 17 serves as a bridge between the internal bus (I-BUS) 13 (or external bus (E-BUS) 13 (2)) and the IDE device, for example, an integrated circuit (CHIP3) having an I / O control function. And the integrated circuit (C
The HIP2) 14 has an address decoding function of an IDE port (IDE-Port) assigned to the same I / O address space.

Reference numeral 18 denotes a circuit (B) provided in the integrated circuit (CHIP3) 17 for controlling the window of the I / O address space, and here, like the circuit (A) 15 described above, it is given from the outside. Window control signal (WI
Based on C), the above window is opened / closed and the use of the IDE port (IDE-Port) is permitted /
The prohibition control is performed, and the internal circuit configuration will be described later with reference to FIG.

19 is the ID of the integrated circuit (CHIP3) 17
For example, a device (DV #) such as a hard disk drive (HDD) connected to the E port (IDE-Port)
2).

FIG. 2 is a block diagram showing the internal components of the circuit (A) 15 for controlling the window of the I / O address space provided in the integrated circuit (CHIP2) 14, and the integrated circuit (CHIP3). I provided in 17
Circuit (B) 1 for controlling the window of the / O address space
8 has the same configuration.

In FIG. 2, reference numeral 21 is an I / O address open / close register (O / C-Reg) for opening / closing a window, and 22 is this I / O address open / close register (O / C). -Reg)
21 is an address gate controlled by open / close (open / close).

The I / O address open / close register (O / C-Reg) 21 holds a window control signal (WIC) given at the time of initial setting of drk, and the corresponding IDE port (IDE-Por) according to the held contents.
The use of t) is permitted / prohibited. Here, when the stored content is “1”, the address gate (Address GATE) 2
2 is opened (open control is performed) to pass through the address, and when the stored content is "0", the address gate (Ad
Dress GATE) 22 is closed (closed control) to cut off the address transfer path.

The address gate (Address GATE) 22 is
Integrated circuit (CHIP2) 14 (or integrated circuit (CHIP2
3) The above I / O is intervened in the address transfer path of 17).
Address open / close register (O / C-Re
g) When "1" is received from 21, the address is passed through,
When 0 "is received, the address transfer path is cut off.

In this way, it becomes possible to simply open / close the window of the I / O address space. That is, the ID is controlled by controlling the I / O address open / close register (O / C-Reg) 21 of the circuit (A) 15 or the circuit (B) 18.
The integrated circuit (CHIP2) determines whether or not the I / O address space in which the E port (IDE-Port) exists can be accessed.
14, the integrated circuit (CHIP3) 17 can be notified.

Here, in order to access the device (DV # 1) 16, the system uses the internal bus (IB).
The I / O address open / close register (O / C-Reg) 21 of the circuit (A) 15 in the integrated circuit (CHIP2) 14 connected to the US) 13 is controlled. That is, in this case, "1" is set in the I / O address open / close register (O / C-Reg) 21.

When the I / O address open / close register (O / C-Reg) 21 is "1", the address gate (Address GATE) 22 is open (gate open). And the I / O address space is opened. By performing this processing, I of integrated circuit (CHIP2) 14
It becomes possible to control the DE port (IDE-Port).

At this time, the integrated circuit (CHIP3) 17 which uses the same I / O address space is connected to the internal bus (I-BU).
S) or an external bus (E-BUS) 13 (1) is connected to the system beforehand.
P3) 17 circuit (B) 18 I / O address open / close register (O / C-Reg) 21 is controlled. That is, in this case, "0" is set in the I / O address open / close register (O / C-Reg) 21.

When the I / O address open / close register (O / C-Reg) 21 is "0", the address gate (Address GATE) 22 is closed (gate closed), and therefore the address is narrowed. , IDE access is disabled. In this way, the I / O address space is closed.

By performing this processing, the system enables normal access to the device (DV # 1) 16.

Next, the device (DV # 2) 19 of the integrated circuit (CHIP3) 17 connected to the internal bus (I-BUS) 13 (1) or the external bus (E-BUS) 13 (2).
In order to access the
P3) 17 circuit (B) 18 I / O address open / close register (O / C-Reg) 21 is controlled. That is, at this time, the I / O address open / close register (O / C-Reg) 21 of the circuit (B) 18 is
Set “1” to.

When the I / O address open / close register (O / C-Reg) 21 of the circuit (B) 18 is "1", the address gate (Address GATE) 22 is open (gate open), so the address is through. Is in a state,
IDE access becomes possible and the I / O address space is opened. By performing this processing, the integrated circuit (C
It becomes possible to control the IDE port (IDE-Port) of the HIP3) 17.

At this time, the integrated circuit (CHIP2) 14, which uses the same I / O address space, is transferred to the internal bus (I-BU).
S) 13 (1), the system pre-configures the I / O address open / close register (O / C-Reg) 2 of the circuit (A) 15 of the integrated circuit (CHIP2) 14.
Control 1

That is, at this time, the I / O of the circuit (A) 15
Address open / close register (O / C-Re
g) Set "0" to 21.

When the I / O address open / close register (O / C-Reg) 21 of the circuit (A) 15 is "0", the address gate (Address GATE) 22 is closed (gate closed). It becomes a squeezed state,
IDE access is disabled. This closes the I / O address space.

By performing this processing, the system enables normal access to the integrated circuit (CHIP2) 14.

By providing such a function, even if there are a plurality of IDE ports assigned to the same I / O address space, the system can access only one IDE port. As a result, when there are a plurality of IDE ports, only the IDE port desired to be used can be used.

Also in terms of software, since only access control to the same I / O address space is performed, no major changes are required, and the circuits (A) 15 and (B) 1
Only 8 controls are added.

Next, referring to FIGS. 3 and 4, the second embodiment of the present invention will be described.
An embodiment will be described.

In the first embodiment described above, the integrated circuit (C
HIP2) 14 and I of integrated circuit (CHIP3) 17
I explained how to access a desired I / O address space by opening / closing this window in the I / O address space.
Open E port I / O address space window /
A circuit for closing is provided in the host bridge.

That is, in this embodiment, as shown in FIG. 3, an integrated circuit (CHIP
1) A circuit (C) 30 for opening / closing an I / O address space window is provided in 32.

The circuit (C) 30 in the integrated circuit (CHIP1) 32 is an integrated circuit (CHIP2) connected to the internal bus (I-BUS) 33 (1) or the external bus (E-BUS) 33 (2). 34 and integrated circuit (CHIP3) 17
Among them, a circuit for controlling which integrated circuit in the I / O address space to access the IDE port (IDE-Port) is provided.

That is, the system uses the internal bus (I-BU
S) 33 (1) or the integrated circuit (CHIP2) 34 and integrated circuit (CHIP3) 17 connected to the external bus (E-BUS) 33 (2), which I / O address space is to be accessed? Integrated circuit (CHIP1) 3
It will be decided by controlling the circuit (C) 30 in 2.

Further, signal lines 30a, 30b dedicated to IDE port selection are provided on the internal bus (I-BUS) 33 (1) and the external bus (E-BUS) 33 (2) to provide an IDE port (IDE-Port). Integrated circuit (CHIP2)
14 and the integrated circuit (CHIP3) 17 has a circuit (D) for receiving the signals SA and SB of the signal lines 30a and 30b.
35 and 38 are provided. The circuits (D) 35 and 38 have the same address gate function as the circuits (A) 15 and 18 (B) 18 in the first embodiment.

The circuit (C) 30 and the circuit (D) 3
The internal components of 5, 38 are shown in FIG. Here, in the circuit (C) 30, each I / O address open / close register (O / C-Reg) 4 of the circuits (D) 35 and 38 is provided.
It has 1a and 41b.

Here, the internal bus (I-BUS) 33 (1)
The device (DV #) connected to the IDE port (IDE-Port) of the integrated circuit (CHIP2) 34 connected above
1) In order to access 36, I / O of the circuit (C) provided in the integrated circuit (CHIP1) 32 by the system
O address open / close register (O / C-Re
g) 41a is controlled to be set to "1", and the internal bus (I-BU
S) 33 (1) Integrated circuit (CHIP2) 34 connected to the top
Signal (SA) to the integrated circuit (CHIP2)
The address gated by the circuit (D) 35 in 34 is responded.

After the completion of this control, the system operates the IDE port (IDE-Po) of the integrated circuit (CHIP2) 34.
rt) can be accessed, and the device (DV # 1)
36 can be controlled.

At this time, the integrated circuit (CHIP3) 37 that uses the same I / O address space is connected to the internal bus (I-BU).
S) 33 (1) or the external bus (E-BUS) 33 (2), the control signal (SB) from the integrated circuit (CHIP1) 32 is not a gate release (accessible logic). The device (DV # 2) 39 connected to the integrated circuit (CHIP3) 37 cannot be accessed.

Next, the internal or external bus (I-BUS or
E-BUS) 33 (2) Integrated circuit (CHIP)
3) In order to access the device (DV # 2) 39 connected to the IDE port (IDE-Port) 37, the system I (C) 30 provided in the integrated circuit (CHIP1) 32 / O address open / close register (O / C-Reg) 41b is set and controlled to "1", and a signal (code B) is sent to CHIP3 connected to the internal bus, and a circuit in integrated circuit (CHIP3) 37 (D) The gated address is responded at 38.

After this control is completed, the system can access the IDE port of the integrated circuit (CHIP3) 37, and can control the device (DV # 2) 39.

At this time, the integrated circuit (CHIP2) 34, which uses the same I / O address space, is transferred to the internal bus (I-BU).
S) 33 (1) or the external bus (E-BUS) 33 (2), the control signal (SA) from the integrated circuit (CHIP1) 32 is not a gate release (accessible logic). The device (DV # 1) 36 connected to the integrated circuit (CHIP2) 34 cannot be accessed.

By performing such processing, the system enables normal access to the device (DV # 2) 39.

By providing this function, the same I / O
Even if there are multiple IDE ports assigned to the address space, the system can access only one IDE port. Therefore, when there are a plurality of IDE ports, only the IDE port that is desired to be used can be used.

Also in terms of software, only access control to the same I / O address space is required.
A circuit (C) with a simple configuration that does not require major changes,
Only the control of (D) is added.

According to the above-described embodiment, when there are a plurality of IDE ports assigned to the same I / O address space, only the IDE port that is desired to be used can be used, so that the same I / O address space can be used. Similar control is possible for all I / O ports in the.
In other words, I connected to each device in terms of hardware
It becomes possible to freely control the / O device. Also in terms of software, there is an advantage that no major changes are required because only access control to the same I / O address space is performed.

Next, a third embodiment of the present invention will be described with reference to FIGS.

The third embodiment shows an example in which the present invention is applied to a computer system to which an expansion system (expansion unit) called a desk station or a docking station can be connected via a PCI bus.

In the third embodiment, as shown in FIG. 6, when there are a plurality of IDE ports assigned to the same I / O address space, either of them is provided by the positive decode / subtract decode function according to the PCI specification. An example is shown in which only one arbitrary IDE port is accessible by closing each of the other IDE port windows except one IDE port.

In FIG. 5, reference numeral 51 is a CPU that controls the entire system. 52 is a CPU 51 and an internal PCI
It is a host bridge (HOST-Bridge) having a function of a system controller, for example, which serves as a bridge with the bus (PCI-BUS) 53.

Reference numeral 53 denotes an internal PCI bus (PCI-BUS) to which various devices are connected via a bridge, and here, it is bus-connected to an expansion unit (DS) 61 via an expansion connector 60.

The PCI bus (PC
The I-BUS) 53 is an expansion unit (DS) when the expansion unit (DS) 61 is connected to the expansion connector 60.
It becomes a PCI bus on the primary side with a PCI-PCI bridge 62 provided in 61 as a boundary. At this time, the PCI bus (PCI-BU) in the expansion unit (DS) 61 described later is used.
S) 63 becomes the PCI bus on the secondary side.

54 is an internal PCI bus (PCI-BU
S) 53 is a bridge between the IDE device and, for example, a PCI device (PC) having an I / O control function.
I-Device), which is an expansion unit (D
S) PCI device in 61 (PCI-Device)
IDE assigned to the same I / O address space as 64
It has a port (IDE-Port) address decoding function. This PCI device (PCI-Device) 5
In the same manner as in the first embodiment described above, the I / O 4 is
It has a function part to open / close the address space window.

Reference numeral 55 is a PCI device (PCI-Device).
ce) 54 is a device (IDE) such as a hard disk drive (HDD) connected to an IDE port (IDE-Port).

Reference numeral 61 denotes an expansion unit (DS) connected to the computer main body via the expansion connector 60, which has various card slots for expanding the functions of the computer main body, equipment connection connectors and the like.

62 to 65 are expansion units (D
S) 61 is a constituent element, and 62 is a PCI bus (PCI-BUS) 53 inside the computer and a PCI bus (PCI-BUS) 63 inside the expansion unit (DS) 61.
It is a PCI-PCI bridge that bridges and, and here is a docking bridge (Docking-Bridg).
e).

63 is a PC in the expansion unit (DS) 61
I-bus (PCI-BUS), and here the PCI
An IDE port (IDE-P) assigned to the same I / O address space as the device (PCI-Device) 54
or PCI device having a PCI device (PCI-Device)
e) 64 is connected.

PCI in this expansion unit (DS) 61
Bus (PCI-BUS) is expansion unit (DS) 61
Is connected to the expansion connector 60 of the computer main body, it becomes a PCI bus on the secondary side with the PCI-PCI bridge 62 as a boundary. At this time, the PCI bus (PCI-BUS) 53 in the computer body is set to P on the primary side.
It becomes a CI bus.

64 is a PC in the expansion unit (DS) 61
I-bus (PCI-BUS) 63 and expansion unit (DS)
It becomes a bridge with the IDE device connected to 61,
For example, it is a PCI device (PCI-Device) having an I / O control function, and the PCI device (PCI-Device) 5 in the computer body described above.
4 has an address decoding function of an IDE port (IDE-Port) assigned to the same I / O address space as that of No. 4. This PCI device (PCI-Device) 64
Is a PCI device (PCI-
Like the Device 54, it has a functional unit for opening / closing the I / O address space window.

Reference numeral 65 denotes a PCI device (PCI-Device).
ce) 64 is a device (IDE) such as a hard disk drive (HDD) connected to an IDE port (IDE-Port) 64.

In the third embodiment, when the system accesses the device (IDE) 55, the system is a host bridge (HOST-Bridge) 52.
A PCI device (PCI-Device) 5 is issued by issuing an I / O address for normal IDE access to an internal PCI bus (PCI-BUS) 53 via
4 IDE ports (IDE-Port) can be controlled.

That is, at this time, the PCI positive decoding function causes the IDE port (I) of the PCI device (PCI-Device) 54 in the computer main body.
DE-Port) can be controlled.

At this time, the process of closing the IDE port window does not intervene at all.

Next, the system sets the device (IDE) 65
The system controls to close the IDE port window of the PCI device (PCI-Device) 54 when accessing.

As a result, the internal PCI bus (PCI-
Apparently on the BUS 53, a PCI device (PCI-
Device) 54 no longer exists, and the I / F issued from the system by the subtract decode function of PCI.
The I / O address for the DE port access is accepted by the PCI device (PCI-Device) 64 via the docking bridge (Docking-Bridge) 62 and the PCI bus (PCI-BUS) 63.
Device (IDE) 65 in expansion unit (DS) 61
Can be controlled, and the device (IDE) 65 can be normally accessed.

In FIG. 5, a PC inside the computer
I-bus (PCI-BUS) 53 and expansion unit (D
S) 61 to the PCI bus (PCI-BUS) 63,
Each of the configurations has one IDE port (IDE-Port), but more IDE ports (ID-Port) are used.
Even in a configuration having an E-port), an IDE similar to the above
Port access is possible.

At this time, as shown in FIG. 6, open / close of the IDE port window on each I / O address space is defined in the PCI configuration space, and any one IDE port to be accessed is defined. Except for this, each IDE port window may be closed.

By providing such a function, even if there are a plurality of IDE ports assigned to the same I / O address space, the system can access only one IDE port. As a result, when there are a plurality of IDE ports, only the IDE port desired to be used can be used.

Also in terms of software, since access to the same I / O address space is only controlled, no major changes are required, and only a circuit for opening / closing the IDE port window is added. is there.

Further, as in the third embodiment described above, a PC
PCI divided into a primary side bus and a secondary side bus by an I-PCI bridge (docking bridge) 62
An IDE port (IDE-Por) in which windows of the same I / O address space are assigned to both buses 53 and 63
By placing t), even if the window of the IDE port provided on the primary side bus is opened / closed, the ID provided on the secondary side bus is nevertheless irrelevant.
Since the E port window can be kept open at all times, the IDE port (IDE-P) can be configured with a simple configuration using the subtract decode function according to the PCI specifications.
ort) can be extended.

In the above embodiment, the IDE
Although the port expansion function has been described for ports, the present invention can be applied to expansion of I / O ports other than IDE ports. The present invention can be applied to other system structures such as a bus structure having more bridges than the embodiment.

[0096]

As described above in detail, according to the present invention, even if a plurality of IDE ports exist in the same I / O address space, the system can be normally accessed and the port expansion method and the port expansion method. Can be provided.

That is, according to the port expansion system of the present invention,
In a system configuration in which a plurality of IDE ports to which windows of the same I / O address space are assigned exist on the system, a window of the same I / O address space is provided to each of a plurality of devices having the IDE ports. By providing a circuit for opening / closing and allowing access to any IDE port selectively by opening / closing a window, multiple IDE ports controlled by the same address space exist in the system. However, it can be accessed from the system only by controlling the I / O address space window.

According to the port expansion method of the present invention, the system configuration is such that there are a plurality of I / O ports to which windows of the same I / O address space are allocated on the system, and each I / O is A circuit for opening / closing the window of the same I / O address space is provided for each of a plurality of devices having ports, and the I / O port is allowed to be accessed only to the device having the circuit that has opened the window. As a result, even if there are a plurality of I / O ports controlled by the same address space in the system, access can be made only by controlling the I / O address space window from the system.

Further, according to the port expansion system of the present invention, the system configuration is such that a plurality of IDE ports controlled by the same I / O address space exist on the system body side and the expansion board side, respectively. When there is at least one integrated circuit having an IDE port controlled by the same address on the main body side and the expansion board side, a circuit for opening / closing a window of the I / O address space is provided in all of the integrated circuits. Due to the provision, even if there are a plurality of IDE ports controlled by the same address space on the system and the expansion board, each IDE port can be normally accessed only by controlling the I / O address space window from the system.

Further, according to the port expansion system of the present invention, the system configuration is such that there are a plurality of I / O ports controlled by the same I / O address space on the system body side and the expansion board side respectively. When there are at least one integrated circuit having I / O ports controlled by the same I / O address on the system body side and the expansion board side, respectively,
Even if there are multiple I / O ports controlled by the same I / O address space on the system and the expansion board, the circuit that opens / closes the window of the I / O address space is provided in all of the integrated circuits. Each IDE port can be normally accessed only by controlling the I / O address space window from the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part according to a first embodiment of the present invention.

2 is a block diagram showing internal components of a circuit (A) 15 for controlling a window of an I / O address space, which is provided in the integrated circuit (CHIP2) 14 shown in FIG.

FIG. 3 is a block diagram showing a configuration of a main part according to a second embodiment of the present invention.

4 is a circuit (C) 30 and a circuit (D) 3 shown in FIG.
The block diagram which shows the internal component of 5,38.

FIG. 5 is a block diagram showing a configuration of a main part according to a third embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of the third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a system having a conventional IDE port.

[Explanation of symbols]

11 ... CPU controlling overall system, 12 ... Integrated circuit (C having function of system controller)
HIP1), 13 ... Internal bus (I-BUS), 14 ... Integrated circuit (CH) having I / O control function
IP2), 15 ... Circuit (A) for controlling window of I / O address space, 16 ... Device (DV #) connected to IDE port
1), 17 ... Integrated circuit (CH with I / O control function
IP3), 18 ... Circuit (B) for controlling window of I / O address space, 19 ... Device (DV #) connected to IDE port
2), 21 ... I / O address open / close register (O
/ C-Reg), 22 ... Address GATE, 30 ... Circuit (C) controlling window of I / O address space, 31 ... CPU controlling overall system, 32 ... Integrated circuit serving as host bridge (C) CHIP1), 33 ... Internal bus (I-BUS) 34 ... Integrated circuit (CHIP2) having IDE port, 35 ... Circuit (D) for receiving signal SA, 36 ... Device (DV #) connected to IDE port
1), 37 ... Integrated circuit (CHIP3) having IDE port, 38 ... Circuit (D) receiving signal SB, 41a ... I / O address open / close register (O / C-Reg), 41b ... I / O address Open / close register (O / C-Reg), 42 ... Address gate (Address GATE), 43 ... Address gate (Address GATE), 51 ... CPU controlling overall system control, 52 ... Host bridge (HOST-Bridge), 53 ... Internal PCI bus (PCI-BUS), 54 ... PCI device (PCI-Device), 55 ... Device (IDE) connected to IDE port, 61 ... Expansion unit (DS), 62 ... Internal PCI-PCI Bridge, 63 ... PCI bus (PC) in expansion unit (DS) 61
I-BUS), 64 ... PCI device (PCI-Device), 65 ... Device (IDE) connected to the IDE port.

Claims (10)

[Claims] 1. A system configuration having a plurality of IDE ports to which windows of the same I / O address space are allocated on the system, wherein the same I / O is provided to each device having each of the IDE ports.
A port expansion method characterized by providing a circuit for opening / closing the window of the address space and permitting access to the IDE port of the device having the circuit with the window opened. 2. A system configuration having a plurality of I / O ports to which windows of the same I / O address space are allocated on the system, wherein the same I / O port is provided to each device having the respective I / O ports. / O
A port expansion method characterized by providing a circuit for opening / closing the window of the address space and permitting access to the I / O port of the device having the circuit with the window opened. 3. A plurality of IDEs controlled by the same I / O address space on the system body side and the extension board side, respectively.
In a system configuration having ports, when there is at least one integrated circuit having an IDE port controlled by the same address on the system body side and the expansion board side, I / O is provided to all of the integrated circuits. A port expansion method that features a circuit that opens / closes the address space window. 4. A plurality of I / Os controlled by the same I / O address space on the system body side and the extension board side, respectively.
If the system configuration has ports, and there is at least one integrated circuit having I / O ports controlled by the same I / O address on the system body side and the expansion board side, all of the integrated circuits are present. To I / O
A port expansion method that features a circuit that opens / closes the address space window. 5. The same I / O is provided to each of a computer main body having a PCI bus and an expansion unit connected to the PCI bus of the computer main body via an expansion connector.
At least one IDE port to which a window of the address space is assigned is provided, and at least a device connected to the IDE port of the computer main body is provided with a circuit for opening / closing the window of the I / O address space. Port expansion method. 6. The same I is applied to both the primary side bus and the secondary side bus formed by interposing a bridge between buses.
An IDE port to which a window of the / O address space is assigned is provided, and the IDE port window provided on the secondary side bus is always open regardless of whether the IDE port window provided on the primary side bus is open or closed. Port expansion method. 7. A plurality of IDE ports to which windows of the same I / O address space are allocated are provided on a single system configuration, and the windows of the same I / O address space are provided to devices connected to these IDE ports. A port expansion method characterized by selectively accessing a desired address space through a circuit that becomes inaccessible when closed. 8. An IDE port, to which a window of the same I / O address space is allocated, is provided on both the PCI bus divided into a primary bus and a secondary bus by a PCI-PCI bridge, and is provided on the primary bus. A port expansion method characterized in that an IDE port window provided on a secondary bus is always open regardless of whether the IDE port window is opened or closed. 9. The single system configuration includes a system configuration in which function expansion units are combined.
The port expansion method described. 10. When there are a plurality of IDE ports to which windows of the same I / O address space are allocated on the PCI bus, one IDE on the configuration space
10. The port is set to be accessible.
The port expansion method described.