JPH09246286A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately control the width of a recess etching groove. SOLUTION: A side wall 18 made of silicon nitride film is formed at the side walls of a source electrode 15 and a drain electrode 16 respectively, and a recess etching groove 22 is formed in a channel region 14 with this side wall 18 as a mask. The control of the film thickness of the silicon nitride film is easy and the shape and dimension control of the side wall is easy so that the width of recess etching groove can be controlled accurately.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky gate type field effect transistor (hereinafter referred to as MESFET) and a method for manufacturing the same, and particularly to a MESFET characterized by recess etching a channel portion.
And its manufacturing method.

[0002]

2. Description of the Related Art A conventional method for manufacturing a MESFET will be described with reference to FIG. 3A to 3D are process cross-sectional views of a conventional manufacturing method. A high impurity concentration source region 32 and a drain region 33 are formed separately from each other on the upper surface of a semi-insulating GaAs substrate 31, and these regions are formed on the upper surface of the GaAs substrate 31 between the source region 32 and the drain region 33. After contacting to form the low impurity concentration channel region 34, the source electrode 35 is formed on the source region 32 and the drain electrode 36 is formed on the drain region 33 (FIG. 3A).

Next, a polyimide film 37 is applied and formed on the entire upper surface of the GaAs substrate 31 (FIG. 3B). Subsequently, the polyimide film 37 is cured at about 400 ° C.
To cure. At this time, the thickness of the polyimide film is reduced to about half by curing and curing (FIG. 3C).

Subsequently, the polyimide film 37 is replaced with O
₂ Etch back by RIE to form sidewalls 38 made of polyimide film 37 on the sidewalls of the source electrode 35 and the drain electrode 36, respectively (FIG. 3D).

Next, a silicon dioxide film 39 is formed on the upper surface of the GaAs substrate 31, a resist film 40 is laminated in this order, and then the resist film 40 is patterned to form an opening 41 at a desired portion where a gate electrode is to be formed. (Fig. 3
(E)).

Subsequently, an ammonium fluoride solution is introduced through the opening 41, and the silicon dioxide film 39 is removed by etching until the sidewall 38 is sufficiently exposed (FIG. 3 (F)).

In this state, a portion of the channel region 34 which is not covered with the sidewall 38 is removed by etching with a phosphoric acid type etching solution to form a recess etching groove 42 (FIG. 3G).

In this state, subsequently, by the vacuum deposition method,
Titanium, platinum, and gold are continuously vapor-deposited in this order to form a gate electrode metal 431 having a three-layer structure. At this time, the gate electrode metal 431 formed on the recess etching groove
And the metal 4 for the gate electrode formed on the resist film 39.
31 are formed separately from each other. (FIG. 3 (H)).

When the vacuum deposition is completed, the gate electrode metal 431 on the resist film 40 is lifted off and removed to form the gate electrode 43 on the recess etching groove 42. Further, the remaining silicon dioxide film 39 is removed with ammonium fluoride (FIG. 3 (I)).

Finally, the source electrode 35 and the drain electrode 3
6, the protective film 4 made of silicon nitride is formed on the surfaces of the gate electrode 43, the sidewall 38, and the recess etching groove 42.
4 is formed to obtain a MESFET (FIG. 3 (J)).

[0011]

However, the conventional M
In the ESFET manufacturing method, since the sidewall 38 is formed of the polyimide film, the following problems occur. That is, first, as shown in FIG. 3 (A), first, a polyimide film 37 is applied, and thereafter, a cure is performed.
It is necessary to cure the polyimide film 37 as shown in FIG.
Since 7 shrinks, it is difficult to control the film thickness of the polyimide film 37 after curing. Therefore, the sidewall 38
It is difficult to control the shape and size of the recess, the width of the recess etching groove 42 varies, and a semiconductor device having uniform characteristics cannot be obtained.

Secondly, the polyimide film 39 is applied after forming the source electrode and the drain electrode, and then 40
Curing is performed at a temperature of about 0 ° C. Therefore, the ohmic characteristics of the source electrode and the drain electrode deteriorate.

As a third problem, the polyimide film forming the side wall is an organic substance, and moisture absorption is inevitable during the process in which water is present. In particular, during the etching of the silicon dioxide film 39 of FIG. 3F and the formation of the recess etching groove 42 of FIG. 3G, the sidewalls are also exposed to the aqueous solution, and moisture absorption cannot be avoided. And
This sidewall is covered with the silicon nitride film 44 as shown in FIG. 3 (J), but thereafter, there is a possibility that the absorbed moisture will be desorbed and the surface of the recess etching groove 42 will be oxidized to induce characteristic fluctuation. is there.

On the other hand, in the above-mentioned conventional MESFET, since the silicon nitride film 44 as the protective film and the polyimide film of the sidewall 38 are used, there are the following problems. That is, the silicon nitride film and the polyimide film have different coefficients of thermal expansion, and the periphery of the side wall portion has a complicated shape due to recess etching and side wall etching. A crack is generated in the film 44, which affects reliability.

The present invention has been made to solve the above problems, and has a highly reliable semiconductor device having stable characteristics.
Another object of the present invention is to provide a manufacturing method in which a recess etching groove width can be easily controlled and a semiconductor device having uniform characteristics can be obtained.

[0016]

A semiconductor device according to the present invention is a compound semiconductor substrate, a channel region formed on one main surface of the compound semiconductor substrate, and the compound semiconductor in contact with one end of the channel region. A source region formed on one main surface of the substrate, a drain region formed on one main surface of the compound semiconductor substrate in contact with the other end of the channel region, and a source electrode formed on the source region. A drain electrode formed on the drain region, a sidewall made of silicon nitride formed on each of the source electrode sidewall and the drain electrode sidewall, and etched in the channel region using the sidewall as a mask. Recess etching groove, a gate electrode formed in the recess etching groove, the electrodes, the sidewall Those characterized by comprising a protective film made of pre said recess etching groove silicon nitride is formed to cover the surface.

Further, in the method of manufacturing a semiconductor device according to the present invention, a source region and a drain region are formed separately from each other on one main surface of a compound semiconductor substrate, and a gate region is formed between the source region and the drain region. And a drain region, respectively, a source electrode and a drain electrode are respectively formed on the source region and the drain region, and a silicon nitride film is formed on the semiconductor substrate including the electrode and the channel region. Forming the sidewalls of the source electrode and the drain electrode by etching back the silicon nitride film, and forming the sidewalls of the silicon nitride film on the sidewalls of the source electrode and the drain electrode, respectively. Insulation made of different material from the sidewall on the compound semiconductor substrate And a step of forming a resist film on the insulating film, patterning the resist film, and forming an opening in the resist film portion on the channel region, and then from the opening. Introducing an etching material, etching and removing the insulating film until the sidewalls are exposed, and etching the insulating film, and then etching the channel region surface to form a recess etching groove, And a step of forming a gate electrode on the surface of the recess etching groove using the resist film as a mask.

In the method of manufacturing a semiconductor device according to the present invention, after the gate electrode forming step, an insulating protective film is formed covering the compound semiconductor substrate including the electrodes, the sidewalls and the recess etching groove. It is characterized by including the step of performing.

The semiconductor device manufacturing method according to the present invention is characterized in that the sidewall and the protective film are made of the same material. Further, the method for manufacturing a semiconductor device according to the present invention is characterized in that the sidewall and the protective film are made of silicon nitride.

Further, in these semiconductor devices and the manufacturing method thereof, the formation position of the gate electrode does not have to be at the center of the drain electrode side wall and the source electrode side wall, and the gate electrode may be formed depending on the required characteristics. May be provided on the side of the source electrode sidewall.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 1A to 1I are process cross-sectional views of a method for manufacturing a MESFET according to this embodiment.

GaAs substrate 11 with no added impurities
An N-type source region 12 and a drain region 13 having a high impurity concentration are formed on top of each other with a space therebetween. The source region 12 and the drain region 13 are formed, for example, by using silicon ions at an acceleration voltage of 120 (kV) and a dose of 3.0 × 1.
Ion implantation is performed at 0 ¹³ (cm -2). Next, on the GaAs substrate 11 between the source region 12 and the drain region 13,
The low impurity concentration N-type channel region 14 is replaced with the source region 12
And the drain region 13, respectively.

The channel region 14 is formed, for example, by
After implanting silicon ions with an accelerating voltage of 70 (kV) and a dose of 4.0 × 10 ¹² (cm ⁻² ), 80
It is performed by annealing at a temperature of 0 ° C. and activating implanted ions.

The source region 12 and the drain region 13 and the channel region 14 may be formed in the reverse order. Subsequent to the above, the source electrode 15 and the drain electrode 16 are ohmic-contacted on the source region 12 and the drain region 13, respectively. The source electrode 15 and the drain electrode 16 are formed by stacking gold containing germanium, gold, and nickel in this order to a total thickness of 0.5 μm, and then performing a heat treatment at 400 ° C. Are formed (FIG. 1A).

Next, a silicon nitride film 17 is formed on the entire surface of the GaAs substrate 11 by plasma CVD to a thickness of about 1.0 micron (FIG. 1 (B)). Subsequently, the silicon nitride film 17 is subjected to anisotropic dry etching such as RIE. As a result, the silicon nitride film 17 on the source electrode 15, the drain electrode 16, and the central portion of the channel region 14 is uniformly removed by etching. At this time, the silicon nitride film 17 on the stepped portion at the end of the source electrode 15 and the drain electrode 16 on the side of the channel region 14 is formed on the electrode and Ga.
Since it is formed thick according to the step of the As substrate,
It remains on the sidewalls of the source electrode 15 and the drain electrode 16 when anisotropic etching is performed. As a result, the sidewalls 18 made of the silicon nitride film 17 each having a width of about 0.5 μm are formed on the sidewalls of the source electrode 15 and the drain electrode 16 (FIG. 1C).

The sidewall material may be any material that is resistant to the etching solution for the silicon dioxide film to be formed next, but the reason why the silicon nitride film is selected here is that the protective film to be formed later is used. By making the same as the film, it is possible to avoid cracking of the protective film due to the difference in thermal expansion coefficient between the sidewall and the protective film.

Next, silicon dioxide 19 is formed on the entire surface of the GaAs substrate 11 on which the source electrode 15 and the drain electrode 16 are formed, and a resist film 20 is successively laminated in this order, and then the resist film 20 is patterned. Then, the opening 21 is provided at a desired portion (FIG. 1D).

Then, an ammonium fluoride solution is introduced through the opening 21 to remove the silicon dioxide film 19 by etching. At this time, the etching solution not only etches the silicon dioxide film 19 directly under the opening 21, but also the sidewall 1 of the sidewall of the resist film 20 and the source electrode 15.
8 and between the resist film 20 and the side wall 18 of the side wall of the drain electrode 16 and into the source electrode 15 and a part of the drain electrode 16, and the side etching of the silicon dioxide film 20 is proceeded to form the side wall of the source electrode 15. The sidewall 18 of the drain electrode 16 and the sidewall 18 of the drain electrode 16 can be exposed (see FIG. 1).
(E)).

In this state, using a phosphoric acid type etching solution,
The recess etching groove 22 is formed by etching the surface portion of the channel region 14 between the sidewall 18 of the source electrode 15 and the sidewall 18 of the drain electrode 16 (FIG. 1F).

In this state, subsequently, by the vacuum deposition method,
Titanium, platinum, and gold are deposited in this order to form a gate electrode metal 231 having a three-layer structure on the recess etching groove 22. Further, the metal 23 for the gate electrode is also formed on the resist film 20.
1 is formed, but the silicon dioxide film serves as a spacer layer,
The gate electrode metal 231 on the recess etching groove 22 and the gate electrode metal 231 on the resist film 20 are formed separately from each other (FIG. 1G).

When the vacuum deposition is completed, the gate electrode metal 231 on the resist film 20 is lifted off to form the gate electrode 23 on the recess etching groove 22. Further, the remaining silicon dioxide film 19 is removed with ammonium fluoride. (FIG. 1 (H)).

Finally, the source electrode 15 and the drain electrode 1
6, a protective film 24 made of silicon nitride on the surfaces of the gate electrode 23, the sidewall 18 and the recess etching groove 22.
To obtain a MESFET (FIG. 1 (I)).

M according to the above-described first embodiment of the present invention
According to the ESFET manufacturing method, the following effects can be obtained. First, since a silicon nitride film is used as a sidewall material and the silicon nitride film is formed by a plasma CVD method, the film thickness can be easily controlled, and the step coverage of the source electrode side wall and the drain electrode side wall part can be easily covered. Is very good. Therefore, the shape and size of the sidewalls can be easily controlled, and the recess etching groove width does not vary, so that MESFETs having uniform characteristics can be obtained.

Secondly, since the silicon nitride film can be formed by the CVD method at a low temperature of about 300 ° C., there is no fear that the ohmic characteristics will deteriorate. Thirdly, silicon nitride used as the material of the sidewall is an inorganic substance, and does not absorb moisture even in the process where water is present. Therefore, MESFET
There is little risk of characteristic changes during operation.

Further, M according to the first embodiment of the present invention
According to the ESFET, since the sidewall is formed of the same silicon nitride film as the protective film, the following effects can be obtained. That is, since the thermal expansion coefficient of the sidewall and the protective film can be made equal, the peripheral portion of the sidewall has a complicated shape due to recess etching and sidewall etching. There is no risk of cracks in the protective film due to the difference between the two, and the reliability of the device can be improved.

Further, a second embodiment of the present invention will be described with reference to FIG. FIG. 2A and FIG.
FIG. 6 is a process sectional view of a method for manufacturing a MESFET according to this embodiment. In describing this embodiment, the first
The description of the same steps as those of the embodiment will be omitted, and only different steps will be described. First, on the semi-insulating GaAs substrate 11, the source region 12, the drain region 13, the channel region 14,
The source electrode 15, the drain electrode 16, and the sidewall 18 are formed (the steps up to here are the same as those in FIGS. 1A to 1C).

Subsequently, a silicon dioxide film 19 and a resist film 20 are formed on the entire surface, and then the resist film 20 is patterned to form an opening 211 in a desired portion.
At this time, although the opening 21 is formed at the center of the gate region 14 in the first embodiment, the opening 21 is formed here.
1 is set at a position deviated from the center position of the channel region 14.

From this state, the silicon dioxide film 19 is removed by etching through the opening 211, and the recess etching groove 22 is formed by using the side wall 18 on the side wall of the source electrode 15 and the side wall 18 on the side wall of the drain electrode 16 as masks. A gate electrode metal 231 having a three-layer structure of titanium, platinum, and gold is formed by vacuum evaporation (FIG. 2A).

After that, the gate electrode metal 231 on the resist film 20 is lifted off and removed, and a MESFET having a shape in which the gate electrode 23 is offset from the central axis of the recess etching groove 22 to the source electrode side can be obtained (FIG. 2).
(B)).

The MESFET obtained by the manufacturing method according to the second embodiment has the following special effects in addition to the effects according to the first embodiment. That is, the position of the gate electrode is offset to the source electrode side, and the distance between the drain electrode and the gate electrode is set to be larger than the distance between the source electrode and the gate electrode, so that the drain electrode and the gate electrode are interposed, and the source electrode and the gate electrode are The resistance between the source and the gate can be lowered and the breakdown voltage between the drain and the gate can be increased as compared with the case where the distance between the electrodes is equal.

In the above first and second embodiments, G
Although the MESFET using aAs as the substrate has been described, the application of the present invention is not limited to GaAs, and other compound semiconductor materials such as InP, InAs, and In can be used.
Sb, GaSb, GaP, SiGe or the like may be used.
Further, an epitaxially grown semiconductor film formed on a semiconductor substrate, for example, in addition to the above binary compounds, Ga as a Group 3 element, Al, In, and A as a Group 5 element
Needless to say, it is effective to use a ternary material or a quaternary material by combining s, P and Sb.

Also, the case where the channel, source and drain regions are formed by ion implantation has been described.
The application of the present invention is not limited to this, and a channel can be formed using an epitaxial growth method, a thermal diffusion method, a solid phase diffusion method, or the like.
Source and drain regions may be formed.

[0043]

According to the MESFET manufacturing method of the present invention, the MESF having uniform characteristics and good ohmic characteristics is obtained.
ET can be easily obtained. Further, the MESFET obtained by the manufacturing method of the present invention has stable characteristics and high reliability.

[Brief description of drawings]

FIG. 1 is a MESFET according to a first embodiment of the present invention.
FIG. 4 is a cross-sectional view of a manufacturing process.

FIG. 2 is a MESFET according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view of the manufacturing process of the main part of

FIG. 3 is a cross-sectional view of manufacturing steps of a conventional MESFET.

[Explanation of symbols]

 11, 31 ... GaAs substrate 14, 34 ... Channel region 13, 33 ... Drain region 12, 32 ... Source region 16, 36 ... Drain electrode 15, 35 ... Source electrode 17. ..Silicon nitride films 18, 38 ... Side walls 19, 39 ... Silicon dioxide films 37 ... Polyimide films 20, 40 ... Resist films 21, 211, 41 ... Openings 231, 431. ..Metal for gate electrode 23, 43 ... Gate electrode 22, 42 ... Recess etching groove 24, 44 ... Protective film

Claims (5)

[Claims] 1. A compound semiconductor substrate, a channel region formed on one main surface of the compound semiconductor substrate, and a source region formed on one main surface of the compound semiconductor substrate in contact with one end of the channel region. A drain region formed on one main surface of the compound semiconductor substrate in contact with the other end of the channel region, a source electrode formed on the source region, and a drain electrode formed on the drain region. A sidewall made of silicon nitride formed on each of the source electrode sidewall and the drain electrode sidewall, a recess etching groove formed in the channel region by using the sidewall as a mask, and a recess etching groove formed in the recess etching groove. The formed gate electrode is formed so as to cover the electrodes, the sidewalls, and the recess etching groove surface. A semiconductor device comprising a protective film made of formed silicon nitride. 2. A step of forming a source region and a drain region apart from each other on one main surface of a compound semiconductor substrate, and forming a channel region between the source and drain regions in contact with the source and drain regions, respectively. ,
Forming a source electrode and a drain electrode on the source region and the drain region, forming a silicon nitride film on the semiconductor substrate including the electrodes and the channel region, and etching the silicon nitride film. Forming a sidewall made of a silicon nitride film on the sidewalls of the source electrode and the drain electrode, respectively, and forming the sidewall on the compound semiconductor substrate including the electrodes, the sidewall, and the channel region. A step of forming insulating films of different materials,
Forming a resist film on the insulating film, patterning the resist film, forming an opening in the resist film portion on the channel region, and then introducing an etching material from the opening, A step of etching away the insulating film until the sidewalls are exposed, a step of etching the insulating film, a step of forming a recess etching groove by etching the surface of the channel region, and using the resist film as a mask, Forming a gate electrode on the surface of the recess etching groove. 3. A step of forming an insulating protective film is provided after the gate electrode forming step, covering the compound semiconductor substrate including the electrodes, the sidewalls and the recess etching groove. The method for manufacturing a semiconductor device according to claim 2. 4. The sidewall and the protective film,
The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor devices are made of the same material. 5. The side wall and the protective film,
5. The method of manufacturing a semiconductor device according to claim 4, wherein the method is made of silicon nitride.