JPH09246534A - Manufacture of pmos, and manufacture of cmos - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture of CMOS where both n MOS and p MOS can operate at high speed, and further short channel effect is hard to occur in the p MOS. SOLUTION: A p well 13a and an n well 13b are made on a silicon substrate 11. Next, punch through suppression implantation and channel implantation are performed for a region 17a, and punch through suppression implantation is performed for a region 17b. Next, silicon films 19a and 19b are made by epitaxial growth on the surface of the silicon substrate of this sample. The silicon films 19a1 and 19b1 in the first stage are made in thickness of 10nm on condition that the concentration of boron within the film becomes, for example, about 2.4×10<18> cm<-3> , and the silicon films 19a2 and 19b2 in the second stages are grown in thickness of 10-40nm on condition that the concentration of boron within the film becomes, for example, about 2.4×10<18> cm<-3> . Then, after formation of gate electrodes 27a and 27b, a source and a drain are made.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pMOS manufacturing method and a CMOS manufacturing method.

[0002]

2. Description of the Related Art In a buried channel type pMOS, a channel is formed inside the semiconductor, not on the surface of the semiconductor. Therefore, the carriers in the channel are not affected by surface scattering. Therefore, in the buried channel type pMOS, carrier mobility is improved and a high speed operation can be expected as compared with the surface channel type pMOS.

In such a buried channel type pMOS, boron (B), for example, is ion-implanted as a p-type dopant from the surface of a silicon (Si) substrate.
Channels can be formed inside the silicon substrate. Boron is ion-implanted from the surface of the silicon substrate over the area where the channel is to be formed. In this case, a channel is formed at a position apart from the surface of the silicon substrate. Therefore, the depletion layer charge (space ch
arge) is difficult to control and the gate length is 0.1 μm
When the length is shortened to a certain extent, there is a problem that a short channel effect (sometimes called a short channel effect) occurs.

As a method for solving this, Document 1: "T.
Ohguro et al., IEDM, Tech. Dig., P.433, 1993 ”. In the technique disclosed in Document 1, UHV-C
The VD method, the surface of the silicon substrate, boron 10 ¹⁹
The silicon film introduced at about cm ⁻³ has a thickness of 7.5 to 12.5n.
Epitaxially grow to a film thickness of m. As a result, a channel is formed inside the semiconductor composed of the silicon substrate and the silicon film.

In this way, when a channel is formed inside the semiconductor by thinly epitaxially growing a silicon film into which a high concentration of boron is introduced on the surface of the silicon substrate, boron ions are ionized from the surface of the silicon substrate. By implanting, a channel is formed closer to the surface of the semiconductor than when a channel is formed inside the silicon substrate. Therefore, the short channel effect is less likely to occur.

[0006]

However, when a channel is formed inside the semiconductor by thinly epitaxially growing a silicon film having a high concentration of boron introduced on the surface of the silicon substrate, the carriers are close to the surface. It comes to flow in the place where the boron concentration is high. For this reason, there is a problem that carrier scattering on the surface and impurity scattering increase and mobility decreases, and high-speed operation, which is an advantage of the buried channel type, cannot be performed.

In addition, by using such a method, CMOS
When the (complementary MOS) is formed, a silicon film having a high concentration of boron is formed on the surface of the substrate in both the nMOS and pMOS regions that form the CMOS. Therefore, even in the nMOS forming the CMOS, the impurity scattering of the carriers becomes large and the mobility is lowered. This is because the nMOS forming the CMOS is a surface channel type and carriers flow on the surface.

Therefore, there has been a demand for the appearance of a pMOS which can operate at high speed and is unlikely to cause the short channel effect. More desirably, a CMOS capable of high-speed operation in both nMOS and pMOS and in which a short channel effect is unlikely to occur in pMOS has been desired.

[0009]

Therefore, according to the first pMOS manufacturing method of the present invention, (a) an element isolation insulating film is formed on a silicon substrate to determine a pMOS formation planned region. And (b) forming a silicon film containing a p-type impurity on the surface of the silicon substrate in the pMOS formation planned region so that the p-type impurity concentration in the silicon film becomes higher toward the surface of the silicon substrate. , A step of forming by epitaxial growth, and (c) on the silicon film,
The method is characterized by including a step of forming a gate oxide film, (d) a step of forming a gate electrode on the gate oxide film, and (e) a step of subsequently forming a source and a drain.

Here, the epitaxial growth of the silicon film shown in step (b) may be performed so that the upper layer portion of the silicon film does not contain p-type impurities. Further, the epitaxial growth of the silicon film shown in step (b) may be performed in n (n is an integer of 2 or more) stages.

When the pMOS is manufactured in this way,
Depending on the thickness of the silicon film and the concentration distribution of the p-type impurity in the silicon film, the concentration of the p-type impurity is maximum in the region immediately below the gate electrode of the pMOS inside the semiconductor formed of the silicon substrate and the silicon film. The position showing the value and the position where the PN junction is formed are determined. In the case of pMOS, a channel is formed in a region centered on a position where the concentration of p-type impurities shows the maximum value, and holes which are carriers flow. Therefore, the influence of carrier surface scattering is reduced, and high-speed operation becomes possible. Furthermore, when the channel is formed in a region centered on a position close to the surface, the depletion layer charge is easily controlled by the gate voltage, and the short channel effect is less likely to occur.

When the epitaxial growth of the silicon film shown in step (b) is performed in n (n is an integer of 2 or more) stages, preferably the epitaxial growth of the silicon film in the first stage is performed with a p-type impurity concentration of 1 ×. It is preferable that the silicon film is grown to 10 ¹⁸ cm ⁻³ or more, and the epitaxial growth of the silicon film at the final stage is performed so that the p-type impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or less.

According to the second pMOS manufacturing method of the present invention, (a) a step of forming an inter-element isolation insulating film on a silicon substrate to determine a pMOS formation planned region, and (b) A step of forming a silicate glass film containing a p-type impurity on the surface of the silicon substrate in the pMOS formation planned region, and (c) a heat treatment is performed to make the p-type impurity contained in the silicate glass film on the silicon substrate. A step of diffusing to form a p-type impurity diffusion region in the surface layer of the silicon substrate, and (d) after removing the silicate glass film, the p-type impurity is formed on the surface of the silicon substrate in the pMOS formation planned region. Forming a silicon film containing silicon so that the p-type impurity concentration in the silicon film is lower than the p-type impurity concentration in the diffusion region; A step of forming a gate oxide film on the gate oxide film, (f) forming a gate electrode on the gate oxide film, and (g) thereafter forming a source and a drain. To do.

Here, the epitaxial growth of the silicon film shown in step (d) may be carried out so as not to contain p-type impurities. Further, the epitaxial growth of the silicon film shown in the step (d) is m (m is an integer of 1 or more).
It may be performed in stages, and at that time, the p-type impurity concentration in the silicon film may be increased toward the surface of the silicon substrate.

When the pMOS is manufactured in this way,
The film thickness of the silicon film, the concentration distribution of p-type impurities in the silicon film, and the p contained in the silicate glass film.
Depending on the concentration of the type impurity, the position where the concentration of the p-type impurity shows the maximum value and the position where the PN junction is formed in the region immediately below the gate electrode of the pMOS inside the semiconductor composed of the silicon substrate and the silicon film. Decided. pMO
In the case of S, a channel is formed in a region centered on the position where the concentration of the p-type impurity shows the maximum value, and holes as carriers flow. Therefore, the influence of carrier surface scattering is reduced, and high-speed operation becomes possible. Furthermore, when the channel is formed in a region centered on a position close to the surface, it becomes easier to control the depletion layer charge by the gate voltage,
Short channel effect is less likely to occur.

When the epitaxial growth of the silicon film shown in step (d) is performed in m (m is an integer of 1 or more) steps, it is preferable to diffuse the p-type impurity into the silicon substrate shown in step (c) into a diffusion region. Has a p-type impurity concentration of 1 × 1
0 ¹⁸ cm ^-3 or more and so as to perform the epitaxial growth of the silicon film at the final stage, p-type impurity concentration of 1 ×
It is preferable to perform it so that the pressure is 10 ¹⁷ cm ^-3 or less.

Further, according to the first CMOS manufacturing method of the present invention, (a) a step of forming an insulating film for element isolation on a silicon substrate to determine a pMOS formation planned region and an nMOS formation planned region. (B) a silicon film containing a p-type impurity is formed on the surface of the silicon substrate in the pMOS formation planned region and on the surface of the silicon substrate in the nMOS formation planned region, and the p-type impurity concentration in the silicon film is the silicon substrate. And (c) on the silicon film, the step of forming by epitaxial growth so that the height increases toward the surface of
The method is characterized by including a step of forming a gate oxide film, (d) a step of forming a gate electrode on the gate oxide film, and (e) a step of subsequently forming a source and a drain.

When the CMOS is manufactured in this way,
The same thing can be said for the pMOS forming the CMOS. On the other hand, the concentration of p-type impurities in the region just below the gate electrode of the nMOS forming the CMOS is low on the surface of the semiconductor formed of the silicon substrate and the silicon film. In the case of nMOS, a channel is formed in a region on the surface of a semiconductor composed of a silicon substrate and a silicon film, and electrons as carriers flow in this region. Therefore, the influence of electron impurity scattering is small, and high-speed operation is possible. Therefore, both the nMOS and the pMOS can operate at high speed, and the short channel effect hardly occurs in the pMOS.

Further, according to the second CMOS manufacturing method of the present invention, (a) a step of forming an inter-element isolation insulating film on a silicon substrate and determining a pMOS formation planned region and an nMOS formation planned region. And (b) a step of forming a silicate glass film containing a p-type impurity on the surface of the silicon substrate in the pMOS formation planned region and on the surface of the silicon substrate in the nMOS formation planned region, and (c) thereafter performing heat treatment. , P-type impurities contained in the silicate glass film are diffused into the silicon substrate to form p-type impurities on the surface layer of the silicon substrate.
Forming a diffusion region of the type impurities, and (d) after that,
After removing the silicate glass film, a silicon film containing p-type impurities is formed on the surface of the silicon substrate in the pMOS formation planned region and on the surface of the silicon substrate in the nMOS formation planned region, and the p-type impurity concentration in the silicon film is increased. Is epitaxially grown so as to have a concentration lower than the p-type impurity concentration of the diffusion region, (e) a gate oxide film is formed on the silicon film, and (f) a gate oxide film is formed on the gate oxide film.
The method is characterized by including a step of forming a gate electrode and (g) subsequently forming a source and a drain.

When the CMOS is manufactured in this way,
The same thing can be said for the pMOS forming the CMOS. On the other hand, the concentration of p-type impurities in the region just below the gate electrode of the nMOS forming the CMOS is low on the surface of the semiconductor formed of the silicon substrate and the silicon film. In the case of nMOS, a channel is formed in a region on the surface of a semiconductor composed of a silicon substrate and a silicon film, and electrons as carriers flow in this region. Therefore, the influence of electron impurity scattering is small, and high-speed operation is possible. Therefore, both the nMOS and the pMOS can operate at high speed, and the short channel effect hardly occurs in the pMOS.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the invention of the present application will be described below with reference to the drawings. In each of the drawings used in the following description, each component is only schematically shown in its shape, size, and positional relationship to the extent that the present invention can be understood. In each of the drawings used for description, the same components are denoted by the same reference numerals, and overlapping description may be omitted. Numerical conditions such as materials used and their amounts, processing time, processing temperature, and film thickness mentioned in the following description are only suitable examples within the scope of these inventions. Therefore, it should be understood that the invention according to this application is not limited only to these conditions.

In each of the following embodiments, CMOS
However, it should be understood that, when attention is paid to the pMOS forming the CMOS, the case of manufacturing the pMOS is also described.

1. First Embodiment FIGS. 1 to 4 are explanatory views in the case of manufacturing a CMOS.
Specifically, C with pMOS and nMOS adjacent to each other
It is a process drawing in the case of manufacturing a MOS, and is a process drawing shown by a cross-sectional view (however, a drawing is focused on a cut end) obtained by cutting a sample in a main process in the manufacturing process in a direction along a gate length. is there. However, in order to avoid complication of the drawing, some hatching showing the cross section is omitted.

First, a P-well 13a and an N-well are formed on a silicon (Si) substrate 11 by using a high energy ion implanter.
Well 13b is formed. Next, the P well 13a is set to nM.
Since the OS formation planned region N is used and the N well 13b is used as the pMOS formation planned region P, the silicon substrate 11 is
The insulating film 15 for element isolation is formed by a known method such as the LOCOS method. In this way, the nMOS formation planned region N and the pMOS formation planned region P are determined (FIG. 1).
(A)). The P well 13a can be formed by ion implantation using, for example, boron (B) with an implantation energy of 400 KeV and a dose amount of 1 × 10 ¹³ cm ⁻² , and the N well 13b can be formed by, for example, phosphorus (B). It can be formed by ion implantation using P) under the conditions that the implantation energy is 900 KeV and the dose is 1 × 10 ¹³ cm ^-2 .

Next, in order to control a so-called punch-through suppression implanter for suppressing the short channel effect and a threshold voltage in a region 17a which is a partial region of the nMOS formation planned region N and is substantially below the gate electrode. The so-called channel implantation is performed by the ion implantation method. The region thus ion-implanted is referred to as a region 17a subjected to channel implantation or the like. Further, a so-called punch-through suppression implantation for suppressing the short channel effect is performed by an ion implantation method in a region 17b which is a partial region of the pMOS formation planned region P and is substantially below the gate electrode. The region thus ion-implanted is referred to as a region 17b subjected to punch-through suppression implantation (FIG. 1).
(B)). The punch-through suppression implanter and the channel implanter for the P-well 13a are implanted into the region 17a with boron, for example, with an implantation energy of 45K.
Ion implantation under the conditions of eV and a dose of 4 × 10 ¹² / cm ² , and further boron fluoride (BF ₂ ) under the conditions of, for example, implantation energy of 90 KeV and a dose of 4 × 10 ¹² / cm ^2. You can do it by doing. On the other hand, punch-through suppression implantation into the N well 13b can be performed by ion-implanting phosphorus into the region 17b under the conditions of an implantation energy of 80 KeV and a dose amount of 2 × 10 ¹³ / cm ² .

Next, this sample is heat-treated at a temperature of, for example, 900 ° C. for 1 minute to recrystallize the surface of the silicon substrate 11 which has been made amorphous by ion implantation. afterwards,
On the surface of the silicon substrate 11 in the nMOS formation planned region and on the surface of the silicon substrate 11 in the pMOS formation planned region,
Silicon film 1 containing p-type impurities by UHV-CVD method
9a and 19b are replaced by p in the silicon films 19a and 19b.
It is formed by epitaxial growth to have a film thickness of 20 to 60 nm so that the type impurity concentration becomes higher toward the surface of the silicon substrate 11 (FIG. 1C). Silicon film 1
9a, 19b epitaxial growth in two stages,
As an example of using boron as the p-type impurity, the silicon films 19a ₁ and 19b _{1 in} the first stage are formed of, for example, silane (SiH ₄ ) or disilane (Si ₂ ) serving as a silicon source.
H ₆ ), and diborane (B ₂ H ₆ ) as a p-type impurity source
Are mixed as a reaction gas under the condition that the boron concentration in the first-stage silicon films 19a ₁ and 19b ₁ is, for example, about 2.4 × 10 ¹⁸ cm ^−3, and is used as a reaction gas, for example, 1 × 10 ⁻⁴ T
It can be formed by epitaxially growing to a film thickness of 10 nm at a substrate temperature of 500 to 700 ° C. under a reaction gas pressure of orr. Similarly, the second stage silicon film 19a
₂ and 19b ₂ are, for example, silane or disilane serving as a silicon source and diborane serving as a p-type impurity source, and the boron concentration in the second-stage silicon films 19a ₂ and 19b ₂ is, for example, 5 × 10 ¹⁶ cm ^−3. It can be formed by epitaxially growing to a film thickness of 10 to 50 nm at a substrate temperature of 500 to 700 ° C. under a reaction gas pressure of 1 × 10 ⁻⁴ Torr and used as a reaction gas. As the second stage silicon films 19a ₂ and 19b ₂ ,
In the case of forming a material that does not contain p-type impurities, for example, silane or disilane serving as a silicon source may be used as a reaction gas.

As will be described in detail later with reference to simulation results, when the silicon films 19a and 19b containing the p-type impurities are formed in this manner, the gate electrode of the pMOS immediately below the pMOS constituting the finally manufactured CMOS is formed. The concentration of the p-type impurity in the region is several tens nm from the surface of the semiconductor composed of the silicon substrate 11 and the silicon film 19b.
It shows a maximum value of about 1 × 10 ¹⁸ cm ⁻³ at distant positions.
10 nm from the position where the concentration of p-type impurities shows the maximum value
A PN junction is formed at a deeper position. In the case of pMOS, a channel is formed in a region centered on a position where the concentration of p-type impurities shows the maximum value, and holes which are carriers flow. Therefore, the influence of carrier surface scattering is reduced, and high-speed operation becomes possible. Further, since the channel is formed in a region centered on a position tens of nm away from the surface, it becomes easy to control the depletion layer charge by the gate voltage,
Short channel effect is less likely to occur. On the other hand, nMO
The concentration of the p-type impurity in the region immediately below the gate electrode of S is about 1 × 10 ¹⁷ cm ⁻³ or less on the surface of the semiconductor composed of the silicon substrate 11 and the silicon film 19a. In the case of the nMOS, a channel is formed in a region on the surface of the semiconductor composed of the silicon substrate 11 and the silicon film 19a, and electrons as carriers flow in this region. The concentration of boron, which is a p-type impurity, is 1 × 10 ¹⁷ cm
^-3 or less, the effect of electron impurity scattering is small,
Therefore, high speed operation becomes possible. In this way, both nMOS and pMOS can operate at high speed.
The short channel effect is less likely to occur in MOS.

Next, this sample was placed in an oxidation furnace, and this furnace was heated to a temperature of 800 ° C. to obtain silicon films 19a and 19a.
Gate oxide films 21a and 21b are formed on b in a film thickness of, for example, 5 nm (FIG. 2A).

Next, a polysilicon film (not shown) having a film thickness of 150 nm is formed on this sample by the LPCVD method, and phosphorus is introduced into this polysilicon film by the diffusion method or the ion implantation method. After that, a tungsten silicide (SiW) film (not shown) is formed to a thickness of 100 nm on this polysilicon film. Further, a resist pattern (not shown) as a mask for patterning the gate electrode is formed on this tungsten silicide film. Then, using this resist pattern as a mask,
The unnecessary portions of the tungsten silicide film and the polysilicon film are removed by suitable etching means. In this manner, the polysilicon film 23a and the tungsten silicide film 2 having a gate length of about 0.1 μm are formed on the gate oxide film 21a in the nMOS formation planned region.
The gate electrode 27a having 5a is formed, and pMO is similarly formed.
0.1 μm on the gate oxide film 21b in the S formation planned region
A gate electrode 27 having a gate length of the order of magnitude and having a polysilicon film 23b and a tungsten silicide film 25b.
b is formed (FIG. 2B). The gate electrode 27
a and 27b, the tungsten silicide film 25a,
Note that 25b is for lowering the resistance of the gate electrode and is not the essence of the invention.

Next, on this sample, a resist pattern (not shown) is formed as a mask for forming the n-type source / drain region 29a having a shallow junction in a predetermined portion of the nMOS formation planned region. Then, using the resist pattern and the gate electrode 27a as a mask, a shallow junction n-type source / drain region 29a is formed by ion implantation.
Is formed (FIG. 2C). The shallow junction n-type source / drain regions 29a are implanted with arsenic (As), for example, with an implantation energy of 10 KeV and a dose of 1 × 10 ^15.
/ Cm ² It can be formed under the condition.

Next, tetraethoxysilane (Tetra-Ethoxy-Silane) was used as a raw material on this sample to obtain CV.
A SiO ₂ film (not shown) is formed to a thickness of 50 nm by the D method. Then, this SiO ₂ film is subjected to anisotropic etching by the reactive ion etching method to perform etch back. Thus, the first sidewall films 31a and 3a are formed on the sidewalls of the gate electrode 27a in the nMOS formation planned region and the sidewalls of the gate electrode 27b in the pMOS formation planned region.
1b is formed (FIG. 3A).

Next, on this sample, a resist pattern (not shown) is formed as a mask for forming the p-type source / drain region 29b having a shallow junction in a predetermined portion of the pMOS formation planned region. Then, using the resist pattern, the gate electrode 27b and the first side wall film 31b as a mask, a p-type source / drain region 29b having a shallow junction is formed by an ion implantation method (FIG. 3B). The shallow junction p-type source / drain region 29b is
Boron fluoride can be formed, for example, under the conditions that the implantation energy is 10 KeV and the dose amount is 1 × 10 ¹⁵ / cm ² .

Next, a SiO ₂ film (not shown) having a film thickness of 200 nm is formed on this sample by a CVD method using tetraethoxysilane as a raw material. Then, this SiO ₂ film is subjected to anisotropic etching by the reactive ion etching method to perform etch back. In this way, the second sidewall films 33a and 33b are formed on the sidewalls of the first sidewall films 31a and 31b (FIG. 3C).

After that, the n-type source / drain region 35a having a deep junction is formed by the same process as the case where the n-type source / drain region 29a having a shallow junction is formed.
A p-type source / drain region 35b having a deep junction is formed by the same process as that for forming the p-type source / drain region 29b having a shallow junction (FIG. 4). However, when the n-type source / drain region 35a having a deep junction is formed,
Resist pattern, gate electrode 27a, first sidewall film 3
When the deep junction p-type source / drain region 35b is formed by using 1a and the second sidewall film 33a as a mask, the resist pattern, the gate electrode 27b, the first sidewall film 31b, and the second sidewall film are formed. 33b is used as a mask. The deep junction n-type source / drain region 3
5a can be formed by implanting arsenic under the conditions of an implantation energy of 100 KeV and a dose of 5 × 10 ¹⁵ / cm ² .
The deep junction p-type source / drain regions 35b can be formed of boron fluoride, for example, under the conditions that the implantation energy is 70 KeV and the dose is 2 × 10 ¹⁵ / cm ² .

Finally, a rapid heating device (RTA device) is used to perform heat treatment at a temperature of, for example, 1050 ° C. for 10 seconds to activate all impurities. As described above, it is possible to manufacture a CMOS having a fine gate length, specifically, a CMOS in which a pMOS and an nMOS are adjacent to each other.

The gate electrodes 27a and 27b of the nMOS and pMOS which constitute the CMOS manufactured as described above.
Two-dimensional process simulator (O
PUS). Specifically, the silicon film 19
The epitaxial growth of a and 19b is performed in two steps, and p
CMOS manufactured by using boron as a type impurity, more specifically, first-stage silicon films 19a ₁ and 19b ₁
The concentration of boron in the films 19a ₁ and 19b ₁ is 2.
4 × 10 ¹⁸ cm was formed at ^-3 and condition: a film thickness of 10 nm, a silicon film 19a _2, 19b ₂ of the second stage, the film 19a _2, 19b is the concentration of boron in ₂ 5 × 10 ¹⁶ c
The impurity profile in the region directly under the gate electrodes 27a and 27b of the nMOS and pMOS forming the CMOS manufactured by forming the film with a film thickness of 30 nm under the condition of m ⁻³ was obtained.

FIG. 5 shows an impurity profile for the nMOS. FIG. 5 (A) shows the boron profile immediately after the formation of the silicon film 19a, and FIG. 5 (B) shows C.
The boron profile after completion of MOS fabrication is shown. Similarly, FIG. 6 shows an impurity profile for the pMOS. In FIG. 6A, a boron profile immediately after the formation of the silicon film 19b is shown by a curve a, and a phosphorus profile is shown by a curve b. ) Is the CMO
The profile of boron after completion of S production is shown by curve a, and the profile of phosphorus is shown by curve b. In addition,
The horizontal axis of FIGS. 5A and 5B and FIGS. 6A and 6B indicates the silicon substrate 11 and the silicon films 19 a and 1 a.
The distance X (nm) measured in the direction toward the inside of the semiconductor is shown perpendicular to the surface of the semiconductor composed of 9b,
The vertical axis represents the impurity concentration (cm ⁻³ ).
However, the position where the curve indicating the boron profile intersects the X axis, that is, FIGS. 5A and 5B, and FIG.
The positions indicated by s on the horizontal axes of (A) and (B) correspond to the positions of the surface of the semiconductor composed of the silicon substrate 11 and the silicon films 19a and 19b.

Hereinafter, the silicon substrate 11 and the silicon film 1
Tens of nm from the surface of the semiconductor composed of 9a and 19b
The description will be made focusing on the area. As can be understood from FIGS. 5A and 5B, after the silicon film 19a is formed, the concentration of boron in the region immediately below the gate electrode 27a of the nMOS forming the CMOS manufactured by performing the various processes described above is , A maximum value of about 1 × 10 ¹⁸ cm ⁻³ at a position about 40 nm away from the surface of the semiconductor composed of the silicon substrate 11 and the silicon film 19a. Further, the concentration of boron is about 1 × 10 ¹⁷ cm ^{−3 on} the surface of the semiconductor composed of the silicon substrate 11 and the silicon film 19a. In the case of the nMOS, a channel is formed in a region on the surface of the semiconductor composed of the silicon substrate 11 and the silicon film 19a, and electrons as carriers flow in this region.
When the boron concentration is about 1 × 10 ¹⁷ cm ⁻³ , the effect of electron impurity scattering is small. Therefore, high-speed operation is considered possible.

On the other hand, as can be understood from FIGS. 6 (A) and 6 (B), after forming the silicon film 19b, the pMO forming the CMOS manufactured by performing the above-mentioned various processes.
The concentration of boron in the region immediately below the gate electrode 27b of S is 1 × 1 at a position about 40 nm away from the surface of the semiconductor composed of the silicon substrate 11 and the silicon film 19b.
The maximum value is about 0 ¹⁸ cm ^-3 . Further, the boron concentration is about 1 × 10 ¹⁷ cm ^{−3 on} the surface of the semiconductor composed of the silicon substrate 11 and the silicon film 19b. The boron concentration and the phosphorus concentration are the same as those of the silicon substrate 11
And at a position about 50 nm away from the surface of the semiconductor composed of the silicon film 19b. A PN junction is formed at a position where the boron concentration is equal to the phosphorus concentration. pM
In the case of OS, a channel is formed in a region centered on a position where the concentration of p-type impurities shows the maximum value, and holes as carriers flow. Therefore, it is considered that the influence of the carrier surface scattering is reduced and high-speed operation becomes possible. Further, since the channel is formed in a region centered on a position 50 nm away from the surface, it is considered that the depletion layer charge is easily controlled by the gate voltage and the short channel effect is less likely to occur.

As described above, it is considered that both the nMOS and the pMOS can operate at high speed, and the short channel effect hardly occurs in the pMOS.

Therefore, the CMO manufactured as described above is used.
In order to examine the operating speeds of the nMOS and pMOS forming S in more detail, a two-dimensional device simulator (ODESA) manufactured by Oki Electric Industry Co., Ltd. was used.
For each of the nMOS and pMOS, a gate voltage dependence of the drain current was obtained (hereinafter, sometimes referred to as I _D -V _G characteristics.). I _D -V _G for nMOS
The characteristics are obtained under the condition that the drain voltage is 0.1 V, and pMO
I _D -V _G characteristics for S, the drain voltage is -0.1
It was determined under the condition of V. However, here, in order to avoid the influence of the short channel effect, an nMOS and a pMOS having a gate length of 1 μm were examined. Furthermore, n
I _D obtained for each of the MOS and pMOS
From -V _G characteristics for each of the nMOS and pMOS, a gate voltage dependence of the transconductance (hereinafter,
Sometimes referred to as G _m -V _G characteristics. ). Note that these electrical characteristics are obtained by performing the epitaxial growth of the silicon films 19a and 19b in two steps and manufacturing the CMOS using boron as a p-type impurity, more specifically, the first-stage silicon films 19a ₁ and 19b ₁ . , The film 19a
The concentration of boron in ₁ , 19b ₁ is 2.4 × 10 ¹⁸ cm
The film thickness of 10 nm is formed under the condition of ^-3, and the second-stage silicon films 19a ₂ and 19b ₂ are formed into the films 19a ₂ and 19b.
20nm under the condition that the concentration of boron in ₂ becomes ^{5 × 10 16 cm -3, 30nm} , nMOS and pMOS forming a CMOS manufactured by forming a film thickness of 40nm
Asked against. In addition, the second stage silicon film 19a
_The electrical characteristics for the nMOS and pMOS forming the CMOS manufactured without forming ₂ , 19b ₂ were also obtained.

[0042] Figure 7 is an electric characteristic obtained for nMOS, in FIG. 7 (A) shows an I _D -V _G characteristics, FIG. 7
In (B) shows a G _m -V _G characteristics. Similarly, FIG. 8 shows the electrical characteristics obtained for the pMOS.
8A shows the I _D -V _G characteristic, and FIG.
Shows a G _m -V _G characteristics. 7 (A) and 8
The curve a in (A) is the second-stage silicon film 19a ₂ ,
An I _D -V _G characteristics when not formed 19b _2, curve b~d the silicon of the second stage membrane 19a _2, 1
The 9b ₂ 20μm, 30μm, an I _D -V _G characteristics when formed each in a thickness of 40 nm. FIG.
The curve e in FIG. 8B and FIG. 8B is G _m − when the second-stage silicon films 19a ₂ and 19b ₂ are not formed.
A V _G characteristic curve f~h is G _m -V _G characteristics in the case of forming each of the silicon film 19a _2, 19b ₂ of the second stage 20 [mu] m, 30 [mu] m, the thickness of 40 nm.
7A and 8A, the horizontal axis represents the gate voltage V _G (V), and the vertical axis represents the drain current I.
_D (μA / μm) is shown. FIG.
The horizontal axis of FIGS. 8B and 8B indicates the gate voltage V _G.
(V) is shown and the vertical axis shows the mutual conductance G.
_m (μS / μm) is shown.

[0043] Here, I _D -V from _G characteristic method for obtaining a G _m -V _G characteristics, p ₁ point and p in FIG. 7 (A)
_An explanation will be given using _two points and the q point in FIG. p
₁ point and p ₂ point are the same as those of the second-stage silicon film 19a ₂
Is two adjacent plots in curve d indicating the I _D -V _G characteristics when formed into a film having a thickness of 0 nm. q point is G _m −
It is a plot in the curve h showing the V _G characteristic, and is obtained from the points p ₁ and p ₂ . When the q point is calculated from the p ₁ point and the p ₂ point, first, p is calculated from the value of the gate voltage V _G at the p ₂ point.
The value of the gate voltage V _G at _one point is subtracted to obtain the gate voltage difference Δ
Find V _G. Next, the drain current difference ΔI _D is obtained by subtracting the value of the drain current I _D at the point p ₁ from the value of the drain current I _D at the point p ₂ . Then, the average of the value of the gate voltage V _G at the point p ₁ and the value of the gate voltage V _G at the point p ₂ is q
Let the value of the gate voltage V _G at the point be ΔI _D / ΔV _{G be} the value of the mutual conductance G _m at the point q. Other plots of the curves e to h can be obtained by the same method.

As can be understood from FIG. 7A, the CMO
The drain current I _{D of the} nMOS forming S is 0.1 (μ
The absolute value of the value of the gate voltage V _G (hereinafter, may be referred to as the threshold voltage V _th ) when it becomes A / μm) becomes smaller as the second-stage silicon film 19a ₂ is formed thicker. Become. Further, as can be understood from FIG. 7B, the maximum value of the mutual conductance G _m becomes larger as the second-stage silicon film 19a ₂ is formed thicker. In particular, compared with the maximum value of the mutual conductance G _m when the second stage silicon film is not formed, the second stage silicon film 19a ₂
The maximum value of the mutual conductance G _m when the film is formed with a thickness of 40 nm is almost doubled.

On the other hand, as can be understood from FIG. 8 (A),
The absolute value of the threshold voltage V _th of the pMOS forming the CMOS becomes smaller as the second-stage silicon film 19b ₂ is formed thicker. Further, as can be understood from FIG. 8B, the thicker the second-stage silicon film 19b ₂ is,
The maximum value of the mutual conductance G _m becomes large. Especially,
Compared with the maximum value of the mutual conductance G _m when the second-stage silicon film is not formed, the maximum value of the mutual conductance G _m when the second-stage silicon film 19b ₂ is formed with a thickness of 40 _n is It almost doubles.

As described above, in both the nMOS and the pMOS, the thicker the second-stage silicon films 19a ₂ and 19b ₂ are formed, the larger the maximum value of the mutual conductance G _m becomes. Therefore, it can be understood that the nMOS and pMOS both can operate at higher speed as the second-stage silicon films 19a ₂ and 19b ₂ are formed thicker. However, in the pMOS, the thicker the second-stage silicon film 19b ₂ is, the larger the subthreshold coefficient is. Therefore, in consideration of this, the second-stage silicon film 19b ₂ is formed.
It is necessary to determine the film thickness for forming a ₂ and 19b ₂ . This means that the absolute value of the gate voltage V _G is equal to the threshold voltage V
_It can be understood by paying attention to the area where the absolute value of _th is less than or equal to the absolute value.

Further, the CMOS manufactured as described above
In order to study in more detail the short channel effect of the nMOS and pMOS that configure
The threshold voltage difference ΔV _th was obtained by subtracting the threshold voltage when the gate length was 0.15 μm from the threshold voltage when m. For the nMOS, the threshold voltage difference ΔV _th was obtained under the condition that the drain voltage was 2 V, and for the pMOS, the threshold voltage difference ΔV _th was obtained under the condition that the drain voltage was −2 V. The threshold voltage difference ΔV _th is C, which is obtained by performing epitaxial growth of the silicon films 19a and 19b in two steps and using boron as a p-type impurity.
MOS, more specifically, the first-stage silicon film 19a
₁ , 19b ₁ are formed to a film thickness of 10 nm under the condition that the boron concentration in the films 19a ₁ and 19b ₁ is 2.4 × 10 ¹⁸ cm ^−3, and the second-stage silicon film 19a _{2 is formed} . 19b
₂ has a boron concentration of 5 in the films 19a ₂ and 19b _2.
20 μm, 30 μm, 40 under the condition of × 10 ¹⁶ cm ⁻³
It was determined for the nMOS and pMOS that constitute the CMOS manufactured by forming the film to have a film thickness of nm. Further, the nMOS and pMO constituting the CMOS manufactured without forming the second-stage silicon films 19a ₂ and 19b ₂ are formed.
The threshold voltage difference ΔV _{th with} respect to S was also obtained. Instead of forming the silicon films 19a and 19b, boron is further fluorinated on the surface of the silicon substrate 11 in the region where the nMOS is to be formed under the condition that the implantation energy is 45 KeV and the dose amount is 4 × 10 ¹² / cm ² . Boron implantation energy is 90 KeV and dose is 4 × 1
Under the condition of 0 ¹² / cm ² , ion implantation, and p
Boron fluoride is implanted into the surface of the silicon substrate 11 in the region where the MOS is to be formed under the conditions that the implantation energy is 10 KeV and the dose amount is 3 × 10 ¹² / cm ² , and further phosphorus is the implantation energy is 120 KeV and the dose amount is 2 ×. 10 ¹³ / c
The threshold voltage difference ΔV _{th with} respect to the nMOS and pMOS forming the CMOS manufactured by ion implantation under the condition of m ² was also obtained.

FIG. 9 is a characteristic diagram showing the relationship between the threshold voltage difference ΔV _th and the maximum transconductance G _{m max} obtained for the nMOS, and FIG. 10 is obtained for the pMOS. FIG. 6 is a characteristic diagram showing a relationship between a threshold voltage difference ΔV _th and a maximum value G _{m max} of mutual conductance. The horizontal axis of FIGS. 9 and 10 indicates the maximum value of mutual conductance G _{m max.}
(ΜS / μm), and the vertical axis shows the threshold voltage difference ΔV _th (V). 9 and 10
In the figure, point a is the second-stage silicon film 19a ₂ , 19b ₂
Shows the result in the case of not forming, the points b to d are the second
The silicon films 19a ₂ and 19b ₂ at the step of 20 nm and 30
The results are shown in the case of forming films with a thickness of 40 nm and 40 nm, respectively. Point e shows the result when the ion implantation is performed as described above. The maximum value G _{m max} of the mutual conductance at a point ~d point indicates the maximum value of the transconductance G _m determined in G _m -V _G characteristics described above. That is, in the nMOS, the gate length is 1 μm and the drain voltage is 0.1V.
The maximum value of the transconductance G _m obtained in conditions is, in pMOS, a gate length is 1 [mu] m, the maximum value of the transconductance G _m of the drain voltage is obtained in the condition is -0.1V ing. Similarly, the maximum value G _{m max} of the mutual conductance at point e is
Then, the gate length is 1 μm, and the drain voltage is 0.1
The maximum value of the transconductance G _m obtained in in a condition V, the pMOS, a gate length of 1 [mu] m, and the maximum value of the transconductance G _m of the drain voltage is obtained in the condition is -0.1V There is.

As can be seen from FIG. 9, in the nMOS, the absolute value of the threshold voltage difference ΔV _th is the largest when the second-stage silicon film 19a ₂ is not formed. The absolute value of the threshold voltage difference ΔV _th decreases as the film thickness of the silicon film 19a ₂ in the second stage increases. Second
The threshold voltage difference ΔV _th when the stepped silicon film 19b ₂ is formed to a film thickness of 20 nm to 40 nm is approximately the same as the threshold voltage difference ΔV _th when ion implantation is performed.
This means that the silicon film 19b ₂ of the second stage has a thickness of 20 nm.
It is shown that the short channel effect does not easily occur as compared with the conventional case even if the film is formed with a film thickness of up to 40 nm. In the case of nMOS, the second stage silicon film 19 is used.
The mutual conductance G _m when the a ₂ is not formed is the smallest. Then, the transconductance G _m increases as the film thickness of the silicon film 19a ₂ in the second stage increases. The second stage silicon film 19a ₂ is formed with a thickness of ₂₀ nm to 40 nm.
transconductance G _m when formed to a film thickness of nm
Is the transconductance G _m when ion implantation is performed
Greater than. Therefore, when the second-stage silicon film 19a ₂ is formed to have a film thickness of 20 nm to 40 nm, high speed operation becomes possible without the short channel effect being likely to occur.

On the other hand, as can be understood from FIG. 10, pM
In OS, the threshold voltage difference ΔV _th is smallest when the second-stage silicon film 19b ₂ is not formed. The threshold voltage difference ΔV _th increases as the film thickness of the silicon film 19b ₂ in the second stage increases. Threshold voltage difference [Delta] V _th in the case of forming a silicon film 19b ₂ of the second stage to a thickness of 20nm~30nm, the threshold voltage difference [Delta] V of the case of not forming the silicon film 19b ₂ of the second stage
slightly larger than _th , the second stage silicon film 19b ₂
Voltage difference ΔV when the film is formed to a film thickness of 40 nm
_th is a threshold voltage difference ΔV _th when ion implantation is performed
Is about the same. Further, in the pMOS, the mutual conductance G _m is smallest when the second-stage silicon film 19b ₂ is not formed. Then, as the film thickness of the second-stage silicon film 19b ₂ becomes larger, the mutual conductance G
_m becomes large. The second-stage silicon film 19b ₂ is formed as 20
The mutual conductance G _m when the film is formed to have a film thickness of nm to 40 _nm is larger than the mutual conductance G _m when the ion implantation is performed. Therefore, the second stage silicon film 1
When 9b ₂ is formed to a film thickness of 20 nm to 30 nm, the short channel effect is unlikely to occur and high speed operation becomes possible.

2. Second Embodiment FIGS. 11 and 12 are explanatory views in the case of manufacturing a CMOS. Specifically, it is a process diagram in the case of manufacturing a CMOS in which a pMOS and an nMOS are adjacent to each other, and is a cross-sectional view of a sample in a main process in the manufacturing process, taken along the gate length (however, FIG. 4 is a process diagram shown by (a drawing focusing on a cut end). However, in order to avoid complication of the drawing, some hatching showing the cross section is omitted.

First, similarly to the case of the first embodiment, the P well 13a and the N well 13b are formed on the silicon substrate 11, the element isolation insulating film 15 is formed on the silicon substrate 11, and the region 17a is formed. Punch-through suppression implanter, channel implanter, and punch-through suppression implanter for the region 17b (see FIG. 11).
(A)).

Next, this sample is heat-treated at a temperature of, for example, 900 ° C. for 1 minute to recrystallize the surface of the silicon substrate 11 which has been made amorphous by ion implantation. afterwards,
On this sample, a silicate glass film 37 containing p-type impurities is formed to a thickness of 100 nm by the CVD method (FIG. 11B). Silicate glass film 3 containing p-type impurities
As an example, a BSG (Boron Silicate Glass) film is used as the BSG film 7. As the BSG film, for example, silane as a silicon source and diborane as a boron source are used.
The molar concentration of B ₂ O _{3 in} Example 7 is, for example, 18 mol%
It can be formed at a temperature of, for example, 400 ° C. by mixing as a reaction gas under various conditions.

Next, this sample was subjected to a rapid heating device,
For example, heat treatment is performed at a temperature of 950 ° C. for 5 seconds. In this heat treatment, boron contained in the silicate glass film 37 is solid-phase diffused from the film 37 to the silicon substrate 11, so that the surface layer of the silicon substrate 11 has a boron concentration of, for example, 2.4 × 10 ¹⁸ cm ^−3. Diffusion regions 39a and 39b are formed to some extent. After that, the silicate glass film 37 is removed by etching (FIG. 12A).

Then, silicon films 19a and 19b containing p-type impurities are formed by UHV-CVD on the surface of the silicon substrate in the region where the nMOS is to be formed and the surface of the silicon substrate in the region where the pMOS is to be formed. It is formed by epitaxial growth to a film thickness of 10 to 50 nm so that the p-type impurity concentration therein becomes lower than the p-type impurity concentration of the diffusion regions 39a and 39b (FIG. 12).
(B)). As an example of forming the silicon films 19a and 19b in one step and using boron as the p-type impurity, the silicon films 19a and 19b include, for example, silane or disilane serving as a silicon source and diborane serving as a p-type impurity source. The films 19a and 19b are mixed under the condition that the boron concentration is, for example, 5 × 10 ¹⁶ cm ⁻³ and used as a reaction gas. For example, the reaction gas pressure is 10 ⁻⁴ Torr
It can be formed by epitaxial growth at a substrate temperature of 500 to 700 ° C. and a film thickness of 10 to 50 nm. When forming the silicon films 19a and 19b that do not contain p-type impurities, for example, silane or disilane serving as a silicon source may be used as a reaction gas.

After that, as in the case of the first embodiment, formation of a gate oxide film, formation of a gate electrode, formation of a shallow junction source / drain region, formation of a first side wall film, and formation of a deep junction are performed. Source / drain regions are formed and impurities are driven in. As described above, a CMOS having a fine gate length can be manufactured.

When the CMOS is manufactured as described above, as in the case of the first embodiment, the nMOS and pM are formed.
High-speed operation is possible in the OS, and pMOS
In, the short channel effect is less likely to occur.

[0058]

As is apparent from the above description, according to the first pMOS manufacturing method of the present invention, the pMOS is manufactured.
A silicon film containing a p-type impurity is epitaxially grown on the surface of the silicon substrate in the formation-destined region so that the p-type impurity concentration in the silicon film becomes higher toward the surface of the silicon substrate.

According to the second pMOS manufacturing method of the present invention, after the silicate glass film containing the p-type impurity is formed on the surface of the silicon substrate in the pMOS formation planned region, heat treatment is performed to form the silicate glass. The p-type impurity contained in the film is diffused into the silicon substrate to form a p-type impurity diffusion region in the surface layer of the silicon substrate. Then, after removing the silicate glass film, a silicon film containing a p-type impurity is formed on the surface of the silicon substrate in the pMOS formation planned region so that the p-type impurity concentration in the silicon film is higher than the p-type impurity concentration in the diffusion region. It is formed by epitaxial growth so that it becomes lower.

When a pMOS is manufactured by these methods,
The influence of carrier surface scattering is reduced, and high-speed operation becomes possible. Furthermore, when the channel is formed in a region centered on a position close to the surface, the depletion layer charge is easily controlled by the gate voltage, and the short channel effect is less likely to occur.

Further, according to the first CMOS manufacturing method of the present invention, a silicon film containing a p-type impurity is formed on the surface of the silicon substrate in the pMOS formation planned region and on the surface of the silicon substrate in the nMOS formation planned region. The silicon film is epitaxially grown so that the p-type impurity concentration in the silicon film increases toward the surface of the silicon substrate.

Further, according to the second CMOS manufacturing method of the present invention, a silicate glass film containing p-type impurities is formed on the surface of the silicon substrate in the pMOS formation planned region and on the surface of the silicon substrate in the nMOS formation planned region. After forming, the p-type impurity contained in the silicate glass film is diffused into the silicon substrate to form a p-type impurity diffusion region in the surface layer of the silicon substrate. Then, after removing the silicate glass film, a silicon film containing p-type impurities is formed on the surface of the silicon substrate in the pMOS formation planned region and on the surface of the silicon substrate in the nMOS formation planned region in the p-type silicon film. It is formed by epitaxial growth so that the impurity concentration becomes lower than the p-type impurity concentration in the diffusion region.

When a CMOS is manufactured by these methods,
With respect to the pMOS forming the CMOS, the influence of carrier surface scattering is reduced, and high-speed operation becomes possible. Furthermore, when the channel is formed in a region centered on a position close to the surface, the depletion layer charge is easily controlled by the gate voltage, and the short channel effect is less likely to occur. In addition, the nMOS forming the CMOS is less affected by the impurity scattering of electrons and can operate at high speed. As described above, both the nMOS and the pMOS can operate at high speed, and the short channel effect hardly occurs in the pMOS.

[Brief description of drawings]

1A to 1C are CMOs of the first embodiment.
It is a manufacturing process drawing of S.

2A to 2C are manufacturing process diagrams of the CMOS according to the first embodiment, following FIG. 1;

3A to 3C are manufacturing process diagrams of the CMOS according to the first embodiment, which is subsequent to FIG. 2;

FIG. 4 is a manufacturing process diagram of the CMOS according to the first embodiment, following FIG. 3;

FIG. 5 is an impurity profile for an nMOS forming a CMOS.

FIG. 6 is an impurity profile for a pMOS forming a CMOS.

7 (A) is an I _D -V _G characteristics for nMOS constituting the CMOS, (B), the G _m for nMOS constituting the CMOS - a V _G characteristics.

8 (A) is an I _D -V _G characteristics for pMOS constituting the CMOS, (B), the G _m for pMOS constituting the CMOS - a V _G characteristics.

FIG. 9 is a characteristic diagram showing the relationship between the threshold voltage difference ΔV _th and the maximum transconductance value G _{m max} for an nMOS forming a CMOS.

FIG. 10 is a threshold voltage difference ΔV _th and a maximum transconductance value G _{m max} for a pMOS forming a CMOS.
FIG. 4 is a characteristic diagram showing a relationship between

11A and 11B are C of the second embodiment.
It is a manufacturing process figure of MOS.

FIG. 12 (A) and FIG. 12 (B) are the second part following FIG. 11.
FIG. 6 is a manufacturing process diagram of the CMOS according to the embodiment.

[Explanation of symbols]

11: Silicon substrate N: nMOS forming region P: pMOS forming region 15: element separating insulating films 19a, 19b: silicon film 19a _1, 19b _1: silicon of the first stage membrane 19a _2, 19b _2: second Stage silicon film 21a, 21b: Gate oxide film 23a, 23b: Polysilicon film 25a, 25b: Tungsten silicide film 27a, 27b: Gate electrode 29a: Shallow junction n-type source / drain region 29b: Shallow junction p-type Source / drain region 35a: n-type source / drain region with deep junction 35b: p-type source / drain region with deep junction 37: silicate glass film 39a, 39b: diffusion region

Claims (12)

[Claims] 1. In manufacturing a pMOS using a silicon substrate, an insulating film for element isolation is formed on the silicon substrate,
a step of determining a pMOS formation planned region, and a step of defining a pMOS formation planned region on the surface of the silicon substrate
A silicon film containing p-type impurities is replaced with p
Forming epitaxially so that the type impurity concentration becomes higher toward the surface of the silicon substrate, forming a gate oxide film on the silicon film, and forming a gate electrode on the gate oxide film. A method of manufacturing a pMOS, which includes a step of forming and a step of forming a source and a drain after that. 2. The pMOS manufacturing method according to claim 1, wherein the epitaxial growth of the silicon film is performed in n stages (where n is 2).
Is an integer greater than or equal to. ). 3. The method of manufacturing a pMOS according to claim 1, wherein the epitaxial growth of the silicon film is performed in n steps, wherein the epitaxial growth of the silicon film in the first step is performed with a p-type impurity concentration of 1 × 10. A pMOS manufacturing method characterized in that the p-type impurity concentration is 1 × 10 ¹⁷ cm ^-3 or less by performing epitaxial growth of a silicon film in the final stage so that the p-type impurity concentration is ¹⁸ cm ^-3 or more. , N is an integer of 2 or more.). 4. When manufacturing a pMOS using a silicon substrate, an insulating film for element isolation is formed on the silicon substrate,
a step of determining a pMOS formation planned region, and a step of defining a pMOS formation planned region on the surface of the silicon substrate
a step of forming a silicate glass film containing p-type impurities, and then performing a heat treatment to diffuse the p-type impurities contained in the silicate glass film into the silicon substrate to form p-type impurities on the surface layer of the silicon substrate. A step of forming an impurity diffusion region, and thereafter, after removing the silicate glass film,
A silicon film containing p-type impurities is epitaxially grown on the surface of the silicon substrate in the MOS formation region such that the p-type impurity concentration in the silicon film is lower than the p-type impurity concentration in the diffusion region. And a step of forming a gate oxide film on the silicon film, a step of forming a gate electrode on the gate oxide film, and a step of forming a source and a drain after that. Method for manufacturing pMOS. 5. The method of manufacturing a pMOS according to claim 4, wherein the epitaxial growth of the silicon film is performed in m stages, in which the p-type impurity concentration in the silicon film increases toward the surface of the silicon substrate. PMOS manufacturing method characterized in that it is performed so that
m is an integer of 1 or more. ). 6. The method for manufacturing a pMOS according to claim 4, wherein the p-type impurity contained in the silicate glass film is diffused into the silicon substrate, and the p-type impurity concentration of the diffusion region is 1 × 10. ^The silicon film is grown to ¹⁸ cm ^-3 or more, and the silicon film is epitaxially grown in m steps. At that time, the silicon film is epitaxially grown in the final step so that the p-type impurity concentration is 1 × 10 ¹⁷ cm ^-3 or less. PMOS manufacturing method (where m is an integer of 1 or more). 7. When manufacturing a CMOS using a silicon substrate, an insulating film for element isolation is formed on the silicon substrate,
determining a pMOS formation planned region and an nMOS formation planned region, on the surface of the silicon substrate in the pMOS formation planned region and on the surface of the silicon substrate in the nMOS formation planned region,
A silicon film containing p-type impurities is replaced with p
Forming epitaxially so that the type impurity concentration becomes higher toward the surface of the silicon substrate, forming a gate oxide film on the silicon film, and forming a gate electrode on the gate oxide film. A method of manufacturing a CMOS, comprising: a forming step; and then a step of forming a source and a drain. 8. The method of manufacturing a CMOS according to claim 7, wherein the epitaxial growth of the silicon film is performed in n steps (where n is 2).
Is an integer greater than or equal to. ). 9. The method of manufacturing a CMOS according to claim 7, wherein the epitaxial growth of the silicon film is performed in n steps, and the epitaxial growth of the silicon film in the first step is performed with a p-type impurity concentration of 1 × 10. ^A method for manufacturing a CMOS, characterized in that the epitaxial growth of a silicon film is performed at a final step of ¹⁸ cm ⁻³ or more so that the p-type impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or less (however, , N is an integer of 2 or more.). 10. When manufacturing a CMOS using a silicon substrate, an insulating film for element isolation is formed on the silicon substrate,
determining a pMOS formation planned region and an nMOS formation planned region, on the surface of the silicon substrate in the pMOS formation planned region and on the surface of the silicon substrate in the nMOS formation planned region,
a step of forming a silicate glass film containing p-type impurities, and then performing a heat treatment to diffuse the p-type impurities contained in the silicate glass film into the silicon substrate to form p-type impurities on the surface layer of the silicon substrate. A step of forming an impurity diffusion region, and thereafter, after removing the silicate glass film,
On the surface of the silicon substrate in the MOS formation region and the n
A silicon film containing p-type impurities is epitaxially grown on the surface of the silicon substrate in the MOS formation region so that the p-type impurity concentration in the silicon film is lower than the p-type impurity concentration in the diffusion region. And a step of forming a gate oxide film on the silicon film, a step of forming a gate electrode on the gate oxide film, and a step of forming a source and a drain after that. And a method of manufacturing a CMOS. 11. The method of manufacturing a CMOS according to claim 10, wherein the epitaxial growth of the silicon film is performed in m steps, and as the p-type impurity concentration in the silicon film increases toward the surface of the silicon substrate. A method of manufacturing a CMOS, which is characterized by performing it so as to be high (however,
m is an integer of 1 or more. ). 12. The method of manufacturing a CMOS according to claim 10, wherein the p-type impurity contained in the silicate glass film is diffused into the silicon substrate, and the p-type impurity concentration of the diffusion region is 1 × 10. ^The silicon film is grown to ¹⁸ cm ^-3 or more, and the silicon film is epitaxially grown in m steps. At that time, the silicon film is epitaxially grown in the final step so that the p-type impurity concentration is 1 × 10 ¹⁷ cm ^-3 or less. A method of manufacturing a CMOS, wherein m is an integer of 1 or more.