JPH09251996A5 - - Google Patents

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Publication number
JPH09251996A5
JPH09251996A5 JP1996181297A JP18129796A JPH09251996A5 JP H09251996 A5 JPH09251996 A5 JP H09251996A5 JP 1996181297 A JP1996181297 A JP 1996181297A JP 18129796 A JP18129796 A JP 18129796A JP H09251996 A5 JPH09251996 A5 JP H09251996A5
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insulating film
semiconductor device
semiconductor
film
manufacturing
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JP1996181297A
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Japanese (ja)
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JP3565993B2 (en
JPH09251996A (en
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Priority claimed from JP18129796A external-priority patent/JP3565993B2/en
Publication of JPH09251996A publication Critical patent/JPH09251996A/en
Publication of JPH09251996A5 publication Critical patent/JPH09251996A5/ja
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【発明の名称】半導体装置及びその製造方法[Title of Invention] Semiconductor device and its manufacturing method

Claims (19)

金属導電層又は半導体層を形成
前記金属導電層又は前記半導体層を覆うように絶縁膜をCVD法により形成
前記絶縁膜をエッチングしてコンタクトホールを形成すること特徴とする半導体装置の製造方法において、
前記絶縁膜のエッチングレートが上層に行くに従って段階的に又は連続的に増加するように前記絶縁膜を形成することを特徴とする半導体装置の製造方法。
forming a metal conductive layer or a semiconductor layer;
forming an insulating film by a CVD method so as to cover the metal conductive layer or the semiconductor layer;
A method of manufacturing a semiconductor device, characterized in that the insulating film is etched to form contact holes,
A method of manufacturing a semiconductor device, comprising forming the insulating film so that the etching rate of the insulating film increases stepwise or continuously toward the upper layer.
請求項1において、前記絶縁膜は、酸化珪素からなることを特徴とする半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is made of silicon oxide. 請求項1または2において、rf出力を段階的に又は連続的に減少させることによって前記絶縁膜を形成することを特徴とする半導体装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed by reducing the RF output stepwise or continuously. 金属導電層又は半導体層を形成
前記金属導電層又は前記半導体層を覆うように第1の絶縁膜をCVD法により形成
前記第1の絶縁膜上に第2の絶縁膜をCVD法により形成し
前記第1の絶縁膜及び前記第2の絶縁膜をエッチングしてコンタクトホールを形成すること特徴とする半導体装置の製造方法において、
前記第2の絶縁膜のエッチングレートが上層に行くに従って段階的又は連続的に増加するように前記第2の絶縁膜を形成することを特徴とする半導体装置の製造方法。
forming a metal conductive layer or a semiconductor layer;
forming a first insulating film by a CVD method so as to cover the metal conductive layer or the semiconductor layer;
forming a second insulating film on the first insulating film by a CVD method;
a contact hole formed by etching the first insulating film and the second insulating film ,
A method for manufacturing a semiconductor device, comprising forming the second insulating film so that the etching rate of the second insulating film increases stepwise or continuously toward the upper layer.
請求項4において、前記第1の絶縁膜は、窒化珪素または酸化窒化珪素からなることを特徴とする半導体装置の製造方法。5. A method for manufacturing a semiconductor device according to claim 4, wherein the first insulating film is made of silicon nitride or silicon oxynitride. 請求項4または5において、前記第2の絶縁膜は、酸化珪素からなることを特徴とする半導体装置の製造方法。6. A method for manufacturing a semiconductor device according to claim 4, wherein the second insulating film is made of silicon oxide. 請求項4乃至6のいずれか一において、rf出力を段階的に又は連続的に減少させることによって前記第2の絶縁膜を形成することを特徴とする半導体装置の製造方法。 7. The method for manufacturing a semiconductor device according to claim 4, wherein the second insulating film is formed by reducing the RF output stepwise or continuously. 請求項1乃至7のいずれか一において、前記CVD法はプラズマCVD法であることを特徴とする半導体装置の製造方法。8. The method for manufacturing a semiconductor device according to claim 1, wherein the CVD method is a plasma CVD method. 基板と、基板上に形成された絶縁膜と、を有する半導体装置において、A semiconductor device having a substrate and an insulating film formed on the substrate,
前記絶縁膜は、配線を形成するためのコンタクトホールが形成されており、The insulating film has contact holes formed therein for forming wiring,
前記絶縁膜のエッチングレートは、上層に行くに従って段階的に又は連続的に増加していることを特徴とする半導体装置。The semiconductor device is characterized in that the etching rate of the insulating film increases stepwise or continuously toward the upper layer.
請求項9において、前記絶縁膜は、酸化珪素からなることを特徴とする半導体装置。10. The semiconductor device according to claim 9, wherein the insulating film is made of silicon oxide. 基板と、基板上に形成された第1の絶縁膜と、前記第1の絶縁膜上に形成された第2の絶縁膜と、を有する半導体装置において、A semiconductor device having a substrate, a first insulating film formed on the substrate, and a second insulating film formed on the first insulating film,
前記第1の絶縁膜および前記第2の絶縁膜は、配線を形成するためのコンタクトホールが形成されており、the first insulating film and the second insulating film have contact holes formed therein for forming wiring;
前記第2の絶縁膜のエッチングレートは、上層に行くに従って段階的に又は連続的に増加していることを特徴とする半導体装置。The semiconductor device is characterized in that the etching rate of the second insulating film increases stepwise or continuously toward the upper layer.
請求項11において、前記第1の絶縁膜は、窒化珪素または酸化窒化珪素からなることを特徴とする半導体装置。12. The semiconductor device according to claim 11, wherein the first insulating film is made of silicon nitride or silicon oxynitride. 請求項11または12において、前記第2の絶縁膜は、酸化珪素からなること13. The method according to claim 11, wherein the second insulating film is made of silicon oxide. を特徴とする半導体装置。A semiconductor device characterized by: 基板と、基板上に形成された下地膜と、前記下地膜上に形成された半導体膜と、前記半導体膜上に形成されたゲイト絶縁膜と、前記ゲイト絶縁膜上に形成されたゲイト電極と、前記半導体膜及び前記ゲイト電極を覆うように形成された層間絶縁膜と、を有する半導体装置において、A semiconductor device having a substrate, an underlayer film formed on the substrate, a semiconductor film formed on the underlayer film, a gate insulating film formed on the semiconductor film, a gate electrode formed on the gate insulating film, and an interlayer insulating film formed to cover the semiconductor film and the gate electrode,
前記層間絶縁膜は、前記半導体膜または前記ゲイト電極に接続される配線を形成するためのコンタクトホールが形成されており、the interlayer insulating film has contact holes formed therein for forming wiring connected to the semiconductor film or the gate electrode;
前記層間絶縁膜のエッチングレートは、上層に行くに従って段階的に又は連続的に増加していることを特徴とする半導体装置。The semiconductor device is characterized in that the etching rate of the interlayer insulating film increases stepwise or continuously toward the upper layer.
請求項14において、前記層間絶縁膜は、酸化珪素からなることを特徴とする半導体装置。15. The semiconductor device according to claim 14, wherein the interlayer insulating film is made of silicon oxide. 基板と、基板上に形成された下地膜と、前記下地膜上に形成された半導体膜と、前記半導体膜上に形成されたゲイト絶縁膜と、前記ゲイト絶縁膜上に形成されたゲイト電極と、前記半導体膜及び前記ゲイト電極を覆うように形成された第1の層間絶縁膜と、前記第1の層間絶縁膜上に形成された第2の層間絶縁膜と、を有する半導体装置において、A semiconductor device having a substrate, an underlayer film formed on the substrate, a semiconductor film formed on the underlayer film, a gate insulating film formed on the semiconductor film, a gate electrode formed on the gate insulating film, a first interlayer insulating film formed so as to cover the semiconductor film and the gate electrode, and a second interlayer insulating film formed on the first interlayer insulating film,
前記第1の層間絶縁膜および前記第2の層間絶縁膜は、前記半導体膜または前記ゲイト電極に接続される配線を形成するためのコンタクトホールが形成されており、the first interlayer insulating film and the second interlayer insulating film have contact holes formed therein for forming wiring connected to the semiconductor film or the gate electrode;
前記第2の層間絶縁膜のエッチングレートは、上層に行くに従って段階的に又は連続的に増加していることを特徴とする半導体装置。The semiconductor device according to claim 1, wherein the etching rate of the second interlayer insulating film increases stepwise or continuously toward the upper layer.
請求項16において、前記第1の層間絶縁膜は、窒化珪素または酸化窒化珪素からなることを特徴とする半導体装置。17. The semiconductor device according to claim 16, wherein the first interlayer insulating film is made of silicon nitride or silicon oxynitride. 請求項16または17において、前記第2の層間絶縁膜は、酸化珪素からなる18. The method according to claim 16, wherein the second interlayer insulating film is made of silicon oxide. ことを特徴とする半導体装置。A semiconductor device characterized by: 請求項9乃至18のいずれか一において、前記コンタクトホールは、テーパー状であることを特徴とする半導体装置。19. The semiconductor device according to claim 9, wherein the contact hole is tapered.
JP18129796A 1995-06-20 1996-06-20 Method for manufacturing semiconductor device Expired - Fee Related JP3565993B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18129796A JP3565993B2 (en) 1995-06-20 1996-06-20 Method for manufacturing semiconductor device

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP17680195 1995-06-20
JP7-176801 1995-06-20
JP2054096 1996-01-10
JP8-20540 1996-01-10
JP18129796A JP3565993B2 (en) 1995-06-20 1996-06-20 Method for manufacturing semiconductor device

Publications (3)

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JPH09251996A JPH09251996A (en) 1997-09-22
JPH09251996A5 true JPH09251996A5 (en) 2004-07-08
JP3565993B2 JP3565993B2 (en) 2004-09-15

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JP2007053355A (en) * 2005-07-22 2007-03-01 Semiconductor Energy Lab Co Ltd Semiconductor device
EP1863090A1 (en) 2006-06-01 2007-12-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
JP2009053034A (en) * 2007-08-27 2009-03-12 Mitsumi Electric Co Ltd Semiconductor pressure sensor and manufacturing method thereof
WO2013190838A1 (en) * 2012-06-21 2013-12-27 パナソニック株式会社 Tft substrate, method for producing same, organic el display device, and method for manufacturing organic el display device
GB2539231B (en) * 2015-06-10 2017-08-23 Semblant Ltd Coated electrical assembly
GB201621177D0 (en) 2016-12-13 2017-01-25 Semblant Ltd Protective coating

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JPS62291064A (en) * 1986-06-11 1987-12-17 Oki Electric Ind Co Ltd Manufacture of thin film transistor
JPS63131542A (en) * 1986-11-20 1988-06-03 Nec Kansai Ltd Manufacture of semiconductor device
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