JPH09251996A5 - - Google Patents
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- Publication number
- JPH09251996A5 JPH09251996A5 JP1996181297A JP18129796A JPH09251996A5 JP H09251996 A5 JPH09251996 A5 JP H09251996A5 JP 1996181297 A JP1996181297 A JP 1996181297A JP 18129796 A JP18129796 A JP 18129796A JP H09251996 A5 JPH09251996 A5 JP H09251996A5
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- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor device
- semiconductor
- film
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【発明の名称】半導体装置及びその製造方法[Title of Invention] Semiconductor device and its manufacturing method
Claims (19)
前記金属導電層又は前記半導体層を覆うように絶縁膜をCVD法により形成し、
前記絶縁膜をエッチングしてコンタクトホールを形成することを特徴とする半導体装置の製造方法において、
前記絶縁膜のエッチングレートが上層に行くに従って段階的に又は連続的に増加するように前記絶縁膜を形成することを特徴とする半導体装置の製造方法。 forming a metal conductive layer or a semiconductor layer;
forming an insulating film by a CVD method so as to cover the metal conductive layer or the semiconductor layer;
A method of manufacturing a semiconductor device, characterized in that the insulating film is etched to form contact holes,
A method of manufacturing a semiconductor device, comprising forming the insulating film so that the etching rate of the insulating film increases stepwise or continuously toward the upper layer.
前記金属導電層又は前記半導体層を覆うように第1の絶縁膜をCVD法により形成し、
前記第1の絶縁膜上に第2の絶縁膜をCVD法により形成し、
前記第1の絶縁膜及び前記第2の絶縁膜をエッチングしてコンタクトホールを形成することを特徴とする半導体装置の製造方法において、
前記第2の絶縁膜のエッチングレートが上層に行くに従って段階的又は連続的に増加するように前記第2の絶縁膜を形成することを特徴とする半導体装置の製造方法。 forming a metal conductive layer or a semiconductor layer;
forming a first insulating film by a CVD method so as to cover the metal conductive layer or the semiconductor layer;
forming a second insulating film on the first insulating film by a CVD method;
a contact hole formed by etching the first insulating film and the second insulating film ,
A method for manufacturing a semiconductor device, comprising forming the second insulating film so that the etching rate of the second insulating film increases stepwise or continuously toward the upper layer.
前記絶縁膜は、配線を形成するためのコンタクトホールが形成されており、The insulating film has contact holes formed therein for forming wiring,
前記絶縁膜のエッチングレートは、上層に行くに従って段階的に又は連続的に増加していることを特徴とする半導体装置。The semiconductor device is characterized in that the etching rate of the insulating film increases stepwise or continuously toward the upper layer.
前記第1の絶縁膜および前記第2の絶縁膜は、配線を形成するためのコンタクトホールが形成されており、the first insulating film and the second insulating film have contact holes formed therein for forming wiring;
前記第2の絶縁膜のエッチングレートは、上層に行くに従って段階的に又は連続的に増加していることを特徴とする半導体装置。The semiconductor device is characterized in that the etching rate of the second insulating film increases stepwise or continuously toward the upper layer.
前記層間絶縁膜は、前記半導体膜または前記ゲイト電極に接続される配線を形成するためのコンタクトホールが形成されており、the interlayer insulating film has contact holes formed therein for forming wiring connected to the semiconductor film or the gate electrode;
前記層間絶縁膜のエッチングレートは、上層に行くに従って段階的に又は連続的に増加していることを特徴とする半導体装置。The semiconductor device is characterized in that the etching rate of the interlayer insulating film increases stepwise or continuously toward the upper layer.
前記第1の層間絶縁膜および前記第2の層間絶縁膜は、前記半導体膜または前記ゲイト電極に接続される配線を形成するためのコンタクトホールが形成されており、the first interlayer insulating film and the second interlayer insulating film have contact holes formed therein for forming wiring connected to the semiconductor film or the gate electrode;
前記第2の層間絶縁膜のエッチングレートは、上層に行くに従って段階的に又は連続的に増加していることを特徴とする半導体装置。The semiconductor device according to claim 1, wherein the etching rate of the second interlayer insulating film increases stepwise or continuously toward the upper layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18129796A JP3565993B2 (en) | 1995-06-20 | 1996-06-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17680195 | 1995-06-20 | ||
| JP7-176801 | 1995-06-20 | ||
| JP2054096 | 1996-01-10 | ||
| JP8-20540 | 1996-01-10 | ||
| JP18129796A JP3565993B2 (en) | 1995-06-20 | 1996-06-20 | Method for manufacturing semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH09251996A JPH09251996A (en) | 1997-09-22 |
| JPH09251996A5 true JPH09251996A5 (en) | 2004-07-08 |
| JP3565993B2 JP3565993B2 (en) | 2004-09-15 |
Family
ID=27283088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18129796A Expired - Fee Related JP3565993B2 (en) | 1995-06-20 | 1996-06-20 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3565993B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4627843B2 (en) * | 1999-07-22 | 2011-02-09 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| JP2005011920A (en) | 2003-06-18 | 2005-01-13 | Hitachi Displays Ltd | Display device and manufacturing method thereof |
| WO2007011061A1 (en) | 2005-07-22 | 2007-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2007053355A (en) * | 2005-07-22 | 2007-03-01 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| EP1863090A1 (en) | 2006-06-01 | 2007-12-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| JP2009053034A (en) * | 2007-08-27 | 2009-03-12 | Mitsumi Electric Co Ltd | Semiconductor pressure sensor and manufacturing method thereof |
| WO2013190838A1 (en) * | 2012-06-21 | 2013-12-27 | パナソニック株式会社 | Tft substrate, method for producing same, organic el display device, and method for manufacturing organic el display device |
| GB2539231B (en) * | 2015-06-10 | 2017-08-23 | Semblant Ltd | Coated electrical assembly |
| GB201621177D0 (en) | 2016-12-13 | 2017-01-25 | Semblant Ltd | Protective coating |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62291064A (en) * | 1986-06-11 | 1987-12-17 | Oki Electric Ind Co Ltd | Manufacture of thin film transistor |
| JPS63131542A (en) * | 1986-11-20 | 1988-06-03 | Nec Kansai Ltd | Manufacture of semiconductor device |
| JPS63112337U (en) * | 1987-01-12 | 1988-07-19 | ||
| JPH02201940A (en) * | 1989-01-30 | 1990-08-10 | Sumitomo Electric Ind Ltd | Interlayer insulation film and its manufacturing method |
| JP2842892B2 (en) * | 1989-07-04 | 1999-01-06 | 株式会社日立製作所 | Thin film transistor, method of manufacturing the same, matrix circuit substrate using the same, and image display device |
| JP2903134B2 (en) * | 1990-11-10 | 1999-06-07 | 株式会社 半導体エネルギー研究所 | Semiconductor device |
| JP2947535B2 (en) * | 1991-03-27 | 1999-09-13 | キヤノン株式会社 | Thin film semiconductor device, light receiving element and optical sensor |
| JPH05181159A (en) * | 1991-12-27 | 1993-07-23 | Toshiba Corp | Active matrix type liquid crystal display device |
| JP3387977B2 (en) * | 1993-05-20 | 2003-03-17 | 株式会社半導体エネルギー研究所 | Fabrication method of insulating film |
| JPH0778996A (en) * | 1993-09-07 | 1995-03-20 | Sony Corp | Method for manufacturing semiconductor device for display element substrate |
| JP3141979B2 (en) * | 1993-10-01 | 2001-03-07 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
-
1996
- 1996-06-20 JP JP18129796A patent/JP3565993B2/en not_active Expired - Fee Related
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