JPH09274603A - Serial data output device and input port of the device - Google Patents

Abstract

(57) [Abstract] [Problem] To increase the response speed of a serial port. SOLUTION: The first 6 bits are A0 to A5.
0 to A5, bit N of 2 ⁶ (= 64) bits port
Represents O (or address). The next 2 bits are C0 and C
1, the set of bits specified by C0 and C1 (0
1) and reset (00) are specified. In this way, it becomes possible to transfer at 9 μs at the transfer frequency (= 1 MHz) (conventional 65 μs), and the total transfer time can be greatly shortened. In addition to the set and reset, it is very convenient in practice if functions such as maintaining the current state (10) that does nothing and clearing all bits (11) are added.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data output device and its input port, and more particularly to a CP.
The present invention relates to an I / O unit of a U circuit, particularly a CPU peripheral circuit such as a PPC having a large number of I / O.

[0002]

2. Description of the Related Art In a copying machine, the number of input / output elements controlled is very large. However, there are many cases in which the high speed change of each input / output bit is not required. For this reason, in many cases, data is serialized and data is communicated with the CPU in clock synchronization with an eraser, key input on the operation unit display, etc. (see Japanese Patent Laid-Open No. 6-282153). In other fields, serialization of data input / output has great merit in terms of reducing the number of pins in the package and reducing costs.
For example, the advantages of serialization include simplification of patterns in the PWB and deletion of the number of harnesses.

[0003]

However, the drawback of serialization is that many bits are sent out in sequence, which slows the response speed. FIG. 7 is a diagram for explaining a conventional clock-synchronized data transfer system. In FIG. 7, for example, when 64-bit data is transferred in synchronization with a clock, it takes 65 μs including the time until latching. Shows. The present invention has been made in view of the above circumstances, and has been made for the purpose of increasing the response speed even though it is a serial port.

[0004]

According to a first aspect of the present invention, in a serial port of a type in which serial data is exchanged in synchronization with a clock, the structure of the data transmitted in synchronization with the clock is "port number of transfer destination ( Address part) and a "data part for controlling the contents of a specified port", and the sending operation on the output side is performed by the writing part such as a CPU triggered by writing to the sending buffer. The present invention is characterized in that it has means to operate only necessary bits and enables bit operation at a high response speed.

According to a second aspect of the present invention, as the input port connected to the serial port of the serial data output device according to the first aspect, there is a detecting means for detecting a change in the input level of the input port and a level change. The port number (address) is detected, and 2 of the port number and the change contents of the port
A data dividing means for dividing the data into two parts, and a transfer means for transferring the change data in synchronization with a clock toward the receiving side (CPU section etc.) triggered by the change in the input level. Therefore, only the bit information that has changed in the input port is transferred as serial data according to the change, and the response speed is increased.

According to a third aspect of the present invention, in the serial data output device according to the first aspect, write means for writing data from a plurality of units to a transmission buffer and a priority order are provided between the plurality of units to transfer lower data. When there is a write from the upper unit, the lower data transfer is immediately stopped and the transfer means for transferring the data of the upper unit and the lower data transfer which has been stopped after the data transfer of the upper unit are completed. It is characterized in that it has a means for performing again, so that when there is a bit operation request with a high priority, it can immediately respond and a response speed is improved.

[0007]

FIG. 1 is a diagram for explaining one embodiment of the present invention. First, the first 6 bits are A0 to A5.
Then, A0 to A5 represent the bit NO (or address) of the 2 ⁶ (= 64) bit port. Next 2 bits
Are C0 and C1, and specify the set (0 1) and reset (0 0) of the bits designated by C0 and C1. In addition to the bit-unit set / reset, it is very convenient in practice if functions such as maintaining the current state of doing nothing (10) and clearing all bits (11) are added. In this example,
With the same transfer frequency (= 1 MHz) as in FIG. 7, transfer is possible in 9 μs, and the total transfer time can be greatly reduced.

FIG. 2 is a block diagram for explaining an embodiment of the hardware configuration of the present invention. In the figure, 1 is a shift register, 2 is a decoder, 3 is an AND circuit, and 4 is a pulse control circuit. Then, shift register 1 which is a transfer buffer
AND of the output of the decoder 2 and the WR pulse (actually a negative logic) is taken by the AND circuit 3 and the LSBD of the data bus is selected.
Address 0 to 0 at the same time as 0 latch (data load)
A5 is also latched by the shift register 1. In the present embodiment, the 64-bit transfer data is represented by A0 to A5. 6
It is assigned to the LSB of four addresses. Most of the actual I / O operations are bit operations, so this configuration is more convenient. The latch pulse simultaneously activates the pulse control circuit 4 and outputs a shift clock to the shift register 1. After the serial output of 8 bits is output from the shift register 1, the pulse control circuit 4 outputs a latch pulse.

FIG. 3 is a block diagram for explaining another embodiment of the present invention. This circuit receives 63 bits in parallel as an input port around the CPU, converts it into serial data, and outputs it. The serial output is transmitted to the CPU side. If any of the 63 bits P0 to P62 is changed, the edge detection circuit 5 detects it and the latch circuit 6 latches it. The 63 latched results are output by the priority encoder 7 as the 6-bit data of the edge detection port having the smallest number.

For example, when an edge is detected at P13 and P15, only P13 is selected and P13 → 0011.
It is output as 01 bit data. The multiplexer 8 selects the selected port number data, and the shift register 9 selects the selected data and port number.
Then, the port number and data are serially formatted (see FIG. 1) and transferred to the CPU side. This series of output sequences is the transfer control unit 10
To control. When the 6-bit data output from the priority encoder 7 is P63, it indicates that no edge is detected. For other data, the data is loaded into the shift register 9 and the data is serially output. After output, transfer control unit 10
Outputs an end signal, clears the latch data of the port number that has ended through the decoder 11, and starts the next processing.
In this way, when there is a change in the port, data can be transferred immediately and no other transfers are needed.

FIG. 4 is a block diagram for explaining still another embodiment of the present invention. In the register 12, bit operation data (bit number, operation content) required to operate at high speed is latched. Is stored. The register 13 stores data in the same format as the register 12 by the WR pulse. The register 12 stores data of a port that operates at high speed by a hardware operation such as phase output of a pulse motor. The register 13 has a CPU
The data used as a normal port is stored by the software operation from. In the transfer control circuit 15, the register 12
The latch pulse or the WR signal is received, the corresponding data is selected by the multiplexer 14 and loaded into the shift register 16. After loading, data is transferred according to the transfer clock.

In this embodiment, the priority order of the data corresponding to the register 12 (hereinafter, channel 1) is set in the register 1
It is set higher than the data of 3 (hereinafter, channel 2). Therefore, as shown in the control state transition diagram of FIG. 5, when there is a transfer request of channel 1 during the data transfer of channel 2, the transfer of channel 2 is interrupted and the transfer of channel 1 is stopped.
Send the data. After the transmission of channel 1 is completed, the transmission of channel 2 is restarted from the beginning. FIG.
Shows a timing chart of the above embodiment, in which A in FIG.
0 to A5 are channel 2 addresses, B0 to B5 are
This is the address of channel 1.

[0013]

According to the first aspect of the present invention, in a serial port of a type that exchanges serial data in synchronization with a clock, the structure of the data to be transmitted in synchronization with the clock is "port number (address) of transfer destination". It is composed of the "data part to show" and the "data part to control the contents of the specified port", and the sending operation on the output side is performed by the CPU.
Since there is a means for writing to the transmission buffer from the writing unit such as etc., and only the necessary bits are operated, the bit operation with high response speed becomes possible.

According to the second aspect of the present invention, as the input port connected to the serial port of the serial data output device according to the first aspect, there is a detecting means for detecting a change in the input level of the input port, and there is a level change. A port number (address) for detecting the port number, and a data dividing unit that divides the data into two parts, the port number and the change content of the port,
Receiving side (CPU
A transfer unit for transferring the changed data in synchronism with a clock, and only the bit information that has changed in the input port is transferred as serial data according to the change. Get faster

According to a third aspect of the present invention, in the serial data output apparatus according to the first aspect, a writing means for writing from a plurality of units to a transmission buffer and a priority order are provided between the plurality of units to transfer lower data. If there is a write from the upper unit, the transfer means for immediately stopping the lower data transfer and transferring the data of the upper unit, and the data transfer that has been stopped after the lower data transfer of the upper unit is completed. Since it is possible to immediately respond to a bit manipulation request having a high priority, the response speed is improved.

[Brief description of drawings]

FIG. 1 is a time chart for explaining an embodiment of the present invention.

FIG. 2 is a block diagram for explaining an example of a hardware configuration of the present invention.

FIG. 3 is a block diagram for explaining another embodiment of the present invention.

FIG. 4 is a block diagram for explaining still another embodiment of the present invention.

FIG. 5 is a state transition diagram of control according to the present invention.

FIG. 6 is a time chart of an example of the present invention.

FIG. 7 is a diagram showing a conventional clock synchronous data transfer system.

[Explanation of symbols]

1, 9, 16 ... Shift register, 2, 11 ... Decoder,
3 ... AND circuit, 4 ... Pulse control circuit, 5 ... Edge detection circuit, 6 ... Latch, 7 ... Priority encoder,
8, 14 ... Multiplexer, 10 ... Transfer control unit,
12, 13 ... Register, 15 ... Transfer control circuit.

Claims (3)

[Claims] 1. In a serial port that exchanges serial data in synchronization with a clock, data to be transmitted in synchronization with a clock is "a portion of data indicating a port number (address) of a transfer destination" and "of a designated port". A serial data output device, which comprises a data portion for controlling the contents, and performs a transmission operation on the output side from a writing unit such as a CPU triggered by writing to a transmission buffer. 2. An input port connected to the serial port of the serial data output device according to claim 1,
The input port detects the change in the input level of the input port and the port number (address) that has changed the level, and the data that divides the data into two parts, the port number and the change content of the port. Separating means and receiving side (CPU section etc.) triggered by the change of the input level
An input port characterized by having a transfer means for transferring the change data in synchronization with a clock. 3. The serial data output device according to claim 1, wherein a writing unit for writing from a plurality of units to a transmission buffer and a priority order are provided between the plurality of units, and a lower unit is transferred from a higher unit during a lower data transfer. When there is a write, it has a transfer means for immediately stopping the lower data transfer and transferring the data of the upper unit, and a means for performing the stopped lower data transfer again after the data transfer of the upper unit is completed. A serial data output device characterized by the above.