JPH0928077A - Switching regulator - Google Patents

Abstract

It is an object of the present invention to provide a switching regulator that can reduce the number of external elements to achieve miniaturization and can output a wide range of output current with high efficiency. An oscillator 27 of a switching regulator outputs an oscillation frequency fosc. Switching control circuit 3
2 outputs a pulse signal for switching-driving the output transistor 4 based on the oscillation frequency fosc. The smoothing circuit 33 smoothes and outputs the output signal output from the output transistor 4. The output control circuit 34, based on the output voltage Vout and the output current Iout of the smoothing circuit 33,
A control signal for controlling the duty of the pulse signal is output to the switching control circuit 32. The oscillator 27 is provided with a frequency adjusting circuit 35 that changes the oscillation frequency fosc so as to follow changes in the output current of the smoothing circuit 33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching regulator that controls an output voltage and an output current by controlling a pulse width of a pulse signal that drives an output transistor.

In a portable electronic device, a switching regulator incorporated as a power supply circuit generates various power supply voltages used in an internal circuit based on the power supply voltage of a battery. With such demands for downsizing and weight reduction of portable electronic devices, downsizing of batteries and reduction of voltage are required. Along with this, it is necessary to miniaturize the switching regulator and operate it with high efficiency.

[0003]

2. Description of the Related Art FIG. 10 shows an example of a conventional switching regulator. The switching regulator 1 is a control IC 3 to which the power supply Vcc is supplied from the battery 2.
And a large number of external elements.

The output signal of the control IC 3 is P
It is input to the gate of the output transistor 4 composed of a channel MOS transistor, and the source of the transistor 4 is supplied with the power supply Vcc from the battery 2.

The drain of the output transistor 4 is connected to the output terminal To through the output coil 5 and the output current detecting resistor Rs. The drain of the output transistor 4 is connected to the cathode of the diode 6, and the anode of the diode 6 is connected to the ground GND.

A capacitor 7 is provided between the output coil 5 and the resistor Rs.
Is connected to the ground GND via the output terminal To
Is the ground GN via the output voltage detection resistors RA1 and RA2.
D is connected. A load 8 is connected to the output terminal To.

The voltage at both terminals of the resistor Rs is input to the current detection amplifier 9 in the control IC 3, and the output signal of the current detection amplifier 9 is input to the inverting input terminal of the current control amplifier 10. A reference voltage is input to the non-inverting input terminal of the current control amplifier 10.

A phase compensation capacitance CP2 of an external element is connected between the input and output terminals of the current control amplifier 10 via an external terminal of the control IC 3, and the output signal of the current control amplifier 10 is compared by PWM. It is output to the device 11.

The voltage between the output voltage detecting resistors RA1 and RA2 is input to the inverting input terminal of the voltage controlling amplifier 12 in the control IC 3. Further, the reference voltage is input to the non-inverting input terminal of the voltage control amplifier 12.

A phase compensation capacitance CP1 of an external element is connected between the input and output terminals of the voltage control amplifier 12 via the external terminal of the control IC 3, and the output signal of the voltage control amplifier 12 is compared by PWM. It is output to the device 11.

The oscillator 13 in the control IC 3 is connected to an oscillation frequency setting resistor RT and an oscillation frequency setting capacitance CT of external elements via an external terminal of the control IC 3. Then, the output signal of the oscillator 13 is output to the PWM comparator 11.

The output signal of the PWM comparator 11 is output to the gate of the output transistor 4 via the output circuit 14. In the switching regulator 1 configured as above, when the output transistor 4 performs a switching operation based on the output signal of the output circuit 14, the pulsating current output from the output transistor 4 is output to the output coil 5, the capacitor 7, the resistor Rs, and the diode. It is smoothed by 6, and is output from the output terminal To as the output current Iout.

At this time, the resistance Rs is increased by the output current Iout.
The potential difference generated between the two terminals is input to the current detection amplifier 9, and the current detection amplifier 9 outputs a voltage signal based on the current value of the output current Iout to the current control amplifier 10.

The current control amplifier 10 outputs an output signal to the PWM comparator 11 based on the comparison between the output voltage of the current detection amplifier 9 and the reference voltage. The output terminal T
A voltage obtained by resistance-dividing the output voltage Vout output from o with resistors RA1 and RA2 is input to the voltage control amplifier 12, and the voltage control amplifier 12 compares the output signal based on the comparison between the input voltage and the reference voltage by PWM comparison. Output to the container 11.

An output signal having a constant frequency is input from the oscillator 13 to the PWM comparator 11. And PWM
The comparator 11 controls the duty of the pulse signal output to the output circuit 14 based on the output signal of the oscillator 13 and the output signals of the current control amplifier 10 and the voltage control amplifier 12, and the output circuit 14 performs PWM comparison. The output transistor 4 is driven based on the pulse signal output from the device 11.

By such an operation, the output voltage Vout of a constant voltage is output within a range in which the output current Iout does not exceed a certain value. At this time, since the phase compensation capacitors Cp2 and Cp1 are connected between the input and output terminals of the current control amplifier 10 and the voltage control amplifier 12, respectively, the oscillation of the output voltage Vout of the switching regulator 1 is prevented. It

That is, in the operation of a normal amplifier,
When the gain is "1" or more and the phase between the input and output is shifted by 180 degrees, oscillation occurs. Therefore, the phase compensation capacitors Cp2, Cp1
As a result, the frequency characteristics of the amplifiers 10 and 12 are lowered, and the gain in the high frequency region is lowered to prevent oscillation.

A concrete structure of the oscillator 13 is shown in FIG. The PNP transistors Tr1 and Tr2 form a current mirror circuit, and the collector current I1 flowing through the transistor Tr1 becomes a constant current set by the resistor RT based on the operation of the NPN transistor Tr3 driven by the buffer amplifier 15. Works like.

The collector current I2 flowing through the transistor Tr2 is the same as the collector current I1 of the transistor Tr1, and the node N1 which is the collector potential of the transistor Tr2 is output to the PWM comparator 11.

Further, the node N1 is connected to the ground GND via the current source 16 and the switch circuit 17, and is connected to the external capacitor CT. The current source 16 has a current 2I which is twice the collector current I2 of the transistor Tr2.
It has a current drive capability to pass 2.

Therefore, if the switch circuit 17 is turned off, the capacitance CT is charged by the collector current I2,
When the potential of the node N1 rises and the switch circuit 17 is turned on, the capacitance CT is discharged by the operation of the current source 16 and the potential of the node N1 falls. And the current source 16
Since the current drivability of is equal to twice the collector current I2, the slope of the increase in the potential of the node N1 is equal to the slope of the decrease in the potential.

The node N1 is connected to the first comparator 18a.
Is input to the non-inverting input terminal of the second comparator 18b and the inverting input terminal of the second comparator 18b. The first comparator 18a
The first set potential Va obtained by resistance-dividing the reference power source VREF with the resistors R1 and R2, R3 is input to the inverting input terminal of the second comparator 18b, and the reference power source VREF is input to the non-inverting input terminal of the second comparator 18b. The second set potential Vb divided by the resistors R1 and R2 and the resistor R3 is input.

The output signal of the first comparator 18a is the set signal input terminal S of the flip-flop circuit 19.
And the output signal of the second comparator 18b is input to the reset signal input terminal R of the flip-flop circuit 19.

The output signal Q of the flip-flop circuit 19 is output to the switch circuit 17, and the switch circuit 17 is driven based on the output signal. With this configuration, the switch circuit 17 is turned off, the potential of the node N1 rises, and when the potential of the node N1 reaches the first set potential Va, the output signal of the first comparator 18a becomes H level, By the output signal of the flip-flop circuit 19 based on the output signal, the switch circuit 1
7 is turned on.

Then, when the potential of the node N1 drops and then the potential of the node N1 reaches the second set potential Vb,
The output signal of the second comparator 18b becomes H level, and the switch circuit 17 is turned off by the output signal of the flip-flop circuit 19 based on the output signal. Then, the potential of the node N1 rises again, and the above operation is repeated.

Therefore, as shown in FIG. 12, a triangular wave oscillating between the first set potential Va and the second set potential Vb is generated at the node N1, and the frequency of the triangle wave is the resistance RT and the capacitance. It is set by CT. Then, the triangular wave is output to the PWM comparator 11.

[0027]

In the switching regulator 1 as described above, the current control amplifier 10 and the voltage control amplifier 12 are connected to the phase compensation capacitors Cp2 and Cp1 of external elements, respectively.

Therefore, the number of external elements increases, which hinders the downsizing of the switching regulator 1, which in turn hinders downsizing of electronic equipment in which the switching regulator 1 is mounted.

Particularly, in the control IC in which a large number of channels of such a switching regulator 1 are mounted, each switching regulator requires two phase compensation capacitors, which causes a problem that the number of external elements is further increased.

Further, in the electronic equipment in which the switching regulator 1 as described above is mounted, there is a large difference in current consumption between the normal operation and the standby operation, so that the width of the output current of the switching regulator 1 becomes large. Then, in order to reduce the size of the battery, it is desirable to secure high efficiency regardless of the increase or decrease of the output current.

Switching regulator 1 as described above
FIG. 13 shows the efficiency characteristics of. Here, the efficiency is the power supplied from the battery to the switching regulator,
It is the ratio of the power output from this switching regulator.

In the figure, the frequency f is the frequency of the pulse signal input to the gate of the output transistor 4, that is, the output signal frequency of the oscillator 13. For example, f = 2
In the range of 0 KHz to 350 KHz, the higher the frequency f, the larger the output current can be output with high efficiency, and the lower the frequency f, the smaller the output current can be output with high efficiency.

In order to output 1.5A when the output current Iout output from the switching regulator 1 to the load 8 during normal operation is 1.5A and the output current Iout during standby operation is 2mA. Is f = 3
It is most efficient at 50 KHz and most efficient at f = 20 KHz to output 2 mA.

Therefore, when the output frequency of the oscillator 13 is 350 KHz during the normal operation and the output frequency of the oscillator 13 is 20 KHz during the standby operation, the output current I
It is possible to output out efficiently.

However, in order to change the output frequency of the oscillator 13, it is necessary to change the values of the resistance RT and the capacitance CT, but since the resistance RT and the capacitance CT are external fixed elements, the output current Oscillator 1 according to Iout
The output frequency of 3 cannot be changed.

Therefore, it is not possible to output a wide range of output current with high efficiency. If the efficiency during the normal operation is secured, the efficiency during the standby operation is lowered, and if the efficiency during the standby operation is secured, the normal operation is performed. There is a problem that the efficiency during operation is reduced.

An object of the present invention is to provide a switching regulator which can reduce the number of external elements and can be miniaturized and can output a wide range of output current with high efficiency.

[0038]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the oscillator 27 of the switching regulator outputs the oscillation frequency fosc. The switching control circuit 32 outputs a pulse signal for switching and driving the output transistor 4 based on the oscillation frequency fosc. The smoothing circuit 33 smoothes and outputs the output signal output from the output transistor 4 by the switching operation of the output transistor 4. Output control circuit 34
Is an output voltage Vout and an output current I of the smoothing circuit 33.
Based on out, a control signal for controlling the duty of the pulse signal is output to the switching control circuit 32. The oscillator 27 is provided with a frequency adjusting circuit 35 for changing the oscillation frequency fosc so as to follow the change in the output current of the smoothing circuit 33.

According to a second aspect of the present invention, the oscillator includes a capacitor for outputting its charge / discharge potential as the oscillation frequency signal, a current mirror circuit for supplying a charging current to the capacitor, and a discharge circuit for discharging the capacitor. When the charging potential of the capacitance reaches a preset upper limit value, the capacitance is connected to the discharge circuit, and when the charging potential of the capacitance reaches a preset lower limit value, the capacitance is changed to the current mirror. A switching circuit connected to the circuit and a current control circuit for increasing or decreasing the output current of the current mirror circuit based on the output current of the smoothing circuit are provided.

According to a third aspect of the present invention, in the current control circuit, the input signal based on the output current of the smoothing circuit and the lower limit setting voltage for setting the lower limit value of the output current of the current mirror circuit are formed by a pair of NPN transistors. The first differential circuit input to the base, the potential of the emitter of the transistor that forms the first differential circuit, and the upper limit setting voltage that sets the upper limit value of the output current of the current mirror circuit are input. The emitter potential of the NPN transistor is
A second differential circuit that is input to the base of the NP transistor and a buffer amplifier that controls the output current of the current mirror circuit based on the potential of the emitter of the transistor that constitutes the second differential circuit are provided. Be prepared.

In the fourth aspect, the oscillator of the switching regulator outputs the oscillation frequency. The switching control circuit outputs a pulse signal for switching-driving the output transistor based on the oscillation frequency. The smoothing circuit smooths and outputs the output signal output from the output transistor by the switching operation of the output transistor. The output control circuit outputs a control signal for controlling the duty of the pulse signal to the switching control circuit based on the output voltage and the output current of the smoothing circuit. The output control circuit includes a current control amplifier that operates based on the output current of the smoothing circuit, and a voltage control amplifier that operates based on the output voltage of the smoothing circuit. The current control amplifier and the voltage control amplifier Are connected in series, and a phase compensation capacitor is connected between the input and output terminals of the voltage control amplifier connected in the subsequent stage.

(Operation) According to the first aspect, the frequency of the pulse signal for switching-driving the output transistor changes following the change in the output current.

In the second aspect, when the output current of the smoothing circuit changes, the output current of the current mirror circuit changes by the current control circuit, and when the output current of the current mirror circuit changes, the charging time of the capacitor changes. , The switching time by the switching circuit changes, and the oscillation frequency changes.

According to the present invention, the input voltage of the buffer amplifier changes between the lower limit setting voltage and the upper limit setting voltage following the signal based on the output current of the smoothing circuit and is based on the output current of the smoothing circuit. The signal and the lower limit setting voltage and the upper limit setting voltage are input to the buffer amplifier via the same number of transistors of the same type and polarity.

According to the present invention, the phase compensation of the current control amplifier and the voltage control amplifier is performed by one phase compensation capacitor connected between the input and output terminals of the voltage control amplifier.

[0046]

FIG. 2 shows one embodiment of a switching regulator embodying the present invention. The switching regulator of this embodiment is composed of a control IC 21 and an external element, and since the external element has the same configuration as the conventional example except for the phase compensation capacitance, the same reference numerals are given and the description thereof is omitted. Omit it.

The potential difference between both terminals of the output current detecting resistor Rs is inputted to the current detecting amplifier 22 in the control IC 21, and an output signal based on the potential difference is outputted to the current controlling amplifier 23.

The output voltage of the current detection amplifier 22 increases linearly with the increase of the output current Iout output to the load 8 as shown in FIG. The output signal of the current control amplifier 23 is input to the inverting input terminal of the voltage control amplifier 25 via the diode 24, and the inverting input terminal also includes a voltage obtained by resistance division of the output voltage Vout by the resistors RA1 and RA2. Is entered.

The output signal of the voltage control amplifier 25 is
The voltage is input to the PWM comparator 26, and the same voltage control amplifier 25 is input.
A phase compensation capacitance Cp of an external element is connected between the inverting input terminal and the output terminal.

The output signal of the current detection amplifier 22 is input to the oscillator 27, and the output signal of the oscillator 27 is PWM.
It is output to the comparator 26. Then, the PWM comparator 26 outputs a pulse signal to the output circuit 28 based on the output frequency of the oscillator 27 and the output signal of the voltage control amplifier 25, and the frequency of the pulse signal is the oscillation frequency of the oscillator 27, The duty is controlled based on the output signal of the voltage control amplifier 25.

The output stage of the output circuit 28 is constructed as shown in FIG. That is, the power supply Vcc and the ground GND
An NPN transistor Tr11 and a PNP transistor Tr12 are connected in series between
, Tr12 common base currents IB1 and IB2 are input,
The emitters of both transistors Tr11 and Tr12 are connected to the gate of the output transistor 4.

Therefore, when the base circuit IB1 in the direction shown in FIG. 4 is supplied by the circuit preceding the output circuit 28, the transistor Tr12 is turned on and the output voltage VG is lowered, so that the output transistor 4 is turned on. . When the base current IB2 is supplied, the transistor Tr11 is turned on and the output voltage VG rises, so that the output transistor 4 is turned off.

A concrete structure of the oscillator 27 is shown in FIG. The oscillator 27 is configured by adding transistors Tr13 to Tr17 and the like to the configuration of the conventional example, and the same components are designated by the same reference numerals and the description thereof will be omitted.

The output voltage of the current detection amplifier 22 is N
It is input to the base of the PN transistor Tr13, and the collector of the transistor Tr13 is connected to the power supply VREF.
The NPN transistor Tr14 is the transistor Tr13.
And constitute a differential circuit, the collector of the transistor Tr14 is connected to the power supply VREF, and the lower limit frequency setting voltage VRT2 is supplied to the base. And the transistor T
The emitters of r13 and Tr14 are connected to the ground GND via the current source 29.

PNP transistor T forming a differential circuit
The emitters of r15 and Tr16 are connected to the power supply VREF via the current source 31, the base of the transistor Tr15 is connected to the emitters of the transistors Tr13 and Tr14, and the collector is connected to the ground GND.

The collector of the transistor Tr16 is connected to the ground GND, the base is connected to the ground GND through the current source 30, and the emitter of the NPN transistor Tr17 is connected.

The collector of the transistor Tr17 is connected to the power supply VREF, and the base thereof has the upper limit frequency setting voltage VRT.
1 is supplied. The upper limit frequency setting voltage VRT1 is set as a voltage higher than the lower limit frequency setting voltage VRT2.

The emitters of the transistors Tr15 and Tr16 are connected to the non-inverting input terminal of the buffer amplifier 15. In the oscillator 27 thus configured, when the output voltage of the current detection amplifier 22 becomes lower than the lower limit frequency setting voltage VRT2, the transistor Tr13 is turned off and the transistor Tr14 is turned on.

Then, if the base-emitter voltage drop of each transistor is VBE, the base potential of the same transistor Tr15 is VRT2-VBE. Further, the base potential of the transistor Tr16 becomes VRT1-VBE due to the operation of the transistor Tr17, so that the transistor Tr15 is turned on and the transistor Tr16 is turned off, so that the input voltage of the non-inverting input terminal of the buffer amplifier 15 is VRT2.
Becomes

Then, the buffer amplifier 15 controls the current flowing from the transistor Tr3 to the resistor RT so that the emitter potential of the transistor Tr3 becomes VRT2. Then, VRT2 is set so that the oscillation frequency based on this current becomes 20 KHz.

The output voltage of the current detection amplifier 22 is higher than the lower limit frequency setting voltage VRT2, and the upper limit frequency setting voltage VRT1
When it is lower, the transistor Tr13 is turned on and the transistor Tr14 is turned off.

Further, the transistor Tr15 is turned on and the transistor Tr16 is turned off, so that the input voltage of the non-inverting input terminal of the buffer amplifier 15 becomes equal to the output voltage of the current detection amplifier 22.

Therefore, when the output voltage of the current detection amplifier 22 is higher than the lower limit frequency setting voltage VRT2 and lower than the upper limit frequency setting voltage VRT1, the current flowing through the resistor RT changes based on the output voltage of the current detection amplifier 22, The oscillation frequency changes as the output voltage of the detection amplifier 22 changes.

When the output voltage of the current detection amplifier 22 becomes higher than the upper limit frequency setting voltage VRT1, the transistor Tr15
Of the buffer Tr15 is turned off, and the input voltage of the non-inverting input terminal of the buffer amplifier 15 becomes VRT1.

Then, the buffer amplifier 15 controls the current flowing from the transistor Tr3 to the resistor RT so that the emitter potential of the transistor Tr3 becomes VRT1. Then, VRT1 is set so that the oscillation frequency based on this current becomes 350 KHz.

With such an operation, the terminal voltage of the resistor RT is set to the lower limit frequency setting voltage V based on the change of the output current Iout of the switching regulator as shown in FIG.
It changes within the range from RT2 to the upper limit frequency setting voltage VRT1.

Based on the change in the terminal voltage of the resistor RT, the oscillation frequency of the oscillator 27 is f as shown in FIG.
It changes in the range of osc1 to fosc2.
c1 is set to 20 KHz and fosc2 is set to 350 KHz.

The output voltage of the current detection amplifier 22
The frequency setting voltages VRT1 and VRT2 are both one NPN.
Transistor and the base of one PNP transistor
It is transmitted to the buffer amplifier 15 via the emitter.

Therefore, since the same number of transistors are transmitted to the buffer amplifier 15, the temperature dependency of each transistor is canceled. Now, in the switching regulator configured as described above, a voltage corresponding to the current value of the output current Iout is supplied to the current control amplifier 23 from the current detection amplifier 22 based on the voltage between both terminals of the output current detection resistor Rs. Is output.

The current control amplifier 23 outputs a signal based on the potential difference between the output voltage of the current detection amplifier 22 and the reference voltage to the voltage control amplifier 25. Further, the voltage based on the output voltage Vout is input to the voltage control amplifier 25 from between the resistors RA1 and RA2. Then, the voltage control amplifier 25
PW the signal based on the potential difference between the input voltage and the reference voltage.
Output to the M comparator 26.

The PWM comparator 26 controls the duty of the frequency of the pulse signal output from the oscillator 27 based on the output signal of the voltage control amplifier 25 to output the output circuit 2.
8 and the output circuit 28 drives the output transistor 4 with the output signal.

Therefore, the output voltage Vout output from the switching regulator to the load 8 becomes a constant voltage based on the operation of the voltage control amplifier 25, and the output current Iout.
Is within a fixed value based on the operation of the current control amplifier 23.

At this time, by the operation of the oscillator 27,
When the output current Iout increases, the oscillation frequency of the oscillator 27 increases, and when the output current Iout decreases, the oscillation frequency of the oscillator 27 decreases.

That is, during the standby operation, the output current I
When out becomes 2mA, the oscillation frequency of oscillator 27 is 20
It becomes KHz, and the output current Iout is 1.5A during normal operation.
Then, the oscillation frequency becomes 350 KHz.

Then, as shown in FIG. 9, the efficiency E of this embodiment is the efficiency at the oscillation frequency of 20 KHz during the standby operation and the efficiency at the oscillation frequency of 350 KHz at the normal operation.

Therefore, the efficiency in both the standby operation and the normal operation can be improved. The reason why the efficiency is improved by lowering the oscillation frequency of the oscillator 27 when the output current is low will be described with reference to FIG.

As shown in FIG. 5A, in the output circuit 28, when the base current IB1 flows, the transistor Tr1 is turned on.
2 is turned on to lower the gate potential VG of the output transistor 4, and the output transistor 4 is turned on to raise the drain potential VD of the transistor 4.

At this time, no current flows through the transistor Tr12 after the electric charge charged between the emitter of the transistor Tr12 and the gate of the output transistor 4 is instantaneously discharged as the emitter current IE1. The base current IB1 also flows instantaneously.

Then, when the base current IB2 flows, the transistor Tr11 is turned on, the gate potential VG of the output transistor 4 rises, and the output transistor 4 is turned on. At this time, no electric current flows in the transistor Tr11 after the electric charge for charging between the emitter of the transistor Tr11 and the gate of the output transistor 4 instantaneously flows as the emitter current IE2, and accordingly, the base current flows. IB2 also flows instantaneously. The output circuit 28 consumes power during this switching operation.

As shown in FIG. 5B, the output current Iout
In order to reduce the
When the time until the base current IB2 is supplied is shortened, the on time of the output transistor 4 is shortened, and the output current I
out decreases.

At this time, the output current Iout has decreased, but the switching frequencies of the transistors Tr11, Tr12 and the output transistor 4 of the output circuit 28 do not change.
Therefore, although the output power of the switching regulator decreases, the power consumption of the output circuit 28 does not change, and therefore the input power does not change, so that the efficiency decreases.

On the other hand, as shown in FIG. 5C, if the switching frequency is set to 1/3 and the supply intervals of the base currents IB1 and IB2 are set so that the ON time of the output transistor 4 is tripled, the output is The number of switching times of the output circuit 28 can be reduced to 1/3 while keeping the current Iout the same.

Therefore, as compared with the case of operating at the frequency shown in FIG. 5B, the input power can be reduced by reducing the power consumption of the output circuit 28 while securing the same output power. , Efficiency is improved.

Further, this switching regulator
The current control amplifier 23 and the voltage control amplifier 25 are connected in series, and the phase compensation capacitance Cp is connected between the input and output terminals of the voltage control amplifier 25.

Therefore, since the phase compensation of the current control amplifier 23 and the voltage control amplifier 25 can be performed by one phase compensation capacitance Cp to prevent the oscillation of this switching regulator, the number of external elements can be reduced. Thus, the switching regulator can be downsized.

In the above embodiment, in the switching regulator in which the current control amplifier 23 and the voltage control amplifier 25 are connected in series, the current detection amplifier 22
Although the output signal of is input to the oscillator 27, the current control amplifier and the voltage control amplifier are PWMed as in the conventional example.
In the switching regulator connected in parallel with the comparator, the output signal of the current detection amplifier may be input to the oscillator 27.

The technical ideas other than the claims that can be understood from the above-described embodiment will be described below along with their effects. (1) In claim 1, the output control circuit includes a current control amplifier that operates based on an output current of the smoothing circuit and a voltage control amplifier that operates based on an output voltage of the smoothing circuit. A current control amplifier and a voltage control amplifier were connected in series, and a phase compensation capacitor was connected between the input and output terminals of the voltage control amplifier connected in the subsequent stage. It is possible to output a wide range of output current with high efficiency and reduce the number of externally attached elements to achieve miniaturization.

[0088]

As described in detail above, the inventions of claims 1 to 3 can provide a switching regulator capable of outputting a wide range of output current with high efficiency.

Further, in the invention of claim 3, the temperature characteristic of the current control circuit can be further canceled. Further, according to the invention of claim 4, it is possible to provide a switching regulator which can be downsized by reducing the number of external elements.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing one embodiment.

FIG. 3 is a circuit diagram showing an oscillator according to an embodiment.

FIG. 4 is a circuit diagram showing an output circuit.

FIG. 5 is a waveform diagram showing the operation of the output circuit.

FIG. 6 is an operating characteristic diagram of a current detection amplifier.

FIG. 7 is a terminal voltage characteristic diagram of an oscillation frequency setting resistor.

FIG. 8 is an output characteristic diagram of an oscillator.

FIG. 9 is an efficiency characteristic diagram of one embodiment.

FIG. 10 is a circuit diagram showing a conventional example.

FIG. 11 is a circuit diagram showing a conventional oscillator.

FIG. 12 is a waveform diagram showing an output signal of a conventional oscillator.

FIG. 13 is an efficiency characteristic diagram of a conventional example.

[Explanation of symbols]

 4 Output Transistor 27 Oscillator 32 Switching Control Circuit 33 Smoothing Circuit 34 Output Control Circuit 35 Frequency Adjustment Circuit fosc Oscillation Frequency Iout Output Current Vout Output Voltage

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Matsuyama 1844-2, Kozoji-cho, Kasugai-shi, Aichi Prefecture Fujitsu Viels AI Co., Ltd. (72) Inventor Yoshiaki Sano 1844-2 Kozoji-cho, Kasugai-shi, Aichi Fujitsu Within VIS Co., Ltd.

Claims (4)

[Claims] 1. An oscillator that outputs an oscillation frequency, a switching control circuit that outputs a pulse signal that drives a switching operation of an output transistor based on the oscillation frequency, and an output transistor that outputs a pulse signal by a switching operation of the output transistor. A smoothing circuit for smoothing and outputting the output signal; and an output control circuit for outputting a control signal for controlling the duty of the pulse signal to the switching control circuit based on the output voltage and the output current of the smoothing circuit. A switching regulator, wherein the oscillator includes a frequency adjustment circuit that changes an oscillation frequency so as to follow a change in an output current of the smoothing circuit. 2. The oscillator includes a capacitor that outputs its charge / discharge potential as the oscillation frequency signal, a current mirror circuit that supplies a charging current to the capacitor, a discharge circuit that discharges the capacitor, and a capacitor that charges the capacitor. When the potential reaches a preset upper limit value, the capacitance is connected to the discharge circuit, and when the charge potential of the capacitance reaches a preset lower limit value, the capacitance is connected to the current mirror circuit. The switching regulator according to claim 1, further comprising a switching circuit and a current control circuit that increases or decreases the output current of the current mirror circuit based on the output current of the smoothing circuit. 3. The current control circuit comprises a pair of N input voltage signals based on the output current of the smoothing circuit and a lower limit setting voltage for setting a lower limit value of the output current of the current mirror circuit.
A first differential circuit input to the base of a PN transistor, a potential of an emitter of the transistor that constitutes the first differential circuit, and an upper limit setting voltage that sets an upper limit value of an output current of the current mirror circuit. Is inputted to the bases of the pair of PNP transistors, and the emitter potential of the NPN transistor is inputted to the bases of the pair of PNP transistors. The switching regulator according to claim 2, further comprising a buffer amplifier that controls an output current of the current mirror circuit. 4. An oscillator that outputs an oscillation frequency, a switching control circuit that outputs a pulse signal that drives the output transistor to switch based on the oscillation frequency, and an output from the output transistor by a switching operation of the output transistor. A smoothing circuit for smoothing and outputting the output signal; and an output control circuit for outputting a control signal for controlling the duty of the pulse signal to the switching control circuit based on the output voltage and the output current of the smoothing circuit. A switching regulator, wherein the output control circuit includes a current control amplifier that operates based on the output current of the smoothing circuit and a voltage control amplifier that operates based on the output voltage of the smoothing circuit, and the current control circuit Before connecting the amplifier and the voltage control amplifier in series and connecting them in the subsequent stage Switching regulator, characterized in that connected to the phase compensation capacitance between the input and output terminals of the voltage controlled amplifier.