JPH09283737A - Quantum dot array structure - Google Patents

Abstract

(57) 【Abstract】 PROBLEM TO BE SOLVED: For a quantum dot array structure, by adopting a simple means of using a strain generation source such as a strained wire or a strained box
It is possible to generate undamaged quantum dots with a uniform size, uniform density, and high density, and a device in which a plurality of quantum dots are connected (arranged), for example,
We will try to develop it into a single-electron device. SOLUTION: An InAs thin wire 4 which is a strained thin wire formed by stacking a thin wire InAs layer 2 on a substrate 1 made of GaAs, and an SK type arrayed on the InAs thin wire 4. InAs, a growing quantum dot array
And a row of dots 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SK which appears at the initial stage of growing a quantum dot composed of a compound semiconductor, for example, strained heterocrystal such as InAs / GaAs.
The present invention relates to improvement of a structure including an array of quantum dots using a (Transsky-Krastanov) type growth island.

At present, individual quantum dots have been realized, and many experiments and measurements are being made, but in order to use them as devices, quantum dot arrays must be created.

However, it is very difficult to arrange the quantum dots in a controlled state to form an array, and this is the main cause of impeding practical application. Therefore, it is necessary to eliminate this problem. According to the present invention, it is possible to provide one means for responding to this.

[0004]

2. Description of the Related Art Generally, two types of methods are known as methods for forming quantum dots (boxes). In other words, it is a method of performing processing based on lithography technology, etc., and a method of growing a structure in a self-forming manner by utilizing the surface phenomenon (natural phenomenon) during crystal growth.

Specifically, (1) molecular beam epitaxial growth (molecular)
Beam epitaxy (MBE) and metalorganic chemical vapor deposition
al vapor deposition: MOCV
By applying D) or the like, a necessary semiconductor layer is laminated and formed on a substrate, and this is processed into a box shape by applying a lithography technique, in particular, electron beam lithography or ion beam lithography, that is, Etching.

(2) The substrate is processed in the same manner as in the above (1), and thereafter, a box-shaped structure is formed by utilizing the selectivity of growth in the MBE method, the MOCVD method or the like.

(3) A box is obtained by utilizing the surface step or kink on the slightly inclined substrate to control the growth in the lateral direction.

(4) A box is obtained by using SK type growth islands appearing at an early stage of growth of a high strain type heterostructure such as InAs / GaAs. And the like.

By the way, when the means described in the above (1) and (2) are used, damage is likely to occur from the surface of the semiconductor layer toward the inside, and the size of the box depends on the processing size. It is difficult to control the size of [nm] or less, and the size variation is large.

Further, when the means described in the above (3) is used, it is difficult to control the shape of the surface step, and in addition, since the material is mixed in the lateral direction, the size, composition, and the steepness of the lateral interface are reduced. It cannot be controlled precisely.

Furthermore, in the case of the means described in (4) above, since no processing process is used, there is no processing damage, and growth islands (dots) are formed due to surface energy and strain energy. Therefore, the sizes of the boxes can be made substantially uniform by approaching the equilibrium state, and the standard deviation is about 10% although it is at the experimental level.

Thus, although there are advantages that the means (1) to (3) do not have, the formation of growth islands depends on the surface condition of the underlying layer, that is, steps or kinks, and the rearrangement structure of atoms on the surface. Because it depends strongly on surface defects,
The dots formed are sparsely and densely and do not have a uniform density, and due to this, variations in size also occur, and the dot arrangement and arrangement cannot be controlled.

When the means (4) is adopted,
If it is possible to control the arrangement of dots, not only can quantum dots with no damage be generated with uniform size and density, but they can also be applied to devices that connect (array) multiple dots, such as single-electron devices Will also be possible.

Various attempts have been made to date regarding the arrangement control of dot generation in the means (4).

(A) A method of processing a step on a substrate to generate dots in the vicinity of the step (if necessary, "DSL Mu.
i et al. , Appl. Phys. Lett. 6
6 (1995) ").

(B) A method of forming a V-shaped groove by applying a selective growth method on a patterned substrate and arranging dots at the bottom thereof (if necessary, "IPRM'95 Late")
Oral presentation on News ").

(C) A multi-step step in which step bunching has occurred is formed, and quantum dots are preferentially generated on the multi-step step (if necessary, "M. Kitamur").
a et al. Proc. of IPRM'95,
(1995) p. 736 "). Is known (in the above description, "IPRM'95" means "S
event International Conf
erence On Indium Phosphid
e and Related Material ").

[0018]

The problem of (A) is that it is difficult to control the step shape for arranging dots.

The problem of the above (B) is that the area used for forming the V-shaped groove, that is, the area where dots are not formed is large, and therefore the density cannot be increased and the processing is not performed. Process is complicated and flat
It does not become r).

The problem of (C) is that bunching control of the surface step is difficult, kinks are locally concentrated on the bunching surface, and fluctuations occur on the bunching surface. Can not be formed in.

The present invention makes it possible to generate undamaged quantum dots with a uniform size and a uniform density by adopting a simple means utilizing a strain generation source such as a strained wire or a strained box. In addition, according to the embodiment, it is possible to generate at high density, and it can be developed to realize a device in which a plurality of quantum dots are connected (arranged), for example, a single electron element. .

[0022]

The present invention is basically based on the technique for obtaining dots by using the above-described SK type growth island that appears in the early stage of growth of a high strain type heterostructure such as InAs / GaAs. However, its drawbacks are eliminated.

Now, apart from the technique described above, SK
It is known that when layered quantum dots are layered via an interval layer, the upper quantum dots are affected by the distortion caused by the lower quantum dots and are generated at the positions of the lower dots. (If necessary,
"L. Goldstein et al., Appl.
Phys. Lett. 47 (10), 15 Novem
ber 1985 pp. 1100-1101 ",
"Y. SUGIYAMA et al., Extend
ed Abstracts of the 1995
International Conference
on Solid State Devices and
Materials, Osaka, 1995, pp.
773-775 "," GSS of Stanford University
olomon et al. Is Physical Re
The paper “Verti submitted to view Letters
callyAligned and Electron
ically Coupled Growth Ind
used InAs Islands in GaA
s "").

By utilizing this phenomenon, it is possible to preferentially select and form the quantum dots on the strained thin line formed on the base or on the box. In addition, in this case, the strained thin line or the box is a strain generation source. Since it is used only as a material and not as an active layer, it is not necessary to control the structure of the thin wire or the box so precisely.

From the above, in the quantum dot array structure according to the present invention, (1) a compound semiconductor layer (for example, a thin wire InAs layer 2) is laminated on a substrate (for example, the substrate 1). Strained thin line (for example, InAs thin line 4) and an SK type grown quantum dot array (for example, InAs) formed on the strained thin line.
A row of dots 6), or

(2) In the above (1), the strained thin line is formed on a substrate tilted from a low index plane (for example, a GaAs substrate tilted by 0.3 ° in the [110] direction from the (001) plane). Characterized in that it is

(3) In the above (1), the strained wire is formed by growing from a uniform monolayer step, or

(4) In the above (1), the strained thin line and S
A strain transmission layer (for example, a strain introduction layer 5A) is interposed between the K-type grown quantum dot array and

(5) In the above (1) to (4), the substrate has a low index plane which is a (110) plane and which is inclined from the (110) plane in the [001] direction up to 1.5 degrees. Or

(6) In the above (1) to (5), the strain in the strained thin wire is a compressive strain, or

(7) A strain box (for example, InAs box 14) formed by laminating a compound semiconductor layer (for example, thin wire InAs layer 12) on a substrate (for example, substrate 11), and arranged on the strain box. Formed S-K type grown quantum dot array, or

(8) In the above (7), the substrate in which the strain box is tilted in two directions from the low index plane (for example, (00
From the 1) plane, from the [110] direction to the [-110] direction 2
It is characterized in that it is formed on a substrate 11) inclined by 0.3 ° in the direction of swinging, or

(9) In the above (7), the strain box is formed by growing uniform monolayer steps and monomolecular kinks, or

(10) In the above (7), the distortion box and the S
-A strain transfer layer is interposed between the K-type grown quantum dot array and

(11) In the above (7) to (10), the substrate has a low index plane of (110) plane and (11)
Characterized in that it is inclined up to 1.5 degrees from the (0) plane in the [001] direction, or

(12) In the above (7) to (11), the strain in the strained thin wire is a compressive strain.

By adopting the above-mentioned means, it is possible to generate damageless quantum dots with a uniform size and a uniform density, and also to connect (arrange) a plurality of quantum dots.
The device can be applied to a single electron element.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 3 are perspective views of a principal part showing a quantum dot array structure in a process key point for explaining the first embodiment of the present invention, and FIG. 4 is an arrow of FIG. FIG. 3 is a side view of a main part cut from the direction, which will be described below with reference to these drawings.

See FIG. 1A. 1- (1) Prepare a GaAs substrate tilted by 0.3 ° in the [110] direction from the (001) plane and apply the MBE method to grow at a temperature of 680. GaAs is grown at [° C.]. For convenience, the whole substrate on which GaAs is grown is designated by the symbol 1.

In this way, the GaAs step
Flow growth is performed and uniform steps are formed on the substrate surface.

That is, monolayer steps parallel to the [110] direction are generated at equal intervals, and the step interval L is determined by L = h / tan θ. In this case, since the substrate is GaAs, h = a / 2 (a = 0.56535: lattice constant) θ = 0.3 L = (0.5635 / 2) /tan0.3, which is about 54 [ nm].

See FIG. 1B. 1- (2) The temperature of the substrate 1 is lowered to 500 [° C.], and the MEE (mi
gration enhancement epita
By applying the xy) method, the thin linear InAs layer 2 corresponding to 0.2 molecular layer is grown from the step end.

The MEE method is a method of separately supplying the Group 3 raw material and the Group 5 raw material to the substrate 1 in order to increase the migration length of the Group 3 raw material.

In this case, the irradiation time of In is about 2 [sec], and the cell temperature of In is set so that the growth rate of one molecular layer grows in 10 [sec]. The irradiation time was about 5 seconds, and the As beam intensity, that is, the pressure was 3 × 10 ⁻⁶ [torr].

In this way, along the step edge,
The width LA is 11 [nm], that is, the step interval L = 54.
A fine linear InAs layer 2 having a height of 1/4 of [nm] and a monolayer height is formed, and the remaining width LB is 43.
[Nm].

See FIG. 2A. 2- (1) A GaAs layer 3 of 0.8 molecular layer is grown by applying the same means and conditions of the substrate 1 as when the thin linear InAs layer 2 was grown.

In this case, the Ga irradiation time is about 2 seconds, and the Ga cell temperature is set so that the growth rate of the four molecular layers grows in 10 seconds. And the irradiation time of As is about 11 seconds, and the beam intensity of As, that is, the pressure is 3 × 10 ⁻⁶ [t].
orr].

In this way, the GaAs layer 3 is grown adjacent to the thin linear InAs layer 2, so that the entire surface is covered with a monomolecular layer of InAs and GaAs.

See FIG. 2B. 2- (2) By repeating the steps 1- (2) and 2- (1) four times, the width is 11 [nm], that is, the step interval L =
It is 1/4 of 54 [nm] and the height is 1.1 [n
m], that is, an InAs thin wire 4 having a height of four molecular layers can be obtained.

See FIG. 3A. 3- (1) The growth temperature is set to 500 by applying the MBE method.
A GaAs layer 5 having a thickness of, for example, 10 nm is grown at [° C.].

In this way, the underlying InAs thin wire 4 is formed.
Strain is introduced into the GaAs grown directly on the surface of the GaAs. In the figure, the layer in which strain is introduced among the GaAs layers 5 is indicated by the symbol 5A.

See FIG. 3B. 3- (2) The growth temperature is set to 500 by applying the MBE method.
When InAs corresponding to two molecular layers is formed at [° C.], SK type InAs growth islands (dots) 6 are preferentially generated on the portion where the underlying layer has strain, that is, on the strain introduction layer 5A.

See FIG. 4 4- (1) Further, by applying the MBE method, the growth temperature is set to 50.
GaAs layer 7 having a thickness of 0 [° C.], for example, 10 [nm]
And then continue to grow the InA
When s is formed, the portion where the base has distortion, that is, InA
The SK type InAs dots 8 are preferentially generated on the portion where the distortion caused by the s dots 6 exists.

Therefore, by repeating this, it is possible to arrange dots in the direction perpendicular to the surface of the substrate 1.

5 and 6 are principal part explanatory views showing a quantum dot row structure in a process principal part for explaining the second embodiment of the present invention, (A) is a principal part sloped surface, B) shows a plane of a main part and (C) shows a slope of the main part, which will be described below with reference to these drawings.

See FIG. 5A. 5- (1) Prepare a substrate 11 tilted from the (001) plane by 0.5 ° from the [110] direction to the [−110] direction by 0.3 °. , MBE method was applied to increase the growth temperature to 6
GaAs is grown at 80 [° C.]. In this case as well, the symbol 11 indicates the entire substrate on which GaAs is grown.

In this way, monolayer steps are formed at equal intervals perpendicular to the direction of 0.5 ° swing from the [110] direction to the [-110] direction, and kinks are formed at equal intervals at the step ends. To be done.

The step interval L is determined by L = h / tan θ as in the first embodiment, and since the substrate is GaAs, h = a / 2 (a = 0.56535) θ = 0.3 L = ( It is 0.5635 / 2) / tan 0.3, which is about 54 [nm].

See FIG. 5B. 5- (2) Further, the kink interval L _K is L _K = 22.9 [nm] when L _K = 0.19988 / tan α α = 0.5 °. Note that d ₂₂₀ = a / (2 ² +2 ² ) ^1/2 = 0.19988 a = 0.5635.

5 (C) 5- (3) After the temperature of the substrate 11 is lowered to 500 [° C.], ME
By applying the E method, the thin linear InAs layer 12 corresponding to 1/900 molecular layer is grown from the kink at the step end.

In this case, the In irradiation time is about 0.3 seconds, and at this time, the In cell temperature is set so that the growth rate of one molecular layer grows in 270 seconds, and
Irradiation time was about 3 seconds, and the As beam intensity, that is, the pressure was 3 × 10 ⁻⁶ [torr].

In this way, along the step edge,
The width is 0.2 [nm], that is, the width of the monolayer, the height is the height of the monolayer, and the length is about 1/3 of the kink interval.
The As layer 12 is formed.

5- (4) By applying the same means and conditions of the substrate 11 as when the thin linear InAs layer 12 is grown, the thin linear Ga of 2/900 molecular layer is applied.
The As layer 13 is grown.

In this case, the Ga irradiation time is about 0.3.
[Sec], and the cell temperature of Ga is set so that the growth rate of the bilayer grows at 270 [sec], and the irradiation time of As is about 3 [sec]. ] At that time, the beam intensity of As, that is, the pressure is 3 × 1.
It was set to 0 ^-6 [torr].

By doing so, the thin linear InAs layer 12 is formed.
The thin linear GaAs layer 13 is grown along the step edge in a state where the step edge is formed of In.
It will be covered with As and GaAs.

See FIG. 6 6- (1) By repeating the steps 5- (2) and 5- (3) 270 times, the height is 1.1 [nm], that is, the height of four molecular layers. It is possible to obtain an InAs box 14 having a height.

6- (2) Although not shown in the subsequent steps, the quantum dot array structure can be completed through steps similar to those of the first embodiment.

That is, by applying the MBE method, the growth temperature is set to 500 ° C. and a GaAs layer having a thickness of, for example, 10 nm is grown.

In this way, the underlying InAs box 14
Strain is introduced into the GaAs grown directly on the surface of the GaAs.

The region into which the strain is introduced has a stripe as the strain introduction layer 5A in the first embodiment, but in the present embodiment, due to the InAs box 14, the square is formed. Will be expressed as the area of.

6- (3) The growth temperature is set to 500 by applying the MBE method.
When InAs corresponding to two molecular layers is formed at [° C.], SK-type InAs growth islands (dots) are preferentially generated on the portion where the underlying layer has strain, that is, on the strain introduction region.

6- (4) Furthermore, the growth temperature is set to 50 by applying the MBE method.
After a GaAs layer having a thickness of, for example, 10 [nm] is grown at 0 [° C.], the InAs corresponding to two molecular layers is subsequently grown.
Form a portion where the underlying layer has distortion, that is, InAs
Preferentially S-on the portion where the distortion due to dots exists
K-type InAs dots are generated.

Therefore, by repeating this, the substrate 11
It is also possible to arrange dots in a direction perpendicular to the surface of the, and according to this, it is possible to arrange dots in a three-dimensional direction.

By the way, according to the conventional technique, when the quantum dots are formed, the electron beam lithography technique and the ion
Since the beam lithography technology and the like are directly applied to the processing of the quantum dots, it is difficult to form the quantum dots with high density.

However, in the present invention, when the strain-introducing layer or the strain-introducing region which is the base for growing the quantum dots is formed by applying the lithography technique, the density is higher than that in each of the above-described embodiments. Although it is a little inferior in terms of efficiency, it is easy to arrange the quantum dots in a line, and the occupied area is smaller than when forming V-shaped grooves, and the surface can be flattened. Such,
Since there are various advantages, the embodiment will be described next.

FIGS. 7 and 8 and FIGS. 9 to 11 are perspective views and a cross-sectional side view of a main part showing a quantum dot array structure in a process main part for explaining the third embodiment of the present invention. Therefore, description will be made below with reference to these figures as needed.

7 (A), FIG. 9, and FIG. 10 7- (1) By applying the MBE method, 680 is formed on the GaAs substrate 21 having the (001) plane just cut.
At a growth temperature of [° C.], a G having a thickness of, for example, 300 [nm]
The aAs buffer layer 22 is formed.

7- (2) Subsequently, the MBE method is applied to lower the temperature of the GaAs substrate 21 to 450 [° C.], and then the GaAs buffer layer 2 is formed.
In _x Ga _1-x As having a thickness of over 2, for example, 15 [nm]
The graded layer 23 is formed.

In this case, the x value is changed from 0.01 (buffer layer 22 side) to 0.5 (front surface side) by changing the cell temperature of In while growing In _x Ga _1-x As. Change up to.

7- (3) By applying the spin coating method, as shown in FIG. 9A, for example, PMMA (polymethylmethacrylate) having a thickness of about 100 nm!
plate) is formed.

7- (4) As shown in FIG. 9B, the electron beam resist film 24 is drawn by applying the electron beam exposure method.

7- (5) MIBK (methylisobutylketon)
The electron beam resist film 24 is developed by immersing it in an etching solution composed of a mixed solution of isopropyl alcohol and
The electron beam irradiation portion in is removed to obtain the fine line pattern shown in FIG.

[0083] 7- (6) (hydrofluoric acid + hydrogen peroxide + water) mixture depending on applying a wet etching method to etchant, an In _x Ga electron beam resist film 24 as a mask
_{The 1-x} As graded layer 23 is etched into a fine line pattern as shown in FIG.

7 (B) and FIG. 11 7- (7) The electron beam resist film 24 used as the mask is removed by immersing it in a remover, acetone or the like.

7- (8) Immerse in ammonium sulfide, and as shown in FIG. 11B, passivate the crystal surface by terminating with S.

See FIG. 8A. 8- (1) MBE after cleaning the surface in the MBE device.
By applying the E method, the GaAs layer 25 having a thickness of, for example, 10 [nm] is formed at a growth temperature of 500 [° C.].

The GaAs layer 25 has a thin linear In _x
The strain introduction layer 25A is generated due to the influence of the Ga _1-x As graded layer 23.

See FIG. 8 (B). 8- (2) By applying the MBE method, an InAs layer corresponding to two molecular layers is grown at a growth temperature of 500 [° C.]. Priority is given to the part which is
Growth islands of nAs, that is, dots 26 are generated.

Although not shown in the figure, thereafter, by applying the MBE method, a GaAs layer having a thickness of, for example, 10 nm is grown at a growth temperature of 500 ° C., and then,
Subsequently, when InAs corresponding to two molecular layers is formed, the SK type InA is preferentially formed on the portion where the underlying layer has strain, that is, the portion where the strain caused by the InAs dots 26 exists.
S dots are generated.

Therefore, by repeating this, the substrate 21
It is also possible to arrange dots in a direction perpendicular to the surface of the, and according to this, it is possible to arrange dots in a three-dimensional direction.

The present invention is not limited to the above embodiment, and many other modifications can be realized.

For example, in the third embodiment, In _z
Although the Ga _1-z As graded layer 23 is formed in a thin line shape, it may be formed in a box shape.

When GaAs is used as the material of the substrate, InAs or InGa is used as the material of the strained wire.
In addition to As, GaSb, InP, or a compound thereof such as GaAsSb or InGaAsP can be used.

When the material of the substrate is InP, InAs, GaSb and their compounds can be used as the material of the strained wire.

Further, in the above-mentioned embodiment, the substrate whose principal plane orientation is (001) is used, but (110)
It is useful to use a substrate having a (110) plane because a linear step is easily obtained on a slightly tilted substrate as compared with a (001) plane.

When the (001) plane or (110) plane of the GaAs substrate is used and the inclination angle is 1.5 degrees, the average step interval is about 11 [nm],
It becomes about 8 [nm], and the diameter of the generated quantum dot is 10 [nm] at the minimum.

Therefore, even if the step interval is smaller than the above-mentioned numerical value, that is, the tilt angle is increased, the quantum dots come into contact with each other in the lateral direction or are energetically coupled with each other. Since the meaning of arrangement is lost, it is useful to set the tilt angle within 1.5 degrees.

In general, when a quantum dot is produced, the quantum dot needs to have a smaller energy band gap than the material (barrier material) surrounding it, and usually has a large lattice constant. Materials tend to have smaller energy band gaps.

Therefore, in the method of forming the quantum dots according to the present invention, for example, when the InAs dots are formed on GaAs, a material having a larger lattice constant than the barrier material should be used as the material for the quantum dots. select.

If a material having a lattice constant smaller than that of a barrier material (for example, GaAs) is used for the strained thin wire for arranging the quantum dots, a material having a small lattice constant, for example, a lattice constant, is formed on the thin wire due to strain. GaAs is preferentially formed instead of InAs, and InAs is formed at a position other than the thin line, and the arrangement becomes impossible.

Therefore, in order to arrange the quantum dots, a strained thin line having a large lattice constant, that is, having a compressive strain is required.

[0102]

In the quantum dot array structure according to the present invention, a strained thin line formed by stacking a compound semiconductor layer on a substrate and an SK formed by arranging on the strained thin line. It is basically provided with a pattern-grown quantum dot array.

By adopting the above-mentioned structure, it is possible to generate undamaged quantum dots with a uniform size and a uniform density, and to connect (arrange) a plurality of quantum dots.
The device can be applied to a single electron element.

[Brief description of drawings]

FIG. 1 is a perspective view of a principal part showing a quantum dot array structure in a process main part for explaining a first embodiment of the present invention.

FIG. 2 is a perspective view of a principal part showing a quantum dot array structure in a process main part for explaining the first embodiment of the present invention.

FIG. 3 is a perspective view of a principal part showing a quantum dot array structure in a process essential part for explaining the first embodiment of the present invention.

FIG. 4 is a side sectional view showing an essential part of a quantum dot array structure in a process essential part for explaining the first embodiment of the present invention.

FIG. 5 is a principal part explanatory view showing a quantum dot array structure in a process main part for explaining the second embodiment of the present invention.

FIG. 6 is a perspective view of a principal part showing a quantum dot array structure in a process essential part for explaining a second embodiment of the present invention.

FIG. 7 is a perspective view of a principal part showing a quantum dot array structure in a process essential part for explaining a third embodiment of the present invention.

FIG. 8 is a perspective view of a principal part showing a quantum dot array structure in a process essential part for explaining a third embodiment of the present invention.

FIG. 9 is a fragmentary side view showing a quantum dot array structure in a process essential part for explaining a third embodiment of the present invention.

FIG. 10 is a fragmentary side view showing a quantum dot array structure in a process essential part for explaining a third embodiment of the present invention.

FIG. 11 is a side sectional view showing a main part of a quantum dot array structure in a process main part for explaining a third embodiment of the present invention.

[Explanation of symbols]

 1 Substrate 2 Fine InAs layer 3 GaAs layer 4 InAs fine line 5 GaAs layer 5A Strain introduction layer 6 SK type InAs growth island (dot) 7 GaAs layer

Claims (12)

[Claims] 1. A strained thin line formed by stacking a compound semiconductor layer on a substrate, and an SK-type grown quantum dot array formed on the strained thin line. Quantum dot array structure. 2. The quantum dot array structure according to claim 1, wherein the strained wire is formed on a substrate inclined from a low index surface. 3. The strained wire is formed by growing from a uniform monolayer step.
The described quantum dot array structure. 4. The quantum dot array structure according to claim 1, wherein a strain transfer layer is interposed between the strained wire and the SK type grown quantum dot array. 5. The substrate according to claim 1, wherein the low index plane is a (110) plane and is tilted from the (110) plane in the [001] direction up to 1.5 degrees. 1. The quantum dot array structure according to any one of items 1. 6. The quantum dot array structure according to any one of claims 1 to 5, wherein the strain in the strained thin line is a compressive strain. 7. A strain box formed by stacking compound semiconductor layers on a substrate, and an SK-type grown quantum dot array formed on the strain box. Quantum dot array structure. 8. The quantum dot array structure according to claim 5, wherein the strain box is formed on a substrate inclined in two directions from a low index plane. 9. The quantum dot array structure according to claim 5, wherein the strain box is formed by growing uniform monolayer steps and monomolecular kinks. 10. The quantum dot array structure according to claim 5, wherein a strain transfer layer is interposed between the strain box and the SK type grown quantum dot array. 11. The substrate according to claim 7, wherein the low index plane is a (110) plane and is tilted from the (110) plane in the [001] direction up to 1.5 degrees. 1. The quantum dot array structure according to any one of items 1. 12. The quantum dot array structure according to claim 7, wherein the strain in the strained wire is a compressive strain.