JPH09293390A - Shift circuit - Google Patents

Abstract

(57) Abstract: Provided is a circuit capable of changing a bit time from data input to output by controlling timing of data transfer between RS flip-flops in a shift circuit. . Data stored in data storage units 1a to 1d are clock signals C for data transfer from a control unit 2.
The respective data D _{1 to} D ₅ are shifted by LK1 or the clock signal CLK2 having a phase different from that of LK1. The select signal SEL is CL in the data storage units 1a to 1d.
This is a command signal for switching between the rising edge of K1 and the rising edge of CLK2.
The bit time from the input of data to the output can be changed by selecting one of a plurality of clock pulses having different phases by a command signal for data transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data shift circuit, and more particularly, to a data shift circuit provided with a control circuit for transferring data at the rising edges of a plurality of clock pulses having different phases. It is about circuits.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional shift circuit. This shift circuit is composed of eight RS flip-flops 10 for serial input and serial output.
It is a bit shift register. In FIG. 4, 1
1 the inverter, D 'is a data input, S _1' clock signal, S ₀ 'is clear signal. For example, "L"-
At the bit time t _n after the transmission of “H” n clocks,
The initial value of the 8-bit shift register is 0,0,0,0,0,0,
0,0, input data is a0,0,0,0,0,0,0,0, ... 0
Then, at the bit time t _{n + 1} , the state of the shift register is a0,0,0,0,0,0,0,0, and the bit time t.
_{When n + 3} , 0,0, a0,0,0,0,0,0, bit time t
_{When n + 8} , 0,0,0,0,0,0,0, a0, bit time t
_{When n + 9} , 0,0,0,0,0,0,0,0, and the output data until the bit time t _{n + 9} is 0,0,0,0,0,0,
It operates like 0,0, a0. However, the above-mentioned configuration has a problem that the input data a0 cannot be output from the shift register until the bit time t _{n + 9} .

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art, and can control the timing of data transfer between the RS flip-flops in this type of shift circuit. Thus, it is an object to be solved to provide the circuit in which the bit time from the input of data to the output can be changed.

[0004]

According to a first aspect of the present invention, a plurality of data storage means and a predetermined operation clock for storing data in the data storage means and transferring data from the data storage means are generated. Means for controlling the operation in the data storage means by the generated operation clock, and stores the data stored in the data storage means between the plurality of data storage means and from the data storage means. In the shift circuit capable of transferring in synchronization with the operation clock, the predetermined operation clock generation means is configured to generate a plurality of clock signals whose phases are mutually shifted.

According to a second aspect of the present invention, in the first aspect of the present invention, the control means selects any one of the plurality of phase-shifted clock signals and inputs it as an operation clock to the plurality of data storage means. As described above, the control signal generating means for instructing switching of the plurality of clock signals is provided.

According to a third aspect of the invention, in the second aspect of the invention, the plurality of data storage means are provided with circuit means for switching the plurality of input clock signals by a control signal instructing the switching. It is a thing.

[0007]

1 is a block diagram showing the configuration of an embodiment of a shift circuit according to the present invention. In FIG. 1, 1a, 1b, 1c and 1d are data storage units, and 2 is a control unit. D ₁ represents 1-bit data input to the data storage unit 1a. S ₁ represents a clock signal CLK1 for data transfer. S ₂ represents a clock signal CLK2 having a phase different from that of CLK1. CLK1, CLK
At the rising edge of 2, the data storage section outputs the stored data and stores the input data. S ₃ is the select signal S
Represents EL. This is the CLK1
It is used to switch between the rising edge of CLK2 and the rising edge of CLK2. D ₂ , D ₃ , D ₄
And D ₅ represent 1-bit data output from the data storage units 1a, 1b, 1c and 1d, respectively.

FIG. 2 shows an embodiment of the waveforms of the clock signal CLK1, the clock signal CLK2, and the select signal SEL generated by the control unit 2 of FIG. In FIG. 2, a clock signal CLK1 represents a basic clock signal. The clock signal CLK2 is a signal obtained by delaying the phase of CLK1 by 180 °. Select signal SEL
Is a signal obtained by further delaying the phase of CLK2 by 90 °. The data storage unit outputs the stored data at the rising edge of the CLK1 clock signal S ₁ or the rising edge of the CLK2 clock signal S ₂ and stores the input data. Data storage unit 1a~1d switches the CLK1 clock signals S ₁ and CLK2 clock signal S ₂ in SEL select signal S _3. The CLK1 clock signal S ₁ is used when the SEL select signal S ₃ is “H”, and the CLK2 clock signal S ₂ is used when the SEL select signal S ₃ is “L”.

FIG. 3 is a diagram showing the configuration of an embodiment in which the data storage units 1a to 1d of FIG. 1 are embodied. Reference numeral 1-1 is a clock switching unit, and 1-2 is an RS flip-flop. Di represents 1-bit data that is input data. S ₁ represents a clock signal for data transfer. S ₂ is S
Represents a clock signal with a phase different from ₁ . S ₃ represents a select signal for switching the clock signals S ₁ and S ₂ for data transfer. D ₀ represents output data.

[0010]

According to the shift circuit of the present invention, by adding a control circuit for transferring data at the rising edge of a clock pulse selected from a plurality of clock pulses having different phases, from data input to output. You can change the bit time of. Further, the selection of a plurality of clock pulses having different phases is performed by the switching control signal,
The bit time can be changed with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a shift circuit of the present invention.

FIG. 2 is a clock signal CL generated by a control unit 2 in FIG.
1 shows an embodiment of waveforms of K1, clock signal CLK2, and select signal SEL.

FIG. 3 is a diagram showing a configuration of an embodiment in which the data storage units 1a to 1d of FIG. 1 are embodied.

FIG. 4 is a block diagram showing an example of a conventional shift register.

[Explanation of symbols]

1a, 1b, 1c, 1d ... data storage unit, 1-1 ... the clock switching unit, 1-2 ... R-S flip-flop, 2 ... control unit, 10 ... R-S flip-flop, 11 ... inverter, D ₁ ... input data to the data storage unit, D ₂ to D ₅ ... output data from the data storage unit, S ₁ ... CLK1 clock signal, S ₂ ... CLK2 clock signal, S ₃ ... SEL select signal, S ₀ '... CLR signal, S ₁ ′ ... clock signal.

Claims (3)

[Claims] 1. A plurality of data storage means, and a predetermined operation clock generation means for storing data in the data storage means and transferring data from the data storage means,
The control means controls the operation in the data storage means by the generated operation clock, and synchronizes the data stored in the data storage means between the plurality of data storage means and from the data storage means to the operation clock. In the shift circuit capable of being transferred, the predetermined operation clock generating means is configured to generate a plurality of clock signals whose phases are shifted from each other. 2. The control means instructs switching of the plurality of clock signals so as to select any one of the plurality of phase-shifted clock signals and input as an operation clock to the plurality of data storage means. 2. The shift circuit according to claim 1, further comprising a control signal generating unit that controls the shift circuit. 3. The shift circuit according to claim 2, wherein the plurality of data storage means are provided with circuit means for switching the plurality of input clock signals by a control signal instructing the switching. .