JPH09294058A - Multiplier circuit - Google Patents

Abstract

Kind Code: A1 A multiplier circuit capable of stably obtaining a desired delay signal as a delay circuit considering variation in accuracy of each element, delay time, and temperature change. SOLUTION: An input terminal 1, delay elements 2 ₁ , 2 ₂ , ...
2 _n , selector circuit 3, exclusive OR circuit 4, output terminal 5
And configure the following controls. At the trailing edge of the pulse of the input signal, the delay elements 2 _{1 are} sequentially selected until the L signal is detected from the output signal of the selector circuit 3, and the number of stages of the delay elements when first detected is Y. At the rising edge of the next pulse, the delay elements 2 _{Y + 1 are} sequentially selected until the L signal is detected from the output signal of the selector circuit 3, and the number of stages of the delay elements at the time of the first detection is X. . The number of stages of delay elements for extracting a signal whose phase is delayed by n ° in the delay circuit is calculated by the following equation. Y × n / 180- | X-Y |

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication circuit that generates a multiplied signal.

[0002]

BACKGROUND ART FIG. 3, FIG. 4 is a conventional multiplication circuit configuration as shows the time chart in FIG. 3, 1 denotes an input terminal, 2 _1, 2 _2, · · · 2 _n is two A delay element formed by combining inverters, 4 is an exclusive OR circuit, and 5 is an output terminal.

As shown in FIG. 4, the clock CK input to the input terminal 1 has n delay elements 2 ₁ , 2 ₂ , ...
CKD delayed by 90 ° by each propagation delay time of 2 _n
Becomes This delay clock CKD and the original input clock C
The output signal CK2F whose exclusive OR is taken by the exclusive OR circuit 2 is output to the output terminal 5 as a clock having a frequency twice that of the input clock CK.

[0004]

However, in the conventional multiplication circuit, the n delay elements 2 ₁ , 2 ₂ , ..., 2 _n have different rise and fall times, which may affect the temperature change. Then, there is a problem that a desired delay signal cannot be stably obtained and a clock having a frequency of a desired multiple cannot be obtained. Specifically, when the pulse rises as an example, as shown in FIG. 4, the pulse rise may fluctuate within the arrow range and the output signal CK2F may fluctuate within the arrow range as described above. Therefore, it becomes impossible to obtain a clock having a desired multiple frequency.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and obtains a multiplied signal by adding an input signal and a signal obtained by delaying the input signal by a delay circuit to an exclusive OR circuit. In the multiplier circuit, the delay circuit is composed of a multi-stage delay element and a selector circuit that selects and extracts one of the output signals of the delay elements, and the delay circuit extracts a signal whose phase is delayed by n ° (n is a positive number). The selection of the selector circuit for this is performed by the multiplication circuit based on the following procedure.

(1) At the falling edge of the pulse of the input signal, the output signals of the delay circuit when the output signals of the delay elements of each stage are selected are sampled in order from the first stage.

(2) Let Y be the number of stages at which the L signal is first detected in the output signal.

(3) At the rising edge of the pulse, the output signals of the delay circuits when the output signals of the delay elements of each stage are selected are sampled in order from the Y stage.

(4) Let X be the number of stages at which the L signal is first detected in the output signal.

(5) The output signal of the delay element having the number of stages calculated by the following equation is selected.

Y × n / 180− | X−Y | where | X−Y | represents the absolute value of X−Y.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 and FIG. 2 show a multiplication circuit configuration of the present invention and a time chart thereof, where 1 is an input terminal,
_{2 1, 2 2, ··· 2} n is n delay elements that many stages connected in series, the selector circuit 3, the 4 exclusive OR circuit, 5
Indicates an output terminal. In the present invention, each delay element is composed of two inverters.

As shown in FIG. 2, the clock CK input to the input terminal 1 is gradually delayed each time it passes through the delay elements 2 ₁ , 2 ₂ , ... 2 _n. It controls which delay element outputs the output signal.

The control that characterizes the present invention will be described below.

First, when the pulse of the clock CK falls,
That is, at time A in FIG. 2 (i), the output signal CKD of the selector circuit 3 when the delay element 2 ₁ is selected is detected (see (i), (ii), and (iii) in FIG. 2). Note that FIG.
(Iii) indicates that the output signal CKD at that time is H (high).

Next, select the delay element in order to detect the L (low) signal from the delay element 2 _2, samples the output signal CKD of the selector circuit 3, first the number of delay elements when the detected Y (See FIG. 2 (iv)).

Further, the output signal CKD of the selector circuit 3 when the delay element _2Y is selected is detected at the next rising edge of the pulse, that is, at time B in FIG. 2 (i). At that time,
After confirming that it is H, the delay elements 2 _{Y + 1 are} sequentially selected, sampling is performed until the L signal is detected from the output signal of the selector circuit 3, and the number of stages of the delay elements at the time of first detection is set as X. (Fig. 2 (i), (iv),
(V)).

From the X and Y values obtained as described above, the delay time Z of the selector circuit 3 becomes | X−Y |.

Therefore, the number of stages of delay elements for extracting a signal delayed in phase by n ° (n is a positive number) in the delay circuit can be obtained by the following equation.

Y × n / 180− | X−Y | For example, the number of stages of delay elements for obtaining a signal with a 90 ° phase delay in the delay circuit is obtained by the following equation.

Y × n / 2− | X−Y | Further, the number of stages of the delay elements for obtaining a signal having a phase delay of 45 ° in the delay circuit is obtained by the following equation.

Y × n / 4− | X−Y | In this way, by considering the delay elements 2 ₁ , 2 ₂ , ... 2 _n and the selector circuit 3 as a delay circuit, the delay amount of the selector circuit 3 is reduced. Since the number of stages of the desired delay element is selected by subtraction, the desired delayed signal can be stably obtained. Moreover, even when the number of stages of the delay elements becomes large, the duty ratio of the output signal is guaranteed, and since the variations of the circuit components are corrected, it is not necessary for the various components to be highly accurate.

Further, the number of stages of delay elements selected by the selector circuit 3 described above is not limited to when the system power is turned on, but is set several times during energization to enable temperature correction of the entire multiplier circuit.

[0024]

As described above, according to the multiplier circuit of the present invention, a desired delay signal can be stabilized by using a delay circuit that takes into consideration variations in the accuracy of each element, delay time, and temperature changes. It becomes a multiplication circuit that can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a multiplication circuit of the present invention.

FIG. 2 is a time chart diagram of the circuit of FIG.

FIG. 3 is a configuration diagram showing a conventional multiplication circuit.

FIG. 4 is a time chart diagram of the circuit of FIG.

[Explanation of symbols]

1: Input terminals 2 ₁ , 2 ₂ , ... 2 _n : Delay element 3: Selector circuit 4: Exclusive OR circuit 5: Output terminal

Claims (1)

[Claims] 1. A multiplication circuit for obtaining a multiplied signal by adding an input signal and a signal obtained by delaying the input signal by a delay circuit to a multiplied signal, wherein the delay circuit comprises a plurality of stages of delay elements and the delay elements. A selector circuit for selecting and outputting any one of the output signals, wherein the selection of the selector circuit for extracting the signal delayed in phase by n ° (n is a positive number) in the delay circuit is based on the following procedure. Characteristic multiplication circuit. (1) At the trailing edge of the pulse of the input signal, the output signals of the delay circuits when the output signals of the delay elements of the respective stages are selected are sequentially sampled from the first stage. (2) The number of stages at which the L signal is first detected in the output signal is Y
And (3) At the rising edge of the pulse of the input signal, the output signals of the delay circuits when the output signals of the delay elements of the respective stages are selected are sequentially sampled from the Yth stage. (4) The number of stages at which the L signal is first detected in the output signal is X
And (5) Select the output signal of the delay element having the number of stages obtained by the following equation. Y × n / 180- | X-Y |