JPH09294148A - Receiving machine - Google Patents

Abstract

(57) 【Abstract】 PROBLEM TO BE SOLVED: To reduce the size and thickness of an oscillation circuit, the reliability is improved even if a simple circuit adopting a communication method that suppresses local amplitude such as a phase change point is eliminated. Achieve a high receiver. SOLUTION: An amplitude suppression point detection circuit 4 which detects an amplitude suppression point from a received signal C whose amplitude is suppressed at a phase change point or the like by binarization processing and outputs a pulse amplitude suppression point detection signal G.
The receiver 800 includes a demodulation circuit 430, a demodulation circuit 430, and internal circuits 50 and 60 that receive and process the demodulation signal D of the circuit 430. The receiver 800 receives the signal G and suppresses the amplitude of the reception signal C. The demodulation circuit 4 includes a waveform shaping circuit 420 that outputs a single-shot pulse signal J having a predetermined width when there is one or more pulses within a predetermined period that exceeds the local period.
30 demodulates based on the output J of the waveform shaping circuit 420.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a receiver,
Specifically, it is a thin and small IC card such as a coin type or a card type, and a receiver applied to a portable wireless device,
The present invention relates to a receiver that communicates with a communication partner such as a reader / writer in order to perform processing such as command transmission / reception and data reading without contact. Improvements have been made to the reception processing circuit, especially the demodulation circuit, in order to make it thinner and smaller.

[0002]

2. Description of the Related Art Conventionally, as a receiver such as an IC card (responder) which can be accessed by a transmitter such as a reader / writer (interrogator) without contact, one using communication by electromagnetic coupling is known. . As the communication method, a digital modulation method such as an amplitude shift keying method (ASK),
A phase shift keying method (PSK), a differential phase shift keying method (DPSK), etc. are common.

FIG. 8 shows an example of an ASK transmission / reception system, which is composed of a transmitter 10 and a receiver 20. The transmitter 10 amplitude-modulates a carrier wave of several hundreds of kHz according to the ASK method to generate a transmission signal A, which is power-amplified by a driver 11, and is further amplified by the antenna coil 1.
By magnetically driving 2 to perform electromagnetic conversion, a magnetic signal B of the ASK system is transmitted.

When the receiver 20 receives the magnetic signal B, the receiver circuit 30 converts the magnetic signal B into a received signal C, and further, the ASK.
The demodulation circuit 40 restores the demodulated signal D in the state before the modulation to perform the ASK system reception. In addition, the demodulation signal D is sampled in bit serial form by the sampling circuit 5
Input to 0 and convert to parallel data, then MP
It is taken into the processing unit 60 composed of U or the like, and the specific processing according to the contents thereof is performed.

The receiving circuit 30 comprises an antenna coil 31 which is electromagnetically coupled to the antenna coil 12 and a capacitor 32 which is connected in parallel with the antenna coil 31 to form a parallel resonance circuit. It is to convert. Further, the diode bridge 33 and the smoothing circuit 34 are connected in series to these, so that the power supply voltage Vcc can be supplied to the processing unit 60 and the like even if there is no battery. Alternatively, the output of the battery can be supplemented. The carrier wave is used to receive not only communication data but also operating power.

The ASK demodulation circuit 40 receives the received signals C to B.
After the effective carrier-corresponding component is extracted by the PF 40a (bandpass filter), it is rectified by the rectifier circuit 40b and then the LP
The demodulated signal D is generated by performing envelope detection through F40c (low-pass filter). The sampling circuit 50 and the processing unit 60 that process the demodulated signal D are
Usually, it is composed of a synchronous digital circuit. Therefore, the receiver 20 is also provided with an oscillating circuit 70, and the processing unit 60 and the like operate by receiving the clock E from the oscillating circuit 70.

The oscillation circuit 70 includes a ceramic oscillator and a charging / discharging capacitor for stabilizing the oscillation frequency, and generates an oscillation signal by repeating charging / discharging according to its natural vibration. It is what is sent.

FIG. 9 shows an example of a PSK transmission / reception system. This system comprises a transmitter 10 and a receiver 21. The transmitter 10 is substantially the same as that described above, except that the transmission signal A is phase-modulated according to the PSK method. The receiver 21 has a demodulation method and a clock generation method different from those of the receiver 20. Regarding the clock generation method, a clock generation circuit 71 is provided instead of the oscillation circuit 70, and the clock E is generated by binarizing the reproduced carrier wave from the carrier wave reproduction circuit 41b.

Regarding the demodulation method, the ASK demodulation circuit 40
Instead, a PSK demodulation circuit 41 is provided. PSK
The demodulation circuit 41 extracts a component corresponding to the effective carrier wave in the BPF 41a from the received signal C, reproduces the carrier wave in the carrier wave reproduction circuit 41b from the extracted signal of this component, and further multiplies the extracted signal and the reproduced carrier wave in the multiplication circuit 41c. By multiplying by, and performing synchronous detection through the LPF 41d,
The demodulated signal D is generated. The carrier wave reproduction circuit 41b includes a circuit for generating a doubled signal of the extracted signal,
A PLL circuit that oscillates at the frequency of the carrier while matching the phase with this signal is provided to reproduce a reference signal that does not depend on the phase inversion state of the received signal C and is in phase with the carrier.

The PLL circuit generally includes a VCO (voltage controlled oscillator circuit) and a charging / discharging capacitor, and oscillates with charging / discharging.

FIG. 10 shows an example of a DPSK transmission / reception system. The system comprises a transmitter 10 and a receiver 22. The transmitter 10 is substantially the same as the one described above, except that the transmission signal A is phase-modulated and differentially encoded according to the DPSK method. The receiver 22 also
The demodulation method and the clock generation method are different from those of the receivers 20 and 21.

Regarding the demodulation method, a DPSK demodulation circuit 42 is provided instead of the circuits 40 and 41. DPSK
The demodulation circuit 42 extracts a component corresponding to the carrier wave effective in the BPF 42a from the received signal C, and delays this extracted signal with the delay circuit 42.
1 bit is delayed by b (a unit period when the carrier phase is inverted / non-inverted) to generate a delayed signal, and the extracted signal and the delayed signal are multiplied by the multiplication circuit 42c and then delayed through the LPF 42d. By detecting, the phase modulation state is solved, and at the same time, the differential coding state is solved and the demodulated signal D is generated.

Regarding the clock generation method, the circuit 70,
Instead of 71, a clock generation circuit 72 is provided. The clock generation circuit 72 full-wave rectifies the reception signal C by the full-wave rectification circuit 72a to generate a signal having a doubled frequency that does not depend on the phase inversion state of the reception signal C, and tunes this signal by the tank circuit 72b and doubles it. The clock E is generated by amplifying and extracting a signal of only the frequency, and then dividing the signal by 2 in the frequency dividing circuit 72c and binarizing the signal.

The tank circuit 72b is a parallel resonance circuit of a coil and a capacitor, and strongly oscillates at charge and discharge at the resonance frequency. Since the coil needs to be disconnected from the antenna coil 31 which is usually formed by a printed pattern or the like, an individual chip is used instead of the printed pattern or the like.

[0015]

Such a conventional receiver includes an oscillation circuit, a circuit such as a PLL circuit and a tank circuit, and oscillates with charging and discharging.
Since a large amount of power is consumed during such charging / discharging, the power consumption inevitably increases, which is not preferable because the battery life of a portable wireless device using a battery is shortened. On the other hand, in an IC card that does not have a battery and receives power only from the carrier wave for communication, if the power consumption is large, the communication distance is limited, which is still inconvenient.

Further, although coils of individual elements, ceramic oscillators, etc. are also mounted, these are factors that hinder the miniaturization and thinning of the receiver. Especially for IC cards, where convenience greatly affects product value, there is a strong demand for thinner products,
A receiver having the same configuration is inconvenient. Therefore, in order to reduce the power consumption and the thickness of the data transmission / reception system, Japanese Patent Application No. 7-33439 filed by the same applicant.
The invention described in 7 was devised.

This transmission / reception system, whose block diagram is shown in FIG. 4, comprises a transmitter 100 and a receiver 200.
The transmitter 100 is different from the conventional one in that a capacitor 121 is inserted in series between the driver 11 and the antenna coil 12. The capacitor 121 and the antenna coil 12 form a series resonance circuit 120. By doing so, the followability to phase inversion is consciously lowered, and the PSK transmission signal A (see the waveform in FIG. 5A).
The amplitudes of the magnetic signal B and the received signal C are locally suppressed at the phase change point in (Fig. 5 (b)).
See the waveform).

The receiver 200 includes an amplitude suppression point detection circuit 410 for generating an amplitude suppression point detection signal G from the received signal C, and demodulates based on the amplitude suppression point detection signal G. The amplitude suppression point detection circuit 410 receives the received signal C and outputs a full-wave rectified signal I (see the waveform in FIG. 5C), and a full-wave rectified signal I that smoothes the full-wave rectified signal I to obtain an amplitude level. The LPF 412 that outputs the signal H (see the waveform of FIG. 5D) and the amplitude level signal H are compared with a predetermined threshold value and digitized to thereby detect the amplitude suppression point detection signal G (FIG. 5).
(E) Waveform reference)) and a binarization circuit 413. As a result, the receiver 200 receives the PL with charge / discharge.
The PSK signal can be demodulated without using L, the tank circuit, the coil of the individual element, or the oscillator.

If a demodulation system and a clock generation system that do not use an oscillation circuit or the like are implemented on the basis of this, a clock generation circuit 700 is provided to receive the received signal C, although the details of each circuit configuration will be described later. To generate the clock E by rectifying (see FIG. 6) or to provide the digital processing differential code demodulation circuit 430 to perform the reverse processing of the differential coding on the amplitude suppression point detection signal G. It is assumed that it can be extended to DPSK (see FIG. 7).

However, when the demodulation circuit based on the amplitude suppression point detection signal is configured by a digital circuit, the circuit configuration can be simplified without using an oscillation circuit or the like, while the input signal is If noise remains in the amplitude suppression point detection signal, the received content is likely to be erroneous. Specifically, in the simple amplitude suppression point detection circuit 410 as described above, the pulse waveform may be broken in the amplitude suppression point detection signal G (see an example of a two-dot chain line waveform in FIG. 7). The possibility of malfunction increases.

The present invention has been made to solve such a problem, and is a communication system in which a local amplitude such as a phase change point is suppressed when an oscillation circuit or the like is eliminated for downsizing and thinning. The objective is to realize a receiver with high reliability even with a simple circuit that adopts.

[0022]

Means for Solving the Problems First and second solving means invented to solve such problems are as follows.
The configuration and operation and effect will be described below.

[First Solving Means] The receiver of the first solving means (as described in claim 1 at the beginning of the application) is (DPS
Phase change point (or ASK in K system or PSK system)
The amplitude suppression point is detected by the binarization process based on the comparison with a predetermined threshold value from the received signal whose amplitude is locally suppressed in the space etc. , An amplitude suppression point detection circuit that sends out a pulse amplitude suppression point detection signal, and based on this amplitude suppression point detection signal (in the DPSK system, PSK system, ASK system, etc.)
A demodulation circuit that performs demodulation (preferably all digitally), and an internal circuit that receives the demodulation signal of this circuit and performs corresponding processing (such as sampling and data processing) (preferably all digitally) In a predetermined period that exceeds the local period in which the amplitude of the received signal is suppressed (however, it is shorter than the period for one bit of data), when the receiver receives the amplitude suppression point detection signal. A waveform shaping circuit that outputs a single-shot pulse signal of a predetermined width when there is one or more pulses is provided, and the demodulation circuit is based on the output of the waveform shaping circuit instead of the amplitude suppression point detection signal. It is characterized by performing demodulation.

In the receiver of the first solving means as described above, the transmission signal transmitted from the communication partner is received and demodulation and other processing are performed. At this time, when the communication partner modulates the carrier wave, When the transmission signal is generated by locally suppressing the amplitude, it means that the reception signal that received the signal is also locally suppressed in amplitude. Then, the amplitude suppression point is detected from this received signal by the amplitude suppression point detection circuit,
At the time of detection, a pulse amplitude suppression point detection signal is output. Moreover, the amplitude suppression point is detected by the binarization processing based on the comparison with the predetermined threshold value. Therefore, the amplitude suppression point can be detected without using an oscillation circuit such as a carrier recovery circuit including a PLL circuit or a complicated analog delay circuit. Further, the amplitude suppression point detection signal is output as a pulse, and the demodulation circuit and the internal circuit perform demodulation and subsequent processing based on the pulse output.
It can be done with a simple digital circuit.

Further, the demodulation processing by the demodulation circuit is performed not by directly using the amplitude suppression point detection signal, but by using the signal that has once passed through the waveform shaping circuit. When the amplitude suppression point detection signal passes through the waveform shaping circuit, when there is one pulse within a predetermined period exceeding the local period during which the amplitude of the received signal is suppressed, the amplitude suppression point detection signal further includes two or more pulses within the predetermined period. Even if there is a pulse, it is a signal of a single pulse having a predetermined width. Thereby, even when the noise or the like of the received signal cannot be completely removed when the amplitude suppression point is detected, the pulse waveform in the amplitude suppression point detection signal is broken like chattering and a plurality of pulses are output for one amplitude suppression point, In the demodulation circuit, normal demodulation operation is performed based on the single-shot pulse.

Therefore, according to the present invention, downsizing and
It is possible to realize a highly reliable receiver even with a simple circuit that employs a communication method that suppresses local amplitude such as a phase change point when eliminating an oscillation circuit or the like for thinning.

[Second Solving Means] The receiver of the second solving means (as described in claim 2 at the beginning of the application) is the receiver of the first solving means, and is the carrier wave of the received signal. And a clock generation circuit that generates a clock by performing binarization processing, and the internal circuit is a clock synchronous circuit that operates at least in part by receiving the clock.

In the receiver of the second solving means, since the internal circuit is a clock synchronous type circuit, it is resistant to noise and has few malfunctions even with a simple structure. Moreover, the clock supplied to this is generated from the carrier wave of the received signal by the clock generation circuit, but at that time, it is generated by the binarization processing. This makes it possible to generate a clock easily and reliably without providing a tank circuit or an independent oscillation circuit. Since the amplitude suppression of the carrier wave of the received signal is performed only locally, even when the clock is generated by the binarization processing of the carrier wave, the missing clock pulse is limited to the local area. The clock pulse required for the above is sufficiently secured.

Therefore, according to the present invention, downsizing and
A simple circuit configuration that employs a communication method that suppresses the local amplitude such as a phase change point when eliminating the oscillation circuit and the like to reduce the thickness, and particularly when implementing the demodulation method and the clock generation method. It is possible to realize a highly reliable receiver even with a circuit configuration that eliminates.

[Third Solving Means] The receiver of the third solving means (as described in claim 3 at the beginning of the application) is the receiver of the first or second solving means, The signal is D
The demodulation circuit is differentially encoded such as PSK, and the demodulation circuit performs demodulation by performing reverse processing of differential encoding.

In the receiver of the third means as described above, the differentially encoded reception signal is subjected to the inverse processing of the differential encoding by the demodulation circuit and demodulated. When differentially encoded, inversion of the data value is caused at the beginning of valid data in the transmission / reception signal. Therefore, if the amplitude of the carrier is locally suppressed at such an inversion point, the amplitude suppression point can be detected reliably. A pulse of the signal is output, and the pulse can be used as a timing signal for starting demodulation. This makes the demodulation circuit and the like simpler than a digital circuit.

Therefore, according to the present invention, downsizing and
Even if the circuit adopts the communication method in which the local amplitude such as the phase change point is suppressed when the oscillation circuit or the like is eliminated to reduce the thickness, a highly reliable receiver can be realized more easily.

[Fourth Solving Means] The receiver of the fourth solving means (as described in claim 4 at the beginning of the application) is the receiver of the first to third solving means, The data of the signal is bit serialized according to the start-stop synchronization method, and the internal circuit includes a start-stop synchronization type serial-parallel conversion circuit to sample the demodulation signal of the demodulation circuit. It is a feature.

In the receiver of the fourth means as described above, the data of the received signal which has been bit-serialized according to the start-stop synchronization method is sampled by the start-stop synchronization type serial-parallel conversion circuit of the internal circuit. . Since the start-stop synchronization type serial-parallel conversion circuit has been made into a general-purpose IC as a peripheral circuit for serial communication of a microcomputer and is in general distribution, it is useful for downsizing and cost reduction. Also, in the case of the start-stop synchronization method, since the data value is inverted at the beginning of valid data due to the presence of the start bit and the like, it is possible to suppress the amplitude of the carrier wave locally at such an inversion point without fail. A pulse of the amplitude suppression point detection signal is output, and the pulse can be used as a timing signal for starting demodulation or sampling. This makes the demodulation circuit, the sampling circuit, etc. simpler than a digital circuit.

Therefore, according to the present invention, downsizing and
Even if the circuit adopts the communication method in which the local amplitude such as the phase change point is suppressed when the oscillation circuit or the like is eliminated to reduce the thickness, a highly reliable receiver can be realized more easily.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION The first embodiment for carrying out the receiver of the present invention achieved by the first to fourth solving means is the waveform shaping circuit and the demodulating circuit. At least a main part (preferably all) of the internal circuit and the start-stop synchronization type serial-parallel conversion circuit is a digital circuit. This simplifies the configuration and surely eliminates circuits involving charging and discharging, such as PLL circuits, tank circuits, and independent oscillation circuits.

In the second embodiment of these receivers, at least the main parts of the waveform shaping circuit, the demodulation circuit, the internal circuit, and the start-stop synchronization type serial-parallel conversion circuit (preferably all are included). However, it is a clock synchronous type digital circuit which operates by receiving a clock from the clock generation circuit. As a result, even a circuit having a simple configuration in which a circuit involving charge and discharge is excluded is resistant to noise and malfunctions are reduced.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A concrete configuration of an embodiment of a receiver of the present invention will be described with reference to the drawings. FIG. 1 is an overall block diagram thereof, FIG. 2 is a circuit diagram of the demodulation unit thereof, and FIG. 3 is an example of a signal waveform thereof. This receiver 80
0 receives the magnetic signal B transmitted by the transmitter 100 of FIG.

The transmitter 100, which is a communication partner, includes an asynchronous serial / parallel conversion circuit and a modulation circuit (not shown).
The transmission data is bit-serialized by the start-stop synchronization type serial-parallel conversion circuit according to the start-stop synchronization method, the transmission data is differentially encoded by the modulation circuit, and the carrier wave is phase-modulated by the data, for example, 1-bit data. The transmission signal A is generated by phase-modulating 16 cycles of the corresponding carrier wave. Further, as described in the problem to be solved, the series resonance circuit 120 is provided, and the amplitude of the magnetic signal B is locally over, for example, about two cycles of the carrier wave at the phase change point in the transmission signal A of the DPSK system. It is supposed to be suppressed. As a result, the amplitude of the received signal C in the receiver 800 is also locally suppressed at the phase change point.

The receiver 800 includes the receiving circuit 30 already described in the conventional example, the amplitude suppression point detection circuit 410 described in detail in the problem to be solved, the waveform shaping circuit 420, and the differential code demodulation circuit 430 of the digital circuit. A sampling circuit 50 mainly composed of an IC of a start-stop synchronization type serial-parallel conversion circuit, a processing section 60 already described in the conventional example, and a clock generation circuit 7.
00 and the like.

The reception circuit 30 electromagnetically converts the magnetic signal B into the reception signal C and also supplies the power supply voltage Vcc. The amplitude suppression point detection circuit 410 receives the reception signal C and performs full-wave rectification and smoothing. Then, this is compared with a predetermined threshold value by the binarization circuit 413 and digitized to generate the amplitude suppression point detection signal G (see FIG. 3C).
That is, the amplitude suppression point is detected from the received signal C where the amplitude is locally suppressed at the phase change point in the DPSK method, and the amplitude suppression point detection signal of the pulse is transmitted.

The clock generation circuit 700 digitizes the rectified output of the half-wave rectifier circuit 701 that receives the received signal C and a predetermined threshold value near the ground voltage GND, and amplifies the power to provide a sufficient fan-out. And a binarization circuit 702 including a buffer for outputting the clock E (see FIG. 6). This simplifies the process of binarizing the carrier wave of the received signal C to generate a clock. This clock E is (see FIG. 3B),
The clock-synchronous differential code demodulation circuit 430, the sampling circuit 50, and the processing unit 60 are supplied.

The waveform shaping circuit 420 receives the inverted signal of the amplitude suppression point detection signal G as a clock input, the power supply voltage Vcc as a data input, receives the output L of the next shift register 422 as a reset input, and receives the non-inverted output as a single pulse signal J. And a 8-bit shift register 422 which receives the pulse signal M as a data input and a clock E as a clock input.

As will be described later, the pulse signal M is a pulse having a one-clock width generated and output in synchronization with the clock E immediately after the falling transition of the single-shot pulse signal J (FIG. 3 (g)).
reference). Therefore, when the first pulse of the amplitude suppression point detection signal G is input to the D flip-flop 421, the one-shot pulse signal J transits, followed by the pulse of the pulse signal M, and the pulse signal M further shifts. It is delayed by 8 clocks by 422 to become the output L and reset the D flip-flop 421 (see FIG. 3 (f)).
Then, the single-shot pulse signal J makes a reverse transition and returns to the original state. During this period, the D flip-flop 421 has the same value (Vcc) even if the amplitude suppression point detection signal G includes another pulse.
Therefore, regardless of whether the amplitude suppression point detection signal G includes a single pulse or a plurality of pulses, the single-shot pulse signal J is a single pulse for about 8 clocks. (See FIG. 3D).

As a result, the waveform shaping circuit 420 is a clock synchronous digital circuit which operates by receiving the clock E, receives the amplitude suppression point detection signal G, and receives the received signal C.
If there is a pulse of 1 within a predetermined period of 8 clocks that exceeds the local period of about 2 clocks in which the amplitude of is suppressed and is shorter than the period of 1 bit of data, that is, about 16 clocks, 2 within the given period
Even when there is the above pulse, the single-shot pulse signal J having a predetermined width for 8 clocks is output. That is, only one pulse is output for each phase change point.

The differential code demodulation circuit 430 does not directly receive the amplitude suppression point detection signal G, but instead receives the single pulse signal J output from the waveform shaping circuit 420 and performs differential coding based on this. The reverse processing is performed to generate the demodulated signal D. Therefore, first, the differential code demodulation circuit 430 inputs the single-shot pulse signal J, and performs a toggle operation to invert the output value each time the pulse is received, and the JK flip-flop 431 and the JK flip-flop 4.
D flip-flop 432 which receives the output of 31 and latches its value in synchronization with clock E to synchronize the rising / falling edge of the pulse with clock E
By including the single pulse signal J, the digital signal K having a value corresponding to the phase state of the received signal C is generated in synchronization with the clock E (see FIG. 3 (e)).

The differential code demodulation circuit 430 delays the digital signal K by one clock of the clock E and outputs an inverted value of the D flip-flop 433.
And an E-OR gate 434 which receives the digital signal K and the output of the D flip-flop 433 as both inputs and outputs the exclusive OR of these as the pulse signal M. / A pulse signal M having a pulse of 1 clock width is generated and output for each falling edge. In the process of generating the digital signal K from the single-shot pulse signal J described above, the pulse signal M is output in synchronization with the clock E immediately after the falling transition of the single-shot pulse signal J (FIG. 3 (g. )reference).

Further, the differential code demodulation circuit 430 receives the double-frequency timing signal N and the 4-bit binary counter 435 which receives the pulse signal M as a load control input and outputs the most significant bit as the double-frequency timing signal N. A low edge detection circuit 43 that detects the falling transition and outputs a sampling timing signal S of a short pulse.
6 is provided. Therefore, the double frequency timing signal N
Is a digital signal having a 16-clock cycle in which the value normally continues to be inverted every 8 clocks. However, when the pulse of the pulse signal M is received, the inversion timing is matched with this (see FIG. 3 (h)). Even if the waveform of the clock E is slightly disturbed or a pulse is missed at an amplitude suppression point such as a point, the influence is not accumulated. The sampling timing signal S is normally output every 16 clocks, that is, every 1 bit of data (see FIG. 3 (l)).

Further, the differential code demodulation circuit 430 receives the digital signal K as a data input and the double frequency timing signal N as a clock input, and a D flip-flop 437.
And a D flip-flop 438 which receives the non-inverted output O of the D flip-flop 437 as a data input and a double frequency timing signal N as a clock input,
Output O of flop 437 and D flip-flop 438
E-OR gate 439 having both inputs and the non-inverted output P of
Is provided.

In this circuit, the digital signal K indicating the phase state of the received signal C is delayed by 8 clocks, that is, 1/2 bit by the D flip-flop 437 (see FIG. 3 (i)), and further D flipped.・ Flop 43
8 delays 16 clocks, that is, 1 bit (see FIG. 3 (j)). And these are E-OR
The gate 439 multiplies by 1 bit and digitally performs a process equivalent to differential detection. Thus, the demodulated signal D output from the E-OR gate 439 is decoded differentially. In addition, since the pulse of the sampling timing signal S comes at approximately the center of the 16 clock period corresponding to each bit data, the waveform of the clock E may be slightly disturbed or missing at the amplitude suppression point such as the phase change point. However, if it is within 7 clocks, there is no problem (see FIG. 3 (k)).

In summary, the differential code demodulation circuit 430 responds to the fact that the received signal C is differentially coded such as DPSK, based on the amplitude suppression point detection signal G.
It is a digital circuit that demodulates in the K system digitally, and is a clock synchronous digital circuit that operates by receiving the clock E.

The sampling circuit 50 as an internal circuit and the processing unit 60 receive the clock E in order to receive the demodulated signal D and digitally perform the processing such as sampling and data processing corresponding to the demodulated signal D as described above. It is a clock-synchronized digital circuit that operates. In particular, the sampling circuit 50 is provided with an asynchronous serial-parallel conversion circuit in response to the data of the transmission signal A, the reception signal C, and the demodulation signal D being bit-serialized according to the asynchronous method. are doing. As a result, the serial demodulated signal D is taken in according to the sampling timing signal S, converted into parallel data of a predetermined number of bits, and then sent to the processing unit 60.

The specific operation of the receiver of this embodiment will be described. From transmitter 100 to receiver 800,
The case where the original data of the bit pattern “001 ...” Is transmitted will be described as an example.

First, in the transmitter 100, a start bit and a stop bit are added to the original data by the start-stop synchronization type serial-parallel conversion circuit to add the bit pattern "0001 ...
1 "is generated and differentially encoded by the modulation circuit to form a bit pattern" 0100 ... ", and the phase of the carrier wave is modulated corresponding to this bit pattern so as to be inverted / non-inverted every 16 cycles. In this way, the transmission signal A is generated and the magnetic signal B whose amplitude at the phase change point is suppressed is transmitted by the series resonance circuit 120.

Next, in the receiver 800, the receiving circuit 30 electromagnetically converts the magnetic signal B into the receiving signal C and receives the magnetic signal B, and the clock generating circuit 700 generates the clock E from the receiving signal C. Although the clock E is slightly disturbed at the phase change point, it basically becomes a rectangular wave having the same frequency as the carrier wave (see FIG. 3B).

An amplitude suppression point detection signal G is generated from the received signal C by the amplitude suppression point detection circuit 410. In the amplitude suppression point detection signal G, a pulse group appears at the amplitude suppression point, that is, the phase change point. In the case of the data of this example, after the first pulse group appears, the next pulse group appears even after about 16 clocks have elapsed, and does not appear after 16 more clocks have elapsed (see FIG. 3C).

Then, the single-shot pulse signal J is processed from the amplitude suppression point detection signal G by the waveform shaping processing of the waveform shaping circuit 420.
Is generated, and a pulse having an 8-clock width appears at two phase change points, but does not appear thereafter (see FIG. 3D). This is the bit pattern "0100 ..."
Corresponds to (see FIG. 3 (e)).

Furthermore, the demodulation signal D is generated by the differential code demodulation circuit 430 from the single-shot pulse signal J, and the bit pattern "00 ..." Is demodulated with a delay of 8 clocks (FIG. 3).
(See (k)). Then, the demodulated signal D is sampled by the sampling circuit 50. That is, the preparation for sampling is started with the first bit “0” as the start bit, and sampling is performed at the center of each bit based on the timing signal S.

In this way, the bit pattern string "001 ..." Of the original data excluding the start bit and the like is reproduced, and the processing unit 60 performs processing according to the data content.

Although the DPSK system communication has been described above as an example, the phase inversion process for the carrier wave is not performed,
Even in the case of the modulation method in which the amplitude is suppressed only at the position corresponding to the phase change point in the transmission / reception signal in the DPSK method, that is, in the modified ASK method, the clock waveform at the amplitude suppression point is the DPSK method (FIG. 3B). It is possible to directly apply the present invention, since the other signals are exactly the same as those described above (see FIG. 3A).

[0061]

As is apparent from the above description, in the receiver of the first solving means of the present invention, even when the pulse waveform in the amplitude suppression point detection signal is broken, one amplitude suppression point is detected. Is a simple circuit that employs a communication method that suppresses the local amplitude such as the phase change point when eliminating the oscillation circuit for size and thickness reduction by shaping the waveform so that it becomes a single pulse. Has an advantageous effect that a highly reliable receiver can be realized.

Further, in the receiver of the second solution of the present invention, the clock is generated from the carrier wave of the received signal by the binarization process and the internal circuit is of the clock synchronous type, so that it is simple and simple. Even with such a circuit configuration, it is possible to reliably eliminate the oscillation circuit and ensure high reliability.

Further, in the receiver of the third and fourth solving means of the present invention, by adopting the differential encoding method and the start-stop synchronization method which are compatible with the communication method in which the local amplitude is suppressed, There is an advantageous effect that the demodulation circuit and the sampling circuit can be made simpler than those simply made into digital circuits.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a receiver of the present invention.

FIG. 2 is a circuit diagram of the demodulation unit (DPS
K).

FIG. 3 is a waveform example of the signal.

FIG. 4 is a block diagram of a transmission / reception system of the existing invention.

FIG. 5 is a waveform example of the signal.

FIG. 6 is an assumed block diagram when a latter part is added to it.

FIG. 7 is a partial detailed view of the receiver.

FIG. 8 is an example of a conventional transmission / reception system (AS
K).

FIG. 9 is another example of a conventional transmission / reception system (PSK).

FIG. 10 is another example of a conventional transmission / reception system (DPSK).

[Explanation of symbols]

10 transmitter 11 driver 12 antenna coil 20 receiver 21 receiver 22 receiver 30 receiving circuit 31 antenna coil 32 capacitor 33 diode bridge 34 smoothing circuit 40 ASK demodulation circuit 40a BPF (bandpass filter) 40b rectifier circuit 40c LPF (low pass filter) ) 41 PSK demodulation circuit 41a BPF (bandpass filter) 41b carrier recovery circuit 41c multiplication circuit 41d LPF (lowpass filter) 42 DPSK demodulation circuit 42a BPF (bandpass filter) 42b delay circuit 42c multiplication circuit 42d LPF (lowpass filter) 50 sampling Circuit (start-stop synchronization type serial-parallel conversion circuit; internal circuit) 60 Processing unit (MPU; Microprocessor; internal circuit) 70 Oscillation circuit 71 Clock generation circuit 72 Black Generator circuit 72a full-wave rectifier circuit 72b tank circuit 72c frequency divider circuit 100 transmitter 120 series resonance circuit (amplitude suppressing means during phase change) 121 capacitor 200 receiver 200 410 amplitude suppression point detection circuit 411 full-wave rectifying circuit 412 LPF ( Low-pass filter) 413 Binarization circuit 420 Waveform shaping circuit 421 D flip flop 422 Shift register 430 Differential code demodulation circuit 431 JK flip flop (toggle circuit) 432 D flip flop (latch) 433 D flip flop (1) Clock delay) 434 E-OR gate (Exclusive-OR; pulsed) 435 Binary counter (sampling timing determination) 436 Low edge detection circuit (sampling timing signal generation) 437 D flip-flop (latch) ) 438 D flip-flop (1 bit delay) 439 E-OR gates (Exclusive-OR; 1-bit multiplier) 700 clock generation circuit 701 half-wave rectifier circuit 702 binarizing circuit 800 receiver

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Megumi Iiyama 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. In the company

Claims (4)

[Claims] 1. A pulse amplitude suppression point detection signal is obtained by detecting an amplitude suppression point from a received signal whose amplitude is locally suppressed at a phase change point or the like by binarization processing based on comparison with a predetermined threshold value. A receiver provided with an amplitude suppression point detection circuit for sending, a demodulation circuit for demodulating based on the amplitude suppression point detection signal, and an internal circuit for receiving a demodulation signal of this circuit and performing processing in accordance therewith. When the amplitude suppression point detection signal is received, a single-shot pulse signal having a predetermined width is output when there is one or more pulses within a predetermined period exceeding the local period in which the amplitude of the reception signal is suppressed. A receiver comprising a waveform shaping circuit, wherein the demodulation circuit performs demodulation based on an output of the waveform shaping circuit instead of the amplitude suppression point detection signal. 2. A clock generation circuit that performs a binarization process from a carrier wave of the received signal to generate a clock, and the internal circuit is a clock synchronous circuit that operates at least in part by receiving the clock. The receiver according to claim 1, wherein the receiver is provided. 3. The demodulation circuit, when the received signal is DPSK
The receiver according to claim 1 or 2, wherein the receiver is a device that performs inverse processing of differential encoding and demodulates in response to being differentially encoded. 4. The demodulation circuit, wherein the internal circuit comprises an asynchronous serial-parallel conversion circuit in response to the data of the received signal being bit serialized in accordance with the asynchronous method. 4. The receiver according to claim 1, wherein the receiver demodulates the demodulated signal.