JPH09294272A - Information signal processing circuit - Google Patents

Abstract

(57) Abstract: A color frame start timing (first field) can be detected easily and surely even if the SCH is deviated. A counter 11 for generating a detection pulse C1 used to detect a first field, a DFF circuit 12 for detecting a phase 0 degree of a burst signal BP based on the detection pulse C1, and a DFF circuit 12 are provided. Timing deviation detection circuit 13 for detecting deviation of SCH from output Sc1
, A counter 21 for generating a detection pulse C2 used for detecting the third field, and a DFF circuit 22 for detecting the phase 180 degrees of the burst signal BP based on the detection pulse C2. A second detection circuit 2 having a timing shift detection circuit 23 for detecting a shift of the SCH from the output Sc1 of the DFF circuit 22;
And a count generation circuit 3 that cyclically updates and outputs the initial value of each counter in accordance with the detection results of the second detection circuits 1 and 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information signal processing circuit, and more particularly to an information signal processing circuit suitable for detecting a color frame from a color video signal.

[0002]

2. Description of the Related Art Generally, a composite sync signal in the NTSC system is repeated every two fields. However, considering the relationship with the phase of a color subcarrier, one field is obtained in four fields.
Cycle. This is called a so-called 4-field sequence, and the relationship between the horizontal synchronizing signal (HD) and the color carrier wave is SC.
It is called H (Sub Carrier to Horizontal).

Specifically, for example, in the first field, the signal waveform of 1H (1 horizontal scanning period) in the vertical blanking period is a waveform including a horizontal synchronizing signal, a reference level and a pedestal level. The period from the start time to 3 horizontal scanning periods (3H) is the pre-equalization pulse period, the vertical synchronization pulse period is from the start time of 4H to the end time of 6H, and the equalization pulse is from the start time of 7H to the end time of 9H. It is considered to be the later period. Then, the color burst signal is superimposed from 10H in the vertical blanking period, and 21H
Is a signal in which the actual video signal is superimposed.

Further, the phases of the color burst signals in the first field and the third field are in opposite phase to each other. The PAL video signal has a signal waveform in which a color burst signal is added from 6H in the vertical blanking period, and the phases of the color burst signals in the first field and the fifth field are opposite to each other. .

Therefore, if the first field and the third field can be discriminated in the NTSC system video signal and the first field and the fifth field in the PAL system video signal, it is easy to detect the first field, that is, the color frame. You can do it.

That is, in the NTSC system, it suffices to check whether the phase of the burst signal on the 10th line (10H) of the first and third fields is 0 degrees or 180 degrees, and in the PAL system, 6 lines of the first and fifth fields. It suffices to check whether the phase of the burst signal of the eye (6H) is 0 degree or 180 degrees.

Here, the case of detecting the phase of the burst signal will be described. First, the burst signal superimposed on the analog composite video signal is cut out in pulses using a comparator. In this case, if the reference level of the comparator is set to the pedestal level, the DUTY ratio of the pulse signal cut out by the comparator can be set to 50% as shown in FIG. In the following description, the pulse signal cut out by the comparator is referred to as a burst pulse signal for convenience.

When detecting the phase of the burst pulse signal, for example, the burst pulse signal BP1 is detected by the detection pulse C which rises at the time when the first pulse of the burst pulse signal BP1 in the 10th line (10H) of the first field arrives. It can be realized by detecting the level. In FIG. 4, BP3
(Or BP5) indicates a burst pulse signal in the third field of the NTSC system (or the fifth field of the PAL system).

As a circuit for detecting the phase of the burst signal from the burst pulse signal BP, for example, as shown in FIG. 5, a counter 101 and a D-flip-flop circuit 1 are provided.
A circuit configured with 02 can be used.

The counter 101 is supplied to its enable terminal with only the 1H horizontal sync signal SYNC in the first and third fields in the NTSC system and in the first and fifth fields in the PAL system. The wiring is connected so that a clock Pc of 27 MHz, for example, is input to the clock terminal. Then, the clock Pc input to the clock terminal is counted on the basis of the input of the horizontal synchronizing signal SYNC to the enable terminal, and when the predetermined count value A is reached, that is, the burst in the 10th line (10H) of the first field. At the same time that the carry signal C is output to the D-flip-flop circuit 102 at the stage when the count value corresponding to the time when the first pulse of the pulse signal BP arrives,
For example, the count value is reset to 0.

The D-flip-flop circuit 102 is wired and connected so that the burst pulse signal BP is input to the data input terminal D and the carry signal C from the counter 101 is input to the clock terminal.

The operation of this circuit will be briefly described. First, in the counter 101, the horizontal synchronizing signal SY of 1H is generated.
Based on the input to the enable terminal of NC, the clock P
The counting of c is started. The count value is the predetermined count value A.
The carry signal C is output at the stage where the signal becomes, and the carry signal C is input to the clock terminal of the D-flip-flop circuit 102.

Then, the D-flip-flop circuit 102
The burst pulse signal BP when the carry signal C is input (at the rising edge) from the Q terminal of the
Will be output as is as the detection signal Sc. In this case, the output timing of the carry signal C is 10H burst pulse signal B in the first field.
Since it is synchronized with the first pulse output period of P, the signal waveform of the detection signal Sc output from the Q terminal of the D-flip-flop circuit 102 is synchronized with the output timing of the carry signal C in the first field. In the third field of NTSC (or the fifth field of PAL), the waveform rises in synchronization with the output timing of the carry signal C.

The rising of the detection signal Sc is equivalent to the detection of the phase 0 degree of the burst signal BP, and the falling of the detection signal Sc is the phase 1 of the burst signal BP.
Since it is equivalent to detecting 80 degrees, the rising of the detection signal Sc means that the color frame (first field) of the 4-field sequence is detected.

[0015]

By the way, in the comparator for cutting out the color burst signal in a pulse shape, the reference level of the comparator is provided with hysteresis so as not to be influenced by the noise of the signal, so that it is not influenced by the noise. .

When the burst signal is cut out in a pulse shape by the comparator having this hysteresis, as shown in FIG. 6, the DUTY ratio of the cut out burst pulse signal BP does not become 50%, for example, high. The level period / low level period = 1/3, and the low level period is longer than the high level period.

When the burst pulse signal BP whose duty ratio is not 50% is input to the data input terminal D of the D-flip-flop circuit 102 and the carry signal C from the counter 101 detects the phase of the burst signal, the following is performed. Inconvenience may occur.

That is, when the relationship (SCH) between the horizontal synchronizing signal and the color carrier is deviated or deviated from the beginning, in the circuit of FIG. 5, after a certain period of time from the 1H horizontal synchronizing signal SYNC in the first field. When it is attempted to detect the phase of the burst signal, as shown in FIG. 6A, for example, the carry signal C rises in the low level period of the burst pulse signal BP1 of the first field, and the third field of NTSC (or the fifth field of PAL). The carry signal C rises during the high level period of the burst pulse signal BP3 (or BP5), and the phase detection of the burst signal is reversed, and the third field of NTSC (or the fifth field of PAL) is changed. There is a problem that it is recognized as the first field.

In particular, as shown in FIG. 6B, the burst pulse signal BP1 of the first field is in the low level period and the burst pulse signal BP3 (or BP5) of the third field of NTSC (or the fifth field of PAL) is used. 6 is a low level period, that is, when the carry signal C rises during the period indicated by b in FIG. 6B, it becomes impossible to determine whether the phase of the burst signal is 0 degree or 180 degrees. However, there is a problem that the color frame cannot be detected.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a start timing of an information signal (in the above example, even if the position of a reference signal is deviated with a simple circuit configuration). It is to provide an information signal processing circuit capable of easily and reliably detecting the first field).

[0021]

An information signal processing circuit according to the present invention detects an alternating attribute of a reference signal superposed on an information signal with a predetermined timing relationship to detect a start timing of the information signal. In the information signal processing circuit, a detection pulse generation circuit that generates a detection pulse according to the predetermined timing relationship, and a timing deviation detection that detects a deviation of the predetermined timing relationship based on the detection result of the reference signal by the detection pulse A circuit and a pulse generation adjustment circuit for adjusting the generation timing of the detection pulse based on the detection result from the timing shift detection circuit are provided.

Thus, first, the detection pulse is output from the detection pulse generation circuit in accordance with the above-mentioned predetermined timing relationship, and the reference signal is detected based on this detection pulse. At this time, if the predetermined timing relationship is deviated, the timing deviation detection circuit detects the timing deviation based on the detection result of the reference signal by the detection pulse.

The detection result of this timing shift circuit is
It is supplied to the pulse generation adjustment circuit in the subsequent stage, and the generation timing of the detection pulse in the detection pulse generation circuit is adjusted based on the detection result in the pulse generation adjustment circuit. By this adjustment, the alternating attribute of the reference signal can be detected well, and the start timing of the information signal can be detected easily and surely.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an example of an embodiment in which an information signal processing circuit according to the present invention is applied to a color frame detection circuit for detecting a 4-frame sequence color frame from a composite color video signal (hereinafter, simply referred to as an embodiment) The color frame detection circuit according to the present invention) will be described with reference to FIGS. For the sake of simplicity, the description will be made with reference to the case of detecting a color frame from an NTSC color video signal.

As shown in FIG. 1, the color frame detection circuit according to this embodiment detects the first field from the burst pulse signal BP and the first field from the burst pulse signal BP. Second to detect
Detection circuit 2 and a count generation circuit 3 that cyclically outputs a count value according to the detection results of the first and second detection circuits 1 and 2.

The first detection circuit 1 generates a first detection pulse C1 used for detecting the first field.
Counter 11 and a first D-flip-flop circuit 12 (hereinafter, simply referred to as a first DFF circuit) that detects the phase 0 degree of the burst signal BP based on the detection pulse C1 from the first counter 11. And the first DFF circuit 12
And a first timing shift detection circuit 13 for detecting the shift of the SCH from the output Sc1.

The first counter 11 has a register 14 in which an initial value is stored, and is configured to read the initial value from the register 14 at the time of resetting the count and start counting from the initial value. There is.

Further, the first counter 11 is wired and connected to its enable terminal so that only the 1H horizontal synchronizing signal SYNC in the first field and the third field is supplied, and its clock terminal is, for example, 27 MHz.
The wiring is connected so that the clock Pc of is input.

Then, the clock Pc input to the clock terminal is counted on the basis of the input of the horizontal synchronizing signal SYNC to the enable terminal, and reaches a predetermined count value A,
That is, the detection pulse (carry signal) C1 is output at the stage when the count value corresponds to the time when the first pulse of the burst pulse signal BP1 in the 10th line (10H) of the first field arrives, and at the same time the count value is reset. (Set to the initial value).

The first DFF circuit 12 is wired and connected so that the burst pulse signal BP is input to the data input terminal D and the carry signal C1 from the first counter 11 is input to the clock terminal.

The first timing shift detection circuit 13 has a value of 1
Comprised of an H delay circuit 15 and a NOR circuit 16,
The output Sc1 of the first DFF circuit 12 is directly input to one input terminal of the circuit 16, and the first DF is input to the other input terminal.
1H delay signal dSc1 of output Sc1 of F circuit 12 is 1H
The wiring is connected so that the signal is input via the delay circuit 15.

The second detection circuit 2 generates a second detection pulse C2 used for detecting the third field.
Counter 21 and a second D-flip-flop circuit 22 (hereinafter, referred to as a second D-flip-flop circuit 22 for detecting the phase 180 degrees of the burst signal BP based on the detection pulse C2 from the second counter 21).
And a second timing shift detection circuit 23 that detects a shift of SCH from the output Sc2 of the second DFF circuit 22.

Like the first counter 11, the second counter 21 has a register 24 in which an initial value is stored. When the counter is reset, the initial value is read from the register 24 and the initial value is read. It is configured to start counting from.

The second counter 21 is wired so that its enable terminal is supplied with only the horizontal synchronizing signal SYNC of 1H in the first and third fields, and its clock terminal is, for example, 27 MHz.
The wiring is connected so that the clock Pc of is input.

Then, the clock Pc input to the clock terminal is counted based on the input of the horizontal synchronizing signal SYNC to the enable terminal, and reaches a predetermined count value B,
That is, the detection pulse (carry signal C2) is output at the same time when the count value corresponding to the arrival time of the first pulse of the burst pulse signal BP3 in the 10th line (10H) of the third field is reached, and at the same time the count is reset. Is configured.

The second DFF circuit 22 is wired and connected so that the burst pulse signal BP is input to the data input terminal D and the carry signal C2 from the second counter 21 is input to the clock terminal.

The second timing deviation detection circuit 23 has
The NOR circuit is composed of an H delay circuit 25 and a NOR circuit 26.
The output Sc2 of the second DFF circuit 22 is directly input to one input terminal of the circuit 26, and the second DF is input to the other input terminal.
The 1H delay signal dSc2 of the output Sc2 of the F circuit 22 is 1H.
It is connected by wiring so as to be input via the delay circuit 25.

The count generation circuit 3 is a NOR circuit 1 in each of the first and second timing deviation detection circuits 13 and 23.
Negatively inputs the outputs Sp1 and Sp2 from 6 and 26,
Fall timing of the negative input (each NOR circuit 1
A monostable multivibrator 31 (simply referred to as an MM circuit) that outputs a count generation signal Sg having a predetermined pulse width at the rising timings of the outputs Sp1 and Sp2 of 6 and 26).
And, for example, three count values (0, + α and −α) are stored, and the count values (0, + α and −α) are cyclically output for each input of the count generation signal Sg from the MM circuit 31. And a register 32.

The count values (0, + α and −α) output from the register 32 are supplied to the registers 14 and 24 in the first and second counters 11 and 21, respectively. In this embodiment,
Each time the count generation signal Sg is output from the MM circuit 31, the register 32 is set to output a count value such as 0 → + α → −α → 0 → + α.

The value of α is, for example, as shown in FIG. 3, the burst pulse signal BP1 of the first field and the third pulse
When the start times of the burst pulse signals BP3 of the fields are the same, the center of the first field from the center of the period from the falling time of the burst pulse signal BP1 of the first field to the rising time of the burst pulse signal BP3 of the third field Burst pulse signal BP1
Is a count value corresponding to the period up to the center of the high level period (or the center of the low level period of the burst pulse signal BP3 of the third field).

Next, the operation of the color frame detection circuit according to the above embodiment will be described with reference to the timing charts of FIGS.

First, in the first counter 11 of the first detection circuit 1, the counting of the clock Pc is started based on the input of the 1H horizontal synchronizing signal SYNC to the enable terminal. Then, when the count value reaches the predetermined count value A, the carry signal C1 is output, and the carry signal C
1 is input to the clock terminal of the first DFF circuit 12.

From the Q terminal of the first DFF circuit 12, the level of the burst pulse signal BP when the carry signal C1 is input (at the rising edge) to the clock terminal is output as it is. In this case, the output timing of the carry signal C1 is 1 in the first field.
Since it is synchronized with the first pulse output period of the 0H burst signal BP1, the signal waveform of the detection signal Sc1 output from the Q terminal of the first DFF circuit 12 is in the first field unless the SCH is shifted. , Rises in synchronization with the output timing of the carry signal C1,
In the field, the waveform falls in synchronization with the output timing of the carry signal C1.

The rise of the detection signal Sc1 is equivalent to the detection of the phase 0 degree of the burst signal BP,
Since the fall of the detection signal Sc1 is equivalent to the detection of the phase 180 degrees of the burst signal BP, it means that the color frame (first field) of the 4-field sequence is detected by the rise of the detection signal Sc1. Become. The output Sc1 of the first DFF circuit 12
Is supplied to the subsequent processing circuit system through the contact a.

On the other hand, in the second counter 21 in the second detection circuit 2, counting of the clock Pc is started based on the input of the horizontal synchronizing signal SYNC of 1H to the enable terminal. When the count value reaches the predetermined count value B, the carry signal C2 is output, and the carry signal C2 is input to the clock terminal of the second DFF circuit 22.

From the Q terminal of the second DFF circuit 22, the level of the burst pulse signal BP when the carry signal C2 is input (at the rising edge) to the clock terminal is output as it is. In this case, the output timing of the carry signal C2 is 1 in the third field.
Since it is aligned with the first pulse output period of the burst signal BP3 of 0H, the signal waveform of the detection signal Sc2 output from the Q terminal of the second DFF circuit 22 is in the first field unless the SCH is shifted. , Falling in synchronization with the output timing of the carry signal C2,
In the field, the waveform rises in synchronization with the output timing of the carry signal C2.

The rising of the detection signal Sc2 is equivalent to the detection of the phase 180 degrees of the burst signal BP, and the falling of the detection signal Sc2 is the burst signal BP.
Is equivalent to detecting the phase 0 degree of.

Next, the case where the SCH is shifted will be described. First, in FIG. 2, at t0 when the burst pulse signal BP1 of the first field is input,
As shown in FIG. 3, in the first detection circuit 1, the carry signal C1 rises in the high level period of the burst pulse signal BP1, and in the second detection circuit 2, the carry signal C2 in the low level period of the burst pulse signal BP1. Is rising, the output Sc1 of the first DFF circuit 12 is at high level, and the second DFF circuit 22
Output Sc2 becomes low level, and the first field is normally detected by the first detection circuit 1 as described above.

In FIG. 2, at time t1 when the burst pulse signal BP3 of the third field is input next,
As shown in FIG. 3, in the first detection circuit 1, the carry signal C1 rises in the low level period of the burst pulse signal BP3, and in the second detection circuit 2, the carry signal C2 in the high level period of the burst pulse signal BP3. Is rising, the output Sc1 of the first DFF circuit 12 is low level, and the second DFF circuit 22
Output Sc2 becomes high level, and this time, the second field is normally detected by the second detection circuit 2.

While the first field is normally detected by the first detection circuit 1, a high level signal and a low level signal are input to the NOR circuit 16 of the first timing shift detection circuit 13, respectively. Therefore, the NOR circuit 1
6 continues to output the low-level detection signal Sp1. Similarly, while the second field is normally detected by the second detection circuit 2, the second timing deviation detection circuit 2
Since the low-level signal and the high-level signal are respectively input to the NOR circuit 26 of No. 3, the low-level detection signal Sp2 continues to be output from the NOR circuit 26.

The initial values stored in the registers 14 and 24 of the first and second counters 11 and 21 at this time are set to 0, for example.

When the SCH shifts after t1 and the burst signal BP has a delay phase with respect to the horizontal synchronizing signal SYNC, for example, at t2 when the burst pulse signal BP1 of the first field is input next, As shown in FIG. 3, in the first detection circuit 1, the carry signal C1 is generated during the low level period of the burst pulse signal BP1.
Rises, and the carry signal C is generated in the second detection circuit 2 during the low level period of the burst pulse signal BP1.
Since 2 has risen, as shown in FIG. 2, both the first and second DFF circuits 12 and 22 output low-level detection signals Sc1 and Sc2. At this time,
In the first timing shift detection circuit 13, the low-level detection signal Sc1 is output from the first DFF circuit 12, and at the same time, the low-level delay signal dSc1 is also output from the 1H delay circuit 15. , The first NOR
The circuit 16 outputs the high-level detection signal Sp1.

Since the rising edge of the output Sp1 of the first NOR circuit 16 serves as a trigger signal for the MM circuit 31 of the count generating circuit 3, the MM circuit 31 simultaneously outputs the count generating signal Sg having a predetermined pulse width at the same time as the rising edge. Is output.

The register 32 at the subsequent stage outputs the count value + α next to the count value 0 based on the input of the count generation signal Sg. The count value + α is stored in the registers 14 and 24 of the counters 11 and 21, respectively. Therefore, in each of the counters 11 and 21, the initial value is set to + α at the same time when the counters are reset.

When the horizontal synchronizing signal SYNC of 1H is input after the initial values of the counters 11 and 21 are set to + α, the counters 11 and 21 start the clock Pc from + α.
Is started, and carry signals C1 and C2 are output when the predetermined count values A and B are reached. In this case, carry signals C1 and C2 are output at a time + α earlier than when the initial value is 0.

Then, at the time t3 when the burst pulse signal BP3 of the third field is input next, as shown in FIG. 3, in the first detection circuit 1, the carry signal is in the high level period of the burst pulse signal BP3. C1
Rises, and the carry signal C is generated in the second detection circuit 2 during the low level period of the burst pulse signal BP3.
2 rises, the first and second DFFs are
High-level and low-level detection signals Sc1 and Sc2 are output from the circuits 12 and 22, respectively. At this time, in the second timing shift detection circuit 23, the second D
Since the FF circuit 22 outputs the low-level detection signal Sc2 and the 1H delay circuit 25 also outputs the low-level delay signal dSc2, the second NOR circuit 26 outputs the high-level detection signal Sc2. Sp2 is output.

Since the rising edge of the output Sp2 of the second NOR circuit 26 serves as a trigger signal for the MM circuit 31 of the count generating circuit 3, the MM circuit 31 outputs the count generating signal Sg having a predetermined pulse width simultaneously with the rising edge. Is output.

The register 32 at the subsequent stage outputs the count value −α next to the count value + α based on the input of the count generation signal Sg. This count value-α is used for each counter 11 and 21.
Are stored in the registers 14 and 24 of. Therefore, in each of the counters 11 and 21, at the same time when the count is reset, its initial value is set to -α this time.

When the horizontal synchronizing signal SYNC of 1H is input after the initial values of the counters 11 and 21 are set to -α, the counters 11 and 21 start clocking Pc from -α.
Is started, and carry signals C1 and C2 are output when the predetermined count values A and B are reached. In this case, the carry signals C1 and C2 are respectively output at a time that is + α later than when the initial value is 0.

Then, at time t4 when the burst pulse signal BP1 of the first field is input next, as shown in FIG. 3, in the first detection circuit 1, the carry signal is in the high level period of the burst pulse signal BP1. C1
Rises, and the carry signal C is generated in the second detection circuit 2 during the low level period of the burst pulse signal BP1.
2, the high and low detection signals Sc1 and Sc2 are output from the first and second DFF circuits 12 and 22, respectively, as shown in FIG. The first field is normally detected by the detection circuit 1 of FIG.

Next, at the time t5 when the burst pulse signal BP3 of the third field is input, as shown in FIG.
Since the carry signal C1 rises in the low level period of P3 and the carry signal C2 rises in the high level period of the burst pulse signal BP3 in the second detection circuit 2, as shown in FIG.
A low level detection signal Sc1 is output from the F circuit 12,
The high level detection signal Sc2 is output from the second DFF circuit 22, and this time, the third field is normally detected by the second detection circuit 2 as at t1.

When the SCH shifts again after the normal detection continues and the burst signal BP has the lead phase this time with respect to the horizontal synchronizing signal SYNC, the burst pulse signal BP1 of the first field is input next t6. At this time, as shown in FIG. 3, in the first detection circuit 1, the carry signal C1 rises in the low level period of the burst pulse signal BP1, and in the second detection circuit 2,
Since the carry signal C2 rises in the low level period of the burst pulse signal BP1, both the low level detection signals Sc1 and Sc2 are output from the first and second DFF circuits 12 and 22, as shown in FIG. A high-level detection signal Sp1 is output from the first NOR circuit 16.

As a result, the count value 0 next to the count value -α is output from the register 32 in the count generation circuit 3. This count value 0 is stored in the registers 14 and 24 of the counters 11 and 21, respectively, and in each of the counters 11 and 21, the initial value is 0 when the count is reset.
It is said.

When the horizontal synchronizing signal SYNC of 1H is input after the initial values of the counters 11 and 21 are set to 0, the counters 11 and 21 start counting the clock Pc from 0, and the predetermined count value A And B, carry signals C1 and C2 are output, respectively. in this case,
The carry signals C1 and C2 are output at a timing + α earlier than when the initial value is −α.

Then, at time t7 when the burst pulse signal BP3 of the third field is input next, as shown in FIG. 3, in the first detection circuit 1, the carry signal is generated in the low level period of the burst pulse signal BP3. C1
Rises, and the carry signal C is generated in the second detection circuit 2 during the high level period of the burst pulse signal BP3.
2 rises, as shown in FIG. 2, the low-level and high-level detection signals Sc1 and Sc2 are output from the first and second DFF circuits 12 and 22, respectively. Therefore, the third field is normally detected by the detection circuit 2 of FIG.

Next, at time t8 when the burst pulse signal BP1 of the first field is input, as shown in FIG. 3, in the first detection circuit 1, the burst pulse signal B
Since the carry signal C1 rises during the high level period of P1 and the carry signal C2 rises during the low level period of the burst pulse signal BP1 in the second detection circuit 2, the first and second DFF circuits 12
22 and 22 output high-level and low-level detection signals Sc1 and Sc2, respectively, and the first field is normally detected by the first detection circuit 1 as at t0.

As described above, in the color frame detection circuit according to this embodiment, when the phase of the burst signal BP in the first field cannot be detected due to the shift of SCH, the shift is detected as the timing shift detection circuits 13 and 23. Detected by the counting generation circuit 3 based on the detection.
Therefore, a predetermined initial value is output to each of the counters 11 and 21. As a result, the clock counting time up to the predetermined count values A and B in the counters 11 and 21 is changed, and the output timing of the carry signals C1 and C2 for detecting the high / low of the burst pulse signal BP is SCH. It changes depending on the shift, and as a result, the phase of the burst signal BP in the first field is detected.

In the above example, the case of detecting the head (first field) of the color frame from the color video signal of the NTSC system has been described. In addition, the head of the color frame (first field) from the color video signal of the PAL system is detected. It can also be applied to the case of detecting.

In this case, the enable terminals of the counters 11 and 21 are supplied with only the horizontal sync signal SYNC of 1H in the first field and the fifth field, and the predetermined count value A in the first counter 11 is set. , The count value corresponding to the time when the first pulse of the burst pulse signal BP1 in the 6th line (6H) of the first field arrives, and the predetermined count value B in the second counter 21 is the 6th line of the 5th field. The count value may correspond to the time when the first pulse of the burst pulse signal BP5 at the (6H) th time arrives.

[0070]

As described above, according to the information signal processing circuit of the present invention, the alternating attribute of the reference signal superimposed on the information signal with a predetermined timing relationship is detected to start the information signal. In the information signal processing circuit for detecting the timing, the deviation of the predetermined timing relationship is detected based on the detection pulse generating circuit that generates the detection pulse according to the predetermined timing relationship and the detection result of the reference signal by the detection pulse. Since the timing deviation detection circuit and the pulse generation adjustment circuit that adjusts the generation timing of the detection pulse based on the detection result from the timing deviation detection circuit are provided, the position of the reference signal is deviated with a simple circuit configuration. Even in the case of the above, the start timing of the information signal (first field in the above example) can be detected easily and surely. Can.

[Brief description of drawings]

FIG. 1 is an example of an embodiment in which an information signal processing circuit according to the present invention is applied to a color frame detection circuit for detecting a 4-frame sequence color frame from a composite color video signal (hereinafter, simply color frame detection according to the embodiment). 3 is a block diagram showing a configuration of a circuit).

FIG. 2 is a timing chart (No. 1) showing the signal processing of the color frame detection circuit according to the present embodiment.

FIG. 3 is a timing chart (No. 2) showing the signal processing of the color frame detection circuit according to the present embodiment.

FIG. 4 is a timing chart showing a detection principle when detecting a phase of a burst signal.

FIG. 5 is a block diagram showing a conventional circuit for detecting the phase of a burst signal.

FIG. 6 is an explanatory diagram showing conventional disadvantages.

[Explanation of symbols]

1 and 2 1st and 2nd detection circuits, 3 count generation circuits, 11 and 21 1st and 2nd counters, 12 and 22 1st and 2nd DFF circuits, 13 and 23 1st and 2nd timing Deviation detection circuit

Claims (5)

[Claims] 1. An information signal processing circuit for detecting an alternation attribute of a reference signal superimposed on an information signal with a predetermined timing relationship set in advance to detect a start timing of the information signal, the detection being performed according to the predetermined timing relationship. A detection pulse generation circuit that generates a pulse, a timing deviation detection circuit that detects a deviation of the predetermined timing relationship based on the detection result of the reference signal by the detection pulse, and a detection result from the timing deviation detection circuit And a pulse generation adjusting circuit for adjusting the generation timing of the detection pulse. 2. The detection pulse generation circuit counts a reference clock based on the input of a synchronization signal included in the information signal, and outputs the detection pulse when the count value reaches a count value according to the predetermined timing relationship. The information signal processing circuit according to claim 1, wherein the information signal processing circuit comprises an output counter. 3. The timing shift detection circuit detects the timing shift based on the detection result of the reference signal by the current detection pulse and the detection result of the reference signal by the previous detection pulse. An information signal processing circuit according to claim 1 or 2. 4. The information signal processing circuit according to claim 1, wherein the pulse generation adjusting circuit makes the initial value of the counter variable based on the detection result of the timing shift detecting circuit. . 5. The information signal is a video signal and the reference signal is a burst signal.
(4) The information signal processing circuit described in any one of (1) to (4).