JPH09294367A - Voltage supply circuit - Google Patents

Abstract

(57) [Summary] A power supply voltage used over a wide range
Power supply of the clock signal frequency that can be supplied to the booster circuit
The voltage dependence can be eliminated and the ripple of the output voltage can be suppressed.
Realizes a voltage supply circuit that can supply a stable boosted voltage
I do. SOLUTION: The power supply voltage V_CCWorks with
Boosted voltage V during normal operation _OUTWith the oscillator 10 operating at
Generates a clock signal CLK and supplies it to the booster circuit 30.
Then, the boosted voltage V of the booster circuit 30_OUTThe resistance element R_L1, R
_L2And the comparator 40 divides the voltage by_TAnd reference voltage
V_refAnd the operation control signal CS according to the comparison result.
By generating S and controlling the operation of the oscillator 10,
Pressure V_OUTSince the level of is kept constant, the oscillator 10
The frequency of the clock signal CLK generated by the
Power supply voltage V_CCHold constant against
Boosted voltage V_OUTRipple can be suppressed and the temperature rises steadily.
Pressure voltage V_OUTCan be supplied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage supply circuit for supplying a boosted voltage to a semiconductor memory device, for example.

[0002]

2. Description of the Related Art Generally, in a flash EEPROM, in the case of low voltage operation, a boosted voltage is applied to a word line at the time of writing and reading in order to secure an operation margin of a memory transistor or realize a high speed access. Is generally done. For example, even if the power supply voltage V _CC is 3.6 V or less, the boosted voltage of 4 to 5 V is applied to the word line during reading.

FIG. 6 is a circuit diagram of a commonly used voltage supply circuit. In FIG. 6, 100 is an oscillator (clock generation circuit), 20 is a buffer, 30 is a booster circuit,
40 is a comparison circuit, 60 is a reference voltage generation circuit, and R _L1 and R _L2
Is a resistance element, ND ₀ is a voltage dividing node, and T _OUT is a booster circuit 3.
0 output terminals are shown.

As shown, a clock signal CLK is generated by an oscillator 100, shaped by a buffer 20, and then input to a booster circuit 30. A high voltage V _OUT is generated by the booster circuit 30 using the clock signal CLK input from the buffer 20, and is output to the output terminal T _OUT . Further, the high voltage V _OUT output to the output terminal T _OUT
Is _divided by the resistance elements R _L1 and R _L2 , a divided voltage V _T is generated at the node ND ₀ , and is input to the comparator 40.

The comparator 40 is composed of, for example, a differential amplifier circuit, and is connected to one input terminal T ₁ of the differential amplifier circuit,
The voltage V _T of the node ND ₀ is applied and the other input terminal T
₂ the reference voltage V generated by the reference voltage generation circuit 60
_ref is applied. The comparator 40 compares the divided voltage V _T of the node ND ₀ with the reference voltage V _ref, and, for example,
When the voltage V _T is lower than the reference voltage V _ref , the oscillator 100
When the voltage V _T is higher than the reference voltage V _ref ,
An operation control signal CSS that stops the oscillator 100 is generated and output to the oscillator 100.

In this way, the output voltage V of the booster circuit 30
By feeding back _OUT to the oscillator 100 side, the oscillator 1
00 is controlled so that the boosted voltage V _OUT generated by the booster circuit 30 is maintained at a constant level.

[0007]

By the way, in the above-mentioned voltage supply circuit, although there is not much problem when operating with a single power supply voltage V _CC , for example, a power supply voltage of 5 V, the voltage is reduced and, for example, The power supply voltage V _CC is 2.2V to 5.V.
When supplied over a wide range of 5 V, there is a problem that the voltage supply becomes unstable.

For example, generated by oscillator 100
The frequency of the clock signal CLK is the power supply voltage V_CCDepends on
At low voltage, the frequency of clock signal CLK is low, and at high voltage
The frequency of the clock signal CLK becomes high. Also,
Even if the frequency of the clock signal CLK is held constant, the booster circuit
Since the boosting capability of 30 is higher at high voltage, the power supply voltage V _CC
The voltage supply capability of the voltage supply circuit changes in accordance with.

In order to reduce the area of the booster circuit, it is preferable to increase the frequency of the clock signal CLK.
To drive a large load at low voltage with a high-frequency clock signal, a corresponding large buffer circuit is required,
As the size of the buffer circuit increases, the capacity of the circuit itself,
The through current also increases accordingly, and the power supply voltage V _CC
In high places, that much power is wasted.

[0010] To improve this, a constant to the power supply voltage V _CC, or lowering the frequency of the power supply voltage V _CC rises when the clock signal CLK as opposed to the change in the power supply voltage V _CC, decreases the power supply voltage V _CC However, a voltage supply circuit for increasing the frequency of the clock signal CLK has been proposed, but when the frequency decreases, the ripple component (vertical fluctuation) of the output voltage V _OUT of the booster circuit becomes large, which is not preferable.

FIG. 7 shows a clock signal CL during operation of the booster circuit.
It is a wave form diagram which shows the waveform of K and output voltage V _OUT . In FIG. 7, a is the clock signal CLK at a high level, b is
Is a period during which the clock signal CLK is at a low level. As shown in the figure, during the period a in which the clock signal CLK is held at the high level, the charge is transferred toward the output terminal T _OUT side in the booster circuit, and the output voltage V _OUT rises,
During the period b during which the clock signal CLK is held at the low level, the charge is not transferred and the output voltage V _{OUT is changed} by the load current flowing from the output terminal T _OUT toward the load side.
Descends.

As described above, since the clock signals CLK are held at the high level and the low level, the level of the output voltage V _OUT of the booster circuit fluctuates up and down accordingly. When the frequency of the clock signal CLK decreases, the ripple component of the output voltage V _OUT increases. For example, the current capacity of the boosted voltage supplied to the word line of the flash EEPROM is required to be large, and for example, the ability to continuously supply the current of about 2 mA or more and the quick recovery ability with small ripple are required. . On the other hand, in the booster circuit, when the high level of the driving clock signal CLK becomes 3 V or less, the frequency dependence of the power supply voltage increases due to the threshold voltage V _{th of the} transistor and the source / drain current I _ds .

The present invention has been made in view of the above circumstances, and an object thereof is to cope with a power supply voltage used over a wide range, and particularly when operating at a low power supply voltage, it is possible to improve the current supply capability and to improve the clock. An object of the present invention is to provide a voltage supply circuit that can keep the frequency constant with respect to the power supply voltage and can suppress the ripple of the output voltage.

[0014]

In order to achieve the above object, the present invention provides a clock generation circuit which receives an operating voltage supplied through a power supply terminal and generates a clock signal,
In accordance with the clock signal generated by the clock generation circuit, a voltage of a level different from the power supply voltage is generated, and the booster circuit that outputs from the output terminal and the output voltage of the booster circuit are compared with the reference voltage, and the comparison result is obtained. Accordingly, a voltage control means for controlling the switching of the operation / stop state of the clock generation circuit is provided, and the power supply terminal of the clock generation circuit is connected to the output terminal of the booster circuit.

According to the present invention, the voltage generated by the voltage supply circuit is supplied as the operating voltage of the clock generation circuit. For example, in accordance with a clock signal generated by the clock generation circuit, a voltage having a level different from the power supply voltage is generated by the booster circuit and output to the output terminal of the booster circuit, and the output voltage of the booster circuit is compared with the reference voltage level. In the voltage supply circuit including the voltage control means for switching the operation / stop state of the clock generation circuit according to the comparison result, the output terminal of the booster circuit is connected to the power supply terminal of the clock generation circuit, Receives the boosted voltage as an operating voltage.

As a result, when operating with a power supply voltage supplied over a wide range, the current supply capability can be improved on the low voltage side and the power consumption can be reduced on the high voltage side. Further, the frequency of the clock signal generated by the clock generation circuit does not depend on the fluctuation of the external power supply voltage and can be constantly kept constant, the ripple of the output voltage can be suppressed, and the stable boosted voltage can be supplied.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a voltage supply circuit according to the present invention. In FIG. 1, 10 is an oscillator, 20
Is a buffer, 30 is a booster circuit, 40 is a comparison circuit, 50 is a level shift circuit, 60 is a reference voltage generation circuit, and R _L1 , R
_L2 is a resistance element, ND ₀ is a voltage dividing node, and T _OUT is an output terminal of the booster circuit 30, respectively.

As shown in the figure, the output terminal of the oscillator 10 is connected to the input terminal of the booster circuit via the buffer 20, and the output terminal T _OUT of the booster circuit is connected in series.
_It is connected to the ground line 2 via _L1 and R _L2, and the voltage dividing node ND ₀ is constituted by the connection point of the resistance elements R _L1 and R _L2 . The node ND ₀ is connected to the comparator 40 input terminal T ₁ , and the comparator 40 input terminal T ₂ is connected to the reference voltage generating circuit 6.
0 output terminal. The output terminal of the comparator 40 is connected to the oscillator 10 via the level shift circuit 50. In the present embodiment, the booster circuit 30 is used as the operating voltage of the oscillator 10 and the level shift circuit 50.
The boosted voltage V _OUT is supplied.

The oscillator 10 receives the boosted voltage V _OUT as an operating voltage, and controls the operating / stopped state according to the level of the operation control signal CSS from the level shift circuit 50.
For example, when the high level operation control signal CSS is received from the level shift circuit 50, the oscillator 10 operates to generate the clock signal CLK and output it to the buffer 20. On the other hand, when the low level operation control signal CSS is received from the level shift circuit 50, the oscillator 10 outputs the clock signal CL.
Stop the generation of K.

FIG. 2 is a circuit diagram showing a concrete configuration example of the oscillator 10 of the voltage supply circuit according to the first embodiment. In FIG. 2, NT ₀ is an nMOS transistor, terminal T _S is the operation control signal CS from the level shift circuit 50.
S input terminal, NGT ₁ is a NAND gate, R ₁ ,
R ₂ , R ₃ and R ₄ are resistance elements, INV ₁ , INV ₂ and I
NV ₃ , INV ₄ are inverters, C ₁ , C ₂ , C ₃ , C
Reference numeral ₄ is a capacitor, 1 is a supply line of the power supply voltage V _CC , 2 is a ground line, and T _CLK is an output terminal of the clock signal CLK. The nMOS transistor NT ₀ preferably has a threshold voltage V _th = 0V.

NAND gate NGT₁One input terminal of
Is the input of the operation control signal CSS from the level shift circuit 50.
Force terminal T_SConnected to the other input terminal of the oscillator 10
Output terminal T_CLKIt is connected to the. NAND gate NG
T₁Output terminal of the resistor element R ₁Inverter via IN
V₁Connected to the input terminal of the capacitor C₁Through
And grounded. Below, the inverter INV_FourUntil
In the same manner as above, the resistance element R, the capacitor and the inverter
Data is connected. Inverter INV_FourOutput terminal
Is the output terminal T of the oscillator 10._CLKConnected to the NA
ND gate NGT ₁Is connected to the input terminal of

Inverter INV₁, INV_Two, IN
V_Three, INV_FourPower supply terminal is node ND ₁Connected to
Node ND₁Is the output terminal T of the booster circuit 30_OUTConnected to
Have been. Furthermore, the node ND₁Is an nMOS transistor
TNT₀Connected to the source diffusion layer of the
Star NT₀Both the gate electrode and drain diffusion layer of
Power supply voltage V_CCIs connected to the supply line 1. That is,
nMOS transistor NT ₀Is a diode connection.

When the circuit rises, the output of the booster circuit 30
Force terminal T_OUTBoosted voltage V output to_OUTLevel is electric
Source voltage V_CCNMOS transistor
NT ₀Forward biased diode
In this case, due to the back gate bias effect, conduction
Sometimes about 0.5V between the drain diffusion layer and the source diffusion layer
Voltage drop occurs at node ND₁Power supply voltage V_CCThan
A voltage as low as about 0.5 V is applied to the NAND gate NG
T₁, Inverter INV₁, INV_Two, INV _Three, IN
V_FourIs the voltage (V_CCIt operates at -0.5V).

In the oscillator 10, the NAND gate N
Since the operation control signal CSS from the level shift circuit 50 is input to one input terminal of GT _{1 and} the other input terminal is connected to the output terminal of the inverter INV ₄ , the level shift circuit 50 outputs a high level signal, for example, When the operation control signal CSS at the power supply voltage V _CC level is input, the ring oscillator is configured, and the output terminal T _CLK of the oscillator 10 mutually takes the power supply voltage V _CC level and the ground potential GND level at a constant cycle. The clock signal CLK is output. The clock signal CLK from the oscillator 10 is supplied to the booster circuit 30 via the buffer 20, the booster circuit 30 operates in response to this, and the boosted voltage V _OU is output to the output terminal T _OUT.
T is output.

Here, during the rising transition period, for example, at time t ₀ , the output terminal T of the booster circuit 30.
Level power supply voltage V of the boosted voltage V _OUT which is output to _OUT
Suppose that the _CC level is exceeded. Thus, from time t ₀ to n
The diode formed by the MOS transistor NT ₀ is reverse biased. The nMOS transistor NT ₀ is
Since the threshold voltage V _th = 0 V and there is a concern about leakage current, the power supply voltage V _CC is applied as the back gate bias, so the level of the boosted voltage V _OUT is equal to or higher than the power supply voltage V _CC level. In this case, no leakage current flows from node ND ₁ to supply line 1 of power supply voltage V _CC .

Therefore, from time t ₀ , the NAND gate N
GT ₁ , inverters INV ₁ , INV ₂ , INV ₃ , I
NV ₄ operates at boosted voltage V _OUT , and NAND gate NG
When a high level operation control signal CSS of, for example, the boosted voltage V _OUT level is input to T _{1 from} the level shift circuit 50, the oscillator 10 operates and the output terminal T _{CLK is} output.
Boosted voltage V _OUT level and ground potential GND in a constant cycle
A clock signal CLK having different levels is output.

As described above, the oscillator 10 operates at the power supply voltage V _CC at the time of rising, and the boosted voltage V _CC at the time of normal operation.
_Works on _OUT . The level of the output voltage V _OUT of the booster circuit 30 is the reference voltage V generated by the reference voltage generation circuit 60.
Since it is controlled by _ref, the level of the boosted voltage V _OUT generated during normal operation is kept constant. As a result,
The frequency of the clock signal CLK generated by the oscillator 10 is kept constant.

The buffer 20 shapes the clock signal CLK from the oscillator 10 and outputs it to the booster circuit 30. The booster circuit 30 is, for example, a charge pump type booster circuit including a capacitive element as a charge pump, performs a boosting operation according to the clock signal CLK from the buffer 20, and boosts the voltage V _CC above the power supply voltage V _CC level. _OUT is generated and output to the output terminal T _OUT .

Boosted voltage V generated by booster circuit 30
_OUT is _divided by the resistance elements R _L1 and R _L2 , and the voltage V _T is generated at the voltage dividing node ND ₀ . It is input to the input terminal T ₁ of the comparator 40. The reference voltage V _ref generated by the reference voltage generation circuit 60 is input to the input terminal T ₂ of the comparator 40.

The comparator 40 has an input terminal T₁Entered in
ND₀Voltage V_TAnd input terminal T _TwoCriteria entered in
Voltage V_refAnd the operation control signal according to the comparison result.
CSS₀Is generated and output to the level shift circuit 50.

For example, if the level of the voltage V _T is the reference voltage V _T
If it is higher than the _ref level, the comparator 40 is low level,
For example, the operation control signal CSS at the ground potential GND level
_{If a 0} is generated and the level of the voltage V _T is lower than the level of the reference voltage V _ref , then the comparator 40 is at a high level, eg,
An operation control signal CSS ₀ of power supply voltage V _CC level is generated.

The level shift circuit 50 receives the operation control signal CSS ₀ from the comparator 40, level-converts it, and outputs it to the oscillator 10. For example, when the operation control signal CSS ₀ of the power supply voltage V _CC level is received from the comparator 40,
The level shift circuit 50 generates the operation control signal CSS of the boosted voltage V _OUT level and outputs it to the oscillator 10.

The operation of the above voltage supply circuit will be described below. A clock signal CLK is generated by the oscillator 10 and input to the booster circuit 30 via the buffer 20. The booster circuit 30 generates a boosted voltage V _OUT according to the clock signal CLK and outputs it to the output terminal T _OUT .

Boosted voltage V output to output terminal T _OUT
OUT is _divided by the resistance elements R _L1 and R _L2 , and the node ND
_The divided voltage V _T is generated at ₀ , the comparator 40 compares it with the reference voltage V _ref generated by the reference voltage generation circuit 60, the operation control signal CSS ₀ is generated according to the comparison result, and the level shift circuit is generated. The level is converted by 50 and output to the oscillator 10 as the operation control signal CSS.

For example, when the boosted voltage V _OUT generated by the booster circuit 30 rises, the divided voltage V _T of the node ND ₀ rises, and when it rises higher than the reference voltage V _ref , the comparator 40 makes a low level. , For example, the operation control signal CSS ₀ at the ground potential GND level is generated, and the operation control signal CSS at the ground potential GND level is generated through the level shift circuit 50 and output to the oscillator 10. In response to this, the oscillator 10 stops oscillating and stops outputting the clock signal CLK, so that the boosted voltage V output to the output terminal T _OUT in the booster circuit 30.
_OUT level decreases.

On the other hand, when the boosted voltage V _OUT generated by the booster circuit 30 drops, the divided voltage V at the node ND _{0
When T} drops and becomes lower due to the reference voltage V _ref , the comparator 40 generates an operation control signal CSS ₀ at a high level, for example, the power supply voltage V _CC level, which is level-converted by the level shift circuit 50 and boosted. The operation control signal CSS at the voltage V _OUT level is generated and output to the oscillator 10. The oscillator 10 operates in response to this,
The clock signal CLK is generated and output to the booster circuit 30 via the buffer 20. In the booster circuit 30, the boosting operation is performed according to the clock signal CLK, and the level of the boosted voltage V _OUT output to the output terminal T _OUT rises.

As described above, the boosted voltage V generated by the booster circuit 30 depends on the ratio of the resistance values of the resistance elements R _L1 and R _L2 and the level of the reference voltage V _ref generated by the reference voltage generation circuit 60. _{The OUT} level is controlled, and a stable boosted voltage V _OUT is supplied to the supply target of the voltage supply circuit. As a result, the dependency of the frequency of the clock signal CLK generated by the oscillator 10 on the power supply voltage is eliminated, and the clock signal CLK having a constant frequency during the boosting operation is always provided.
Are supplied to the booster circuit 30.

In the first embodiment, in order to convert the level of the operation control signal CSS ₀ generated by the comparator 40 into the operating voltage level of the oscillator 10, the voltage between the comparator 40 and the oscillator 10 is boosted. A level shift circuit 50 that operates with the voltage V _OUT is provided, and the high level of the operation control signal CSS ₀ is converted into the operation voltage of the oscillator 10 and input to the oscillator 10 as the operation control signal CSS, but the present invention is not limited to this. Alternatively, for example, a NAND gate with a level conversion function can be used as the NAND gate NGT ₁ that constitutes the oscillator 10.

As described above, according to this embodiment, the clock signal CLK is generated by the oscillator 10 that operates at the power supply voltage V _CC at the time of rising and operates at the boost voltage V _OUT at the time of normal operation, and the clock signal CLK is supplied to the boost circuit 30. The boosted voltage V _OUT of the booster circuit 30 is supplied and _divided by the resistance elements R _L1 and R _L2 , and the comparator 40 divides the divided voltage V _T and the reference voltage generation circuit 60.
Compares the reference voltage V _ref generated by, generates an operation control signal CSS comparison result, so to retain the level of the boosted voltage V _OUT at a constant by controlling the operation of the oscillator 10, the boosted voltage V _OUT well it is a dependence on the power supply voltage V _CC can be solved, to hold the frequency of the clock signal CLK generated by the oscillator 10 constant with respect to the power supply voltage V _CC to be used over a wide range, suppressing the ripple of the boosted voltage V _OUT It is possible and stable and boosted voltage V
_OUT can be supplied.

[0040]Second embodiment FIG. 3 shows a second embodiment of the voltage supply circuit according to the present invention.
It is a circuit diagram shown. In the voltage supply circuit shown in FIG.
It is composed of an oscillator 10a, a buffer 20 and a booster circuit 30.
Boosted voltage generating portion and resistance element R_L1, R_L2, Comparison
40, level shift circuit 50, reference voltage generation circuit 60
The circuit configuration of the boost voltage level control part
The configuration is similar to that of the voltage supply circuit shown in FIG.
In the embodiment, the oscillator 10b and the power-on detection circuit
A path 70 and a switching circuit 80 are added.
The oscillator 10a is the oscillator 10 shown in FIGS.
Unlike the boosted voltage V _OUTOperating as an operating voltage
Pressure voltage V_OUTClock signal C whose level is high level
LK₁Is generated and output to the switching circuit 80.

The oscillator 10b has a power supply voltage V_CCWorks with
Source voltage V_CCClock signal CL whose level is high level
K_TwoAnd the clock signal generated by the oscillator 10a.
No.CLK₁It is also output to the switching circuit 80.
The switching circuit 80 is from the power-on detection circuit 70.
Select the clock signal according to the power-on signal PON
Output the selected clock signal CLK to the buffer 20.
I do. For example, the power-on detection circuit 70
Oscillator when receiving bell power-on signal PON
Clock signal CLK generated by 10b _TwoAnd select
Low-level power-on by the power-on detection circuit 70
Generated by oscillator 10a when receiving signal PON
Clock signal CLK₁Select and display in buffer 20
Power.

The power-on detection circuit 70 is high during the power supply voltage V _CC duration T _P from the time of introduction of, for example, the power-on signal PO which is held at the power supply voltage V _CC level
N is output, and the switching circuit 80 and the oscillator 10b are output.
Are output respectively.

FIG. 4 is a circuit diagram showing an example of the configuration of the switching circuit 80. As shown in FIG. 4, the switching circuit 80 includes transfer gates TG ₁ and TG ₂ and an inverter I.
It is composed of NV ₅ .

Clock signal CLK from oscillator 10a₁
Input terminal T_CLK1Is the transfer gate TG ₁Through the switch
Output terminal T of the ching circuit 80_CLKConnected to the oscillator 1
Clock signal CLK from 0b_TwoInput terminal T_CLK2Turn
Sending gate TG_TwoOutput of the switching circuit 80 via
Terminal T_CLKIt is connected to the. Transfer gate TG₁Configure
PMOS transistor and transfer gate TG_TwoBe composed
Power on the gate electrode of the nMOS transistor
Terminal T of power-on signal PON from detection circuit 70_PON
Connected to the transfer gate TG₁NMOS transistor
Transistor and transfer gate TG_TwoPMOS transistor
The gate electrode of the transistor is the inverter INV_FiveOutput end of
Connected to the child, inverter INV_FiveInput terminal is power
ON signal PON terminal T_PONIt is connected to the.

Therefore, when the power-on detection circuit 70 inputs the power-on signal PON of high level, for example, the level of the power supply voltage V _CC , the transfer gate TG ₂ becomes conductive and the transfer gate TG ₁ becomes non-conductive. The held clock signal CLK ₂ from the oscillator 10b is selected and output to the output terminal T _CLK of the switching circuit 80, and the power-on detection circuit 70 inputs the power-on signal PON of low level, for example, the ground potential GND level. At this time, the transfer gate TG ₁ is held in the conductive state and the transfer gate TG ₂ is held in the non-conductive state, and the clock signal CLK ₁ from the oscillator 10 a is selected and output to the output terminal T _CLK of the switching circuit 80.

FIG. 5 is a circuit diagram showing a configuration example of the power-on detection circuit 70. As shown in FIG. 5, the power-on detection circuit 70 includes an nMOS transistor NT ₁ and a resistance element R.
_P , capacitor C _P , inverter INV _P1 , INV _P2 ,
It is composed of INV _P3 .

NMOS transistor NT₁Gate electrode
And the drain diffusion layer is the power supply voltage V _CCConnect to supply line 1 of
And the source diffusion layer is the node ND_PIt is connected to the.
That is, the nMOS transistor NT₁Is diode connected
Continuing, node ND _PIs the power supply voltage V_CCLower
When the diode is forward biased, it becomes conductive.
And the power supply voltage V_CCIs the node ND_PApplied to the node
ND_PThe level of (V_CC-V_th1) When it comes to
Switch becomes non-conductive. Here, V_th1Is nMO
S transistor NT₁Threshold voltage.

Inverters INV _P1 , INV _P2 , I are provided between the node ND _P and the terminal T _PON of the power-on signal PON.
NV _P3 is connected in series. Therefore, the node ND
_When the voltage of _P is less than or equal to the threshold voltage of the inverter INV _P1 , a high level is applied to the terminal T _PON of the power-on signal PON,
For example, when the signal of the power supply voltage V _CC level is output and the voltage of the node ND _P is equal to or higher than the threshold voltage of the inverter INV _P1 , the output terminal T _PON of the power-on signal _PON is low level, for example, the ground potential GND level. Signal is output.

Power supply voltage V_CCImmediately after the
ND_PIs the ground potential GND, and the output terminal T_PON
The high-level power-on signal PON is output to. This
NMOS transistor NT₁Composed by
The diode is held conductive and the capacitor C_PIs
Source voltage V_CCCharged by the node ND _PPotential of
To rise.

For example, if the voltage of the node ND _P exceeds the threshold voltage of the inverter INV _P1 when the time T _P has passed since the power was turned on, then the output terminal T _{P is} output from the time T _P.
The power-on signal PON output to PON switches to low level.

In the voltage supply circuit according to the present embodiment having the above-described structure, the oscillator 10b starts operating when the power supply voltage V _CC is applied, and the clock signal CLK ₂ is generated and output to the switching circuit 80. Then, from power-on to time T _P , the power-on detection circuit 70 outputs the high-level power-on signal PON, and the switching circuit 80 selects the clock signal CLK ₂ from the oscillator 10 b accordingly. And output to the buffer 20. After being shaped by the buffer 20, it is supplied to the booster circuit 30 to generate the boosted voltage V _OUT ,
It is output to the output terminal T _OUT . When the boosted voltage V _OUT reaches a predetermined level, the oscillator 10a using the boosted voltage V _OUT as a power supply voltage starts operating, and the clock signal CLK ₁ is generated by the oscillator 10a and the switching circuit 80.
Is output to

Then, the time T _{P has passed} since the power supply voltage V _{CC was} turned on.
After the lapse of time, the power-on detection circuit 70 switches the power-on signal PON from the high level to the low level, and accordingly, the oscillator 10b is stopped and the output of the clock signal CLK ₂ is stopped.

Further, the clock signal CLK ₁ generated by the oscillator 10a is selected by the switching circuit 80 in accordance with the power-on signal PON and output to the buffer 20. The booster circuit 30 performs a boosting operation according to the clock signal CLK ₁ supplied via the buffer 20 to generate a boosted voltage V _OUT .

As a result, even when the power supply voltage at a low level, for example, the power supply voltage V _CC of 1 V or less, the oscillator 10b supplies the clock signal CLK ₂ and the voltage supply circuit can start up. When the predetermined boosted voltage V _{OU T} is generated by the voltage supply circuit, the power-on signal P generated by the power-on detection circuit 70
When turned on, the operation of the oscillator 10b is stopped, the clock signal CLK ₁ generated by the oscillator 10a operating at the boosted voltage V _OUT is switched, and the boosting operation is continuously performed.

Further, the oscillator 10a and the oscillator 10b are
Both are resistance elements R_L1, R_L2, Reference voltage generating circuit 60 and
And a boosted voltage level control section composed of a comparator 40
Controlled by the operation control signal CSS from the booster circuit 3
Boosted voltage V generated by 0_OUTIs the reference voltage generator
Reference voltage V generated by 60_refAnd the resistance element R
_L1, R_L2Held at a predetermined level depending on the ratio of the resistance values of
Therefore, the boosted voltage V _OUTWith the oscillator 10a operating at
Generated clock signal CLK₁Frequency is kept constant
Stable boosted voltage V that is held by the voltage supply circuit_OUTBut
Supplied.

In the second embodiment, the power-on detection circuit 70 that generates the power-on signal PON is
As shown in FIG. 5, the capacitor C _{P is connected} to the inverter INV.
The time width T _P of the power-on signal PON is controlled by using the delay time for charging up to the threshold voltage of _P1 , but the invention is not limited to this, and it may be configured by another delay circuit. .

As described above, according to this embodiment, the oscillator 10b operating at the power supply voltage V _CC and the boosted voltage V _CC
The oscillator 10a that operates at _OUT is provided, and the clock signals generated by these oscillators are selected by the switching circuit 80 and supplied to the booster circuit 30. When the power supply voltage V _{CC is} turned on, the power on detection circuit 70 turns on the power. Signal PO
The clock signal CLK ₂ generated by the oscillator 10b is selected according to N, and is supplied to the booster circuit 30 to supply the power supply voltage V
_The clock signal CLK ₁ generated by the oscillator 10a is selected and supplied to the booster circuit 30 after the time T _P has elapsed from the time of _{turning on CC,} so that the clock signal CLK ₂ is supplied by the oscillator 10b even during low voltage operation. The voltage supply circuit rises, and the clock signal CLK ₁ whose frequency is kept constant by the oscillator 10a is supplied to the booster circuit 30 during normal operation. As a result, the power supply voltage used in a wide range can be accommodated, the boosted voltage rises quickly during low voltage operation, the current supply capability can be improved, the dependency of the clock signal CLK on the power supply voltage can be eliminated, and a stable boosted voltage V can be obtained. _OUT can be supplied.

[0058]

As described above, according to the voltage supply circuit of the present invention, the power supply voltage used in a wide range can be coped with, the power supply capability at the time of low voltage operation can be improved, and the power consumption at the time of high voltage operation can be improved. Can be reduced. Furthermore, there are advantages that the dependency of the clock signal frequency supplied to the booster circuit on the power supply voltage can be eliminated, the ripple of the output voltage can be suppressed, and a stable boosted voltage can be supplied.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a voltage supply circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of an oscillator according to the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of a voltage supply circuit according to the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a switching circuit according to a second embodiment.

FIG. 5 is a circuit diagram showing a configuration example of a power-on detection circuit according to a second embodiment.

FIG. 6 is a circuit diagram showing a configuration of a conventional voltage supply circuit.

FIG. 7 is a waveform diagram of a clock signal and an output voltage in a conventional voltage supply circuit.

[Explanation of symbols]

10, 10a, 10b ... Oscillator, 20 ... Buffer, 30
... booster circuit, 40 ... comparison circuit, 50 ... level shift circuit, 60 ... reference voltage generation circuit, 70 ... power-on detection circuit, 80 ... switching circuit, _RL1 , _RL2 ... resistance element,
ND ₀ ... voltage division node, T _OUT ... output terminal of booster circuit 30, V _CC ... power supply voltage, GND ... ground potential

Claims (3)

[Claims] 1. A clock generation circuit that receives an operating voltage supplied through a power supply terminal and generates a clock signal, and a voltage of a level different from the power supply voltage according to the clock signal generated by the clock generation circuit. And a voltage control means for comparing the output voltage of the booster circuit with a reference voltage and controlling the switching of the operation / stop state of the clock generator circuit according to the comparison result. A voltage supply circuit comprising a power supply terminal of the clock generation circuit connected to an output terminal of the booster circuit. 2. The voltage supply circuit according to claim 1, wherein a power supply terminal of the clock generation circuit is connected to an external power supply through a rectifying element provided so as to be in a forward direction toward the power supply terminal. 3. A second clock generating circuit that operates with an external power supply voltage, and a clock signal generated by the second clock generating circuit at the time of rising is input to the boosting circuit and generated by the clock generating circuit during normal operation. 2. The voltage supply circuit according to claim 1, further comprising clock switching means for inputting the generated clock signal to the booster circuit.