JPH09305433A - Microprogram verification device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mioproprogram verification device which can easily confirm whether or not each step of a developed microprogram is executed. SOLUTION: This device is provided with a detection and recording part 14 which inputs a microprogram address cma when a microprogram is read out and the significance signal upop of the read microprogram from a central processor and records data on the execution states of respective steps of the microprogram in recording memories 9 and 10 according to inputted information. Then the microprogram on the central processor is verified according to the data recorded in the recording memories 9 and 10 and previously generated normal data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a micro program verification device for verifying a central processing unit of a micro program control system.

[0002]

2. Description of the Related Art Conventionally, in a central processing unit of a micro program control system, in order to confirm whether or not all of the installed micro programs are executed, various test data are actually used to execute micro programs. Was executed, the micro program address was collected by a logic analyzer or the like, and the result was compared with the flow chart of the micro program and confirmed.

[0003]

However, conventionally, it has been necessary to manually collect a microprogram address, which is an execution result of test data and the like, and associate the result with a flow chart of the microprogram. When the number of microprogram steps is hundreds to thousands, many people and time are required, and there is a problem that human error occurs.

[0004]

A microprogram verifying apparatus according to the present invention is a microprogram verifying apparatus for verifying a microprogram in a central processing unit of a microprogram control system, when reading the microprogram from the central processing unit. The microprogram address and the valid signal of the read microprogram are input, and detection data is recorded in the recording memory for recording the execution state data in each step of the microprogram in the recording memory based on the input information. The microprogram in the central processing unit is verified based on the generated data and the normal data generated in advance.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. FIG. 1 is a circuit diagram showing a configuration of a detection recording unit and a recording RAM of a micro program verification device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a configuration of the micro program verification device of this embodiment. .

In FIG. 1, cma is a microprogram address read by a central processing unit (hereinafter referred to as CPU) to be verified from a control memory (hereinafter referred to as CM) (not shown) in which a microprogram is stored. Signal, upop is a microprogram valid signal from the CPU, sequence is a signal indicating that the read microprogram execution is continuous, and jump is
Is a signal indicating that a jump has occurred during microprogram execution.

Further, 1 is a register holding a microprogram address, 2 is +1 for the output of the register 1.
An adder 3 for latching the output of the adder 2 with an upop signal holds a valid microprogram address + 1. Reference numeral 4 is a flip-flop that holds the upop signal.

Reference numeral 5 is a comparator for comparing the output of the register 1 with the output of the latch circuit 3, and whether the microprogram execution is continuous (sequence signal is asserted) or jump is performed (jupm signal is asserted). Is output). 6 is an inverter,
The coincidence detection output of the comparator 5 is inverted to generate a signal jump indicating a non-coincidence, that is, the microprogram is executing and jumping.

Reference numeral 7 denotes the output of the flip-flop 4 and seq.
An AND circuit that outputs an AND signal (seq-we signal) with the ence signal to control writing in the sequence recording RAM 9, 8 is an output of the flip-flop 4 and ju
An AN that outputs an AND signal (jump-we signal) with the mp signal and controls writing in the jump recording RAM 10
This is a D circuit.

Further, the register 1, the adder 2, the latch circuit 3, the flip-flop 4, the comparator 5, the inverter 6 and the AND circuits 7 and 8 constitute the detection recording section 14, and the sequ
The recording RAM 17 is composed of the ence recording RAM 9 and the jump recording RAM 10.

In FIG. 2, 11 is a CPU to be verified,
Reference numeral 12 denotes a micro program verification device, which includes a CPU interface unit 13, a detection recording unit 14, and an initialization control unit 1.
5, read control unit 16, recording RAM 17, and control I
/ F18. Reference numeral 19 is a terminal for controlling the micro program verification device 12, and 20 is an FD for data collection.
It is D. Further, the CPU 11 and the micro program verification device 12 are connected by a dedicated interface, and the micro program verification device 12 and the control terminal 19 are RS-.
It is connected by an interface such as 232C.

The detection / recording unit 14 is configured as shown in FIG. 1, and the detection / recording RA of microprogram execution / jump is performed via the CPU interface unit 13.
It controls the recording of results to M17. In addition, the initialization control unit 15 turns on the power or controls the interface unit 18.
The detection recording unit 14, the read control unit 16, and the recording RAM 17 are initialized by an instruction from the. The control interface unit 18 sends a control instruction and result data to each component block of the microprogram verification device 12 according to an instruction from the control terminal 19.

Next, the operation of the detection recording unit 14 of this embodiment will be described. FIG. 3 is a time chart showing the state of signals in each unit of this embodiment. In the figure, CLK indicates the basic cycle, and ... Represents outputs of the register 1, the adder 2, the latch circuit 3 and the flip-flop 4 shown in FIG. 1, respectively. Also, se
The sequence signal and the jump signal are under the condition of (A + 1 = C, C + 1 ≠ D, D + 1 = E) as shown in FIG.

First, the CPU 11 reads a microprogram in a CM (not shown). The address at that time is the cma signal, which indicates the microprogram address. If the microprogram read in the next cycle is valid, the microprogram is executed inside the CPU 11 and at the same time the upop signal is asserted. If it is invalid, the microprogram execution is made to wait inside the CPU 11 for some reason, and the upop signal is negated. This operation is the cycle of A and B of the cma signal in FIG. 3, and the two operations are repeated as the operations of the CPU 11 and CM.

Then, the condition (A + 1 = C,
C + 1 ≠ D, D + 1 = E) is executed continuously as addresses A and A + 1 (C) as the operation of the microprogram, and jumps to address D at address A + 1 (C) to obtain addresses D, D + 1 (E ) It has been executed continuously with the address (the microprogram at the address B is not executed).

In this operation, first, in the first cycle, the CPU 11 reads the microprogram at the microprogram address A from the CM and asserts the upop signal. At that time, the cma signal indicates the microprogram address A. Then, in the second cycle, the CPU 11 reads the microprogram address B, but does not execute the microprogram at address B, so the up signal is negated.

Then, in the third cycle, the CPU 11 reads the microprogram at the microprogram address C from the CM and asserts the signal upop. After that, the same operation as that of the third cycle is performed, and the microprogram address, that is, the signal cma is D, E, F,
Addresses G and H.

In the fourth cycle, address A,
Since it is executed with the address C (A + 1), and the signal indicates A + 1, the sequence signal is asserted and se
Since the q-we signal is asserted, the sequence
“1” is written in the address A + 1 of the ce recording RAM 9.

In the fifth cycle, the signal is C
Since the signal is +1 and the signal is D, from the condition C + 1 ≠ D, the jumpm signal is asserted, the seq-we signal is negated, and the jump-we signal is asserted. Therefore, at the address C + 1 (A + 2) of the jump recording RAM 10. "1" is written.

In the sixth cycle, the signal is D
Since the signal is E and the signal is E, the sequence signal is asserted from the condition D + 1 = E, and jump−
Since the we signal is negated and the seq-we signal is asserted, “1” is written in the D + 1 address of the sequence recording RAM 9.

In the seventh cycle, the signal is E
Since the signal is F and the signal is F, since the condition E + 1 = F, the sequence signal remains asserted and the signal swq-we remains asserted.
“1” is written in the address E + 1 (D + 2) of the sequence recording RAM 9.

Therefore, if the microprogram at the microprogram address A is a microprogram that does not jump, A in the sequence recording RAM 9
"1" is recorded in the +1 address, and if it is a jump micro program, "1" is recorded in the A + 1 address of the jump recording RAM 10. In this way, se
sequence recording RAM 9 and jump recording RAM 10
, The sequence (jump) / jump of the address of the microprogram execution by the CPU 11 is recorded,
The CPU 11 is verified by comparison with normal data.

Next, the operation of the microprogram verification device 12 of this embodiment will be described. First, the initialization control unit 15 receives an initialization instruction from the control terminal 19 via the control interface unit 18, and initializes each unit in the microprogram verification device 12. The initialization is also performed under other initialization conditions such as power ON.

Then, the micro program to be verified is executed in the CPU 11, and the cma signal and the up signal from the CPU 11 are supplied via the CPU interface unit 13.
The op signal is input to the detection recording unit 14, and the detection recording unit 14 outputs the micro address (continuous jump) as described above.
p) is detected and recorded in the recording RAM 17.

When all the recording is completed, the control terminal 19 issues an instruction to read the result data to the read control unit 16 via the control interface unit 18, and the result data is recorded from the recording RAM 17 via the control interface unit 18. Read out to the control terminal 19.

Here, after simply initializing each unit,
Although it has been described that the verification (recording) is performed immediately, the test program is actually created in the form of test data that can be executed by the control terminal 19, and the test program is executed to initialize the microprogram verification device 12. C, C
Execution of the verification microprogram by the PU 11, verification by the verification device 12 (microprogram address (continuous /
(jump) detection), reading of the result data, comparing the result data with the normal data created in advance, and checking the execution state of each step of the microprogram. There is. Then, depending on the result of the examination, the test data is added, the microprogram is corrected, and the like.

Now, normal data to be compared with the result data will be described. Since the microprogram stored in the CM is usually developed by another development machine or the like, it is analyzed by the development machine to generate the corresponding normal data. The normal data has a sequence flag and a jump flag for each microprogram address, and is composed of data of the capacity of the target microprogram by the following combinations.

'00': Micro program is not executed '01': Micro program with jump '10': Micro program without jump '11': Micro program with judgment jump

In this embodiment, the detection recording unit 14 detects the sequence (continuous) / jump of the address of the microprogram execution by the CPU 11, and the data is recorded in the sequence recording RAM 9 and jump.
Since it is stored in the recording RAM 10 and the CPU 11 is verified by comparing the stored data with normal data, it is possible to easily confirm whether or not each step of the microprogram is executed, and The verification can be performed easily and surely.

Embodiment 2 FIG. FIG. 4 is a block diagram showing the configuration of a microprogram verification device according to another embodiment of the present invention. In the figure, 21 is a CP to be verified
U and 22 are microprogram verification devices, CPU
The interface unit 23, the detection recording unit 14, the initialization control unit 25, and the recording RAM 17 are included. 27 is a memory (MEM), 28 is a system bus, and 29 is a system console. The microprogram of the CPU 21 has a system console processing section, and the processing section has an interface processing section of the microprogram verification device 22.

The detection recording section 14 is similar to the first embodiment,
Through the CPU interface unit 23, microprogram execution / jump detection and recording of results in the recording RAM 17 are controlled. The initialization control unit 25 initializes the detection recording unit 14 and the recording RAM 17 by turning on the power or by an instruction from the system console 29. Further, the CPU interface unit 23 gives a control instruction to each component block of the microprogram verification device 22 in accordance with an instruction from the system console 29.

Next, the operation of this embodiment will be described. The operation of the detection recording unit 14 is the same as that of the first embodiment. First, the CPU 21 receives an initialization instruction from the system console 29 via the system bus 28, and the CPU 2
The first system console processing unit receives the initialization control unit 25 via the CPU interface unit 23 of the micro program verification device 22, and initializes each unit in the micro program verification device 22. The initialization is also performed under other initialization conditions such as power ON.

Then, the micro program to be verified is executed by the CPU 21, and the cma signal from the CPU 11 and the up signal are supplied via the CPU interface section 23.
The op signal is input to the detection recording unit 14, and the detection recording unit 14 outputs the micro address (continuous jump) as described above.
p) is detected and recorded in the recording RAM 17.

When all the recording is completed, the system console 29 issues an instruction to read the result data to C.
The CPU interface unit 23 is executed via the PU 21, the result data is read from the recording RAM 17 to the CPU 21 via the CPU interface unit 23, and the CP
Write from U21 to MEM27 via system bus 28 (data A of MEM27).

Then, the result data A in the MEM 27 and the prepared normal data B are compared by using the command of the system to be verified, and the detected and recorded execution result data is compared with the normal data to make a microprogram. The operation is confirmed by checking the execution state of each step of. Then, depending on the result of the examination, the test data is added, the microprogram is corrected, and the like.

In this embodiment, the detection recording unit 14 detects the sequence (continuous) / jump of the address of the microprogram execution by the CPU 21, and the data thereof is recorded in the sequence recording RAM 9 and jump.
Since the CPU 21 is verified by storing the data in the recording RAM 10 and comparing the stored data with the normal data, it is possible to easily confirm whether or not each step of the microprogram has been executed. The verification can be performed easily and surely, and since no dedicated control terminal or the like is used, the configuration of the device can be simplified.

Embodiment 3 FIG. 5 is a block diagram showing the configuration of a microprogram verification device according to another embodiment of the present invention. In the figure, 30 is a CP to be verified
U and 31 are microprogram verification devices, which are CPUs
Interface unit 32, detection recording unit 14, initialization control unit 34, recording RAM 17, control interface unit 3
6 and a system bus interface unit 37. 38 is a control terminal, 39 is a system bus, 4
0 is a memory (MEM).

The detection recording unit 14 is similar to the first embodiment,
Through the CPU interface unit 32, microprogram execution / jump detection and recording of results in the recording RAM 17 are controlled. The initialization control section 34 initializes the detection recording section 14 and the recording RAM 17 in response to an instruction from the power source ON or the control interface section 36. Further, the control interface unit 32 receives the instruction from the control terminal 38, and the micro program verification device 3
1, and the system bus interface unit 37 transfers the result data to the MEM 40 in response to an instruction from the control terminal 38.

Next, the operation of this embodiment will be described. The operation of the detection recording unit 14 is the same as that of the first embodiment. First, the initialization control unit 34 receives an initialization instruction from the control terminal 38 via the control interface unit 36, and initializes each unit in the microprogram verification device 31. The initialization is also performed under other initialization conditions such as power ON.

Then, the CPU 30 executes the microprogram to be verified, the detection recording unit 14 detects the micro address (continuous / jump) via the CPU interface unit 32, and records it in the recording RAM 17.

When all the recording is completed, the control terminal 38 issues an instruction to read the result data through the control interface unit 36, and the result data is sent from the recording RAM 17 through the system bus interface unit 37 and the system bus 39. Write to MEM40 (MEM
40 data A).

Then, the result data A in the MEM 40 is compared with the normal data B prepared in advance by using an instruction of the system to be verified, and the detected and recorded execution result data is compared with the normal data to make a microprogram. The operation is confirmed by checking the execution state of each step of. Then, depending on the result of the examination, the test data is added, the microprogram is corrected, and the like.

In this embodiment, the detection recording unit 14 detects the sequence (continuous) / jump of the address of the microprogram execution by the CPU 30, and the data thereof is recorded in the sequence recording RAM 9 and jump.
Since the CPU 30 is verified by storing the data in the recording RAM 10 and comparing the stored data with the normal data, it is possible to easily confirm whether or not each step of the microprogram has been executed. The verification can be performed easily and surely, and the CPU 30
Since the initialization control of the microprogram verification device 31 is not performed, the verification can be executed without incorporating the control microprogram of the microprogram verification device in the system console processing unit of the microprogram of the CPU.

Fourth Embodiment FIG. 6 is a block diagram showing the configuration of a microprogram verification apparatus according to another embodiment of the present invention. In the figure, 41 is a CP to be verified
U and 42 are micro-program verification devices, and CPU
The interface unit 43, the detection recording unit 14, the initialization control unit 45, the recording RAM 17, and the system bus interface unit 47 are included. 48 is the system bus,
Reference numeral 49 is a memory (MEM), and 50 is a system console. The microprogram of the CPU 41 has a system console processing section, and this processing section has an interface processing section of the microprogram verification device 42.

The detection recording section 14 is similar to that of the first embodiment.
Through the CPU interface unit 23, microprogram execution / jump detection and recording of results in the recording RAM 17 are controlled. The initialization control unit 45 turns on the power,
Alternatively, the detection / recording unit 1 is instructed by the system console 50.
4. The recording RAM 17 is initialized. CP
The U interface section 43 gives a control instruction to each section of the microprogram verification device 42 according to an instruction from the system console 50. Further, the system bus interface unit 47 transfers the result data to the MEM 49 according to an instruction from the system console 50.

Next, the operation of this embodiment will be described. The operation of the detection recording unit 14 is the same as that of the first embodiment. First, the CPU 41 receives an initialization instruction from the system console 50 via the system bus 48, and the CPU 4
The system console processing unit 1 receives the initialization control unit 45 via the CPU interface unit 43 of the microprogram verification device 42, and initializes each unit in the microprogram verification device 42. The initialization is also performed under other initialization conditions such as power ON.

Then, the micro program to be verified is executed in the CPU 41, and the cma signal and the up signal from the CPU 11 are supplied via the CPU interface section 23.
The op signal is input to the detection recording unit 14, and the detection recording unit 14 outputs the micro address (continuous jump) as described above.
p) is detected and recorded in the recording RAM 17.

When all the recording is completed, the system console 50 issues an instruction to read the result data to C.
The CPU interface unit 43 is executed via the PU 41, and the result data is transferred from the recording RAM 17 via the system bus interface unit 47 via the system bus 48 to the M
Write to EM49 (MEM49 data A).

Then, the result data A in the MEM 27 is compared with the normal data B prepared in advance by using an instruction of the system to be verified, and the detected and recorded execution result data is compared with the normal data to perform a microprogram. The operation is confirmed by checking the execution state of each step of. Then, depending on the result of the examination, the test data is added, the microprogram is corrected, and the like.

In this embodiment, the detection recording unit 14 detects the sequence (continuous) / jump of the address of the microprogram execution by the CPU 41, and the data is recorded in the sequence recording RAM 9 and jump.
Since the CPU 41 is verified by storing the data in the recording RAM 10 and comparing the stored data with the normal data, it is possible to easily confirm whether or not each step of the microprogram is executed. The verification can be performed easily and surely, and the data in the recording RAM 17 can be recorded in the MEM4 by the system console 50.
Since the result data is transferred to 0, the CPU does not transfer the result data, so that it can be executed at a higher speed.

Incidentally, in the above-mentioned embodiments, the first and second embodiments are embodiments in the case where the microprogram verifying device cannot be connected to the system bus.
4 is an embodiment in the case where a microprogram verification device can be connected to the system bus. In addition, the first embodiment
3 is an embodiment in which the control microprogram of the verification device cannot be incorporated in the system console processing unit of the microprogram of the CPU, and Embodiments 2 and 4 are embodiments in which it can be incorporated.

The verification execution speed is in the order of Embodiment 1, Embodiment 3, Embodiment 2, and Embodiment 4 (depending on the data transfer speed), and there is a trade-off between the amount of hardware and the control microprogram. The form to be implemented will be selected.

Further, in the first to fourth embodiments, the example of the microprogram verification of the CPU has been described, but other devices have the same function as the device to be verified (first to first embodiments).
In the case of No. 4, if it can be provided to the CPU), it can be applied to the verification of the firmware.

[0054]

As described above, according to the present invention, the central processing unit inputs the microprogram address at the time of reading the microprogram and the detection recording means for inputting the valid signal of the read microprogram. Based on the information, the execution state data in each step of the microprogram is recorded in the recording memory, and the microprogram in the central processing unit is verified based on the data recorded in the recording memory and the previously generated normal data. As a result, it is possible to easily confirm whether or not each step of the microprogram is executed, and it is possible to easily and surely verify the central processing unit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a detection recording unit and a recording RAM of a micro program verification device.

FIG. 2 is a block diagram showing a configuration of a micro program verification device according to the first embodiment.

FIG. 3 is a time chart showing a signal state in each unit of the first embodiment.

FIG. 4 is a block diagram showing a configuration of a micro program verification device according to a second embodiment.

FIG. 5 is a block diagram showing a configuration of a micro program verification device according to a third embodiment.

FIG. 6 is a block diagram showing a configuration of a micro program verification device according to a fourth embodiment.

[Explanation of symbols]

 11 Central Processing Unit (CPU) 12 Micro Program Verification Device 13 CPU Interface Section 14 Detection Recording Section 15 Initialization Control Section 16 Read Control Section 17 Recording RAM 18 Control Interface Section 19 Control Terminal 20 Data Collection FDD

Claims (5)

[Claims] 1. A microprogram verification device for verifying a microprogram in a microprogram control type central processing unit, comprising: a microprogram address for reading the microprogram from the central processing unit; and a valid signal of the read microprogram. Is provided, and based on the inputted information, a detection recording unit for recording the execution state data in each step of the microprogram in a recording memory, based on the data recorded in the recording memory and the normal data generated in advance A microprogram verification device characterized by verifying a microprogram in a central processing unit. 2. A microprogram verification device for verifying a microprogram in a microprogram control type central processing unit, comprising: a microprogram address for reading the microprogram from the central processing unit; and a valid signal of the read microprogram. Is input, based on the input information, the detection recording means for recording the data of the execution state in each step of the microprogram in the recording memory, and a control terminal for performing the control operation of the microprogram verification, the control terminal of By operation, the data of the execution state in each step of the microprogram is recorded in the recording memory, the data recorded in the recording memory is recorded in the recording medium, and the data recorded in the recording medium and the previously generated normal data are recorded. Central based A microprogram verifying device for verifying a microprogram in a processing device. 3. A microprogram verification device for verifying a microprogram in a central processing unit of a microprogram control system, comprising: a microprogram address for reading a microprogram from the central processing unit; and a valid signal of the read microprogram. Is input, and based on the input information, a detection recording unit for recording the execution state data in each step of the microprogram in a recording memory, and operation of a system console connected to the central processing unit via a system bus Records the execution state data in each step of the microprogram in the recording memory, records the data recorded in the recording memory into the memory connected to the system bus via the central processing unit, and stores the data in the memory. Recorded Microprogram verification apparatus and performs verification of the microprogram in the central processing unit based on the data and the previously generated normal data. 4. A microprogram verification device for verifying a microprogram in a microprogram control type central processing unit, comprising: a microprogram address for reading the microprogram from the central processing unit; and a valid signal of the read microprogram. Is input, based on the input information, the detection recording means for recording the data of the execution state in each step of the microprogram in the recording memory, and a control terminal for performing the control operation of the microprogram verification, the control terminal of By operation, data of the execution state in each step of the microprogram is recorded in the recording memory, the data recorded in the recording memory is recorded in the memory connected through the dedicated interface, and the data recorded in the memory and Foresight A microprogram verifying device for verifying a microprogram in a central processing unit based on normal data generated for the purpose. 5. A microprogram verifying device for verifying a microprogram in a central processing unit of a microprogram control system, comprising: a microprogram address for reading the microprogram from the central processing unit; and a valid signal of the read microprogram. Is input, and based on the input information, a detection recording unit for recording the execution state data in each step of the microprogram in a recording memory, and operation of a system console connected to the central processing unit via a system bus According to this, the execution state data in each step of the microprogram is recorded in the recording memory, the data recorded in the recording memory is recorded in the memory connected to the system bus through the dedicated interface, and the memo is recorded. Microprogram verification apparatus and performs verification of the microprogram in the central processing unit on the basis of the recorded data and pre-generated normal data.