JPH09306105A - Recorded information reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain highly reliable information even from a recording medium having a residual low frequency component by removing an offset component in a low frequency band from a read signal. SOLUTION: A cut-off frequency of an HPF 14 is set to the side of a low band, so that a DC component is mainly removed from the read signal, and the filtered read signal (a) is supplied to a subtractor 15. A correction read signal (h) obtained by subtracting an error voltage (e) from the signal (a) is supplied by the subtractor 15 to an A/D converter 16. The signal (h) is sampled and converted into a correction read sample group (b) by the converter 16 in accordance with a sampling clock signal supplied from a PLL circuit 17. A clock signal phase-synchronized with the group (b) is generated by the circuit 17, and is supplied to the converter 16. A sample value obtained at the time of inverting polarity of an interpolation value (g) of the group (b) is extracted from the group (b) by a sample extracting circuit 19, and is supplied via a D/A converter 20 and an LPF 21 to the subtractor 15 as the error voltage (e). The most probable binary reproducing data is decoded and outputted by a viterbi decoder 18 based on the group (b).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recorded information reproducing apparatus for reproducing information information from a recording medium on which information data is recorded.

[0002]

2. Description of the Related Art Information data is EFM (eight to fourtee).
A CD (compact disc) is known as a recording medium that is encoded and recorded. Such EF
In M, 14 words of information data are
It is converted into a bit code and a 3-bit code called a merging bit is added to this to obtain an EFM signal. At this time, a bit pattern that reduces the low-frequency component of the code string after conversion is selected as the merging bit.

An EFM signal composed of a code string in which low frequency components are suppressed for each word is recorded on a CD. FIG. 1 is a diagram showing the configuration of a recorded information reproducing apparatus for reproducing recorded information from such a CD. In FIG. 1, the pickup 1 irradiates a CD 2 as a recording medium with a laser beam and photoelectrically converts the reflected light to supply it to the RF amplifier 3 as a read signal. RF amplifier 3
Supplies a signal obtained by amplifying the signal level of the read signal to an HPF (high pass filter) 4. HPF4
In order to remove the disturbance component in the low frequency band from the amplified read signal, only passes the high frequency component in the amplified read signal and supplies it to the comparator 5. The comparator 5 outputs the read signal that has passed through the HPF 4,
Convert to a binary pulse with a predetermined threshold. PLL (phase lo
The cked loop) circuit 7 generates a clock signal of a predetermined frequency that is phase-synchronized with the binary pulse. The sampling circuit 6 has a timing corresponding to the clock signal,
The binary pulse is taken in and output as binary reproduction data.

In such a recorded information reproducing apparatus, a CD
The HPF 4 is provided so as to remove the disturbance component in the low frequency band which is superposed on the read signal due to the characteristic variation of No. 2 or the influence of the servo error of the reproducing apparatus. At this time, as described above, since the EFM signal has few low frequency components, the HPF 4 does not lose the original information.

In recent years, a DVD (digital video disc) has been used as a recording medium for high density recording of information data such as digital audio, digital video and computer data.
Has been attracting attention. In such a DVD, instead of recording information data by EFM encoding like a CD, 8 /
16 modulation coded and recorded. However, in 8/16 modulation encoding, low frequency components are stochastically suppressed according to the permutation of code strings, instead of suppressing low frequency components word by word as in EFM encoding. However, a large amount of low frequency components may remain. Therefore, when the recorded information is reproduced from the DVD by the recorded information reproducing apparatus having the structure as shown in FIG. 1, there is a possibility that the HPF 4 may partially lose the information data. On the other hand, if the HPF 4 is removed, the disturbance component in the low frequency band as described above cannot be removed, and the error rate of the binary reproduction data will increase.

Further, since a DVD records information data at a higher density than a CD, it becomes more susceptible to characteristic variations of the disc itself and errors of various servos on the reproducing device side when reading the information, and thus, it is a binary value. The error rate of the reproduced data is high.

[0007]

Therefore, in the present invention, highly reliable information reproduction is performed even from a recording medium in which a recording signal is recorded in a digital signal format that may include a low frequency band component. It is an object of the present invention to provide a recorded information reproducing device that can be used.

[0008]

A recorded information reproducing apparatus according to the present invention is a recorded information reproducing apparatus for reproducing recorded information recorded on a recording medium, and the recorded information is read from the recording medium and analogized. Information reading means for obtaining a read signal, a subtractor for subtracting an error voltage from the read signal to obtain a corrected read signal, and an A / A for sampling the corrected read signal and converting it into a digital corrected read sample series.
A D converter, a decoding means for decoding the recorded information from the corrected read sample series, and only a sample existing at a position closest to the zero-cross time point in the corrected read sample series is extracted from the corrected read sample series. It has a sample extracting means for obtaining an extracted sample series, and an error voltage generating means for generating, as the error voltage, a signal obtained by converting each sample in the extracted sample series into an analog signal of a level corresponding to the sample value.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a diagram showing the configuration of the recorded information reproducing apparatus according to the present invention. In FIG. 2, a recording disk 12 such as a DVD set in this recording information reproducing apparatus has information data such as digital audio, digital video, and computer data recorded at high density. The pickup 11 supplies an analog read signal obtained by reading the recorded information from the recording disk 12 to the RF amplifier 13. The RF amplifier 13 amplifies the read signal as desired, and the HPF 14
To supply. The HPF 14 has a cutoff frequency set to a lower frequency side than the HPF 4 shown in FIG. 1, and is obtained by mainly removing a DC component from the read signal amplified by the RF amplifier 13. The read signal a is supplied to the subtractor 15.

The subtractor 15 supplies a corrected read signal h obtained by subtracting an error voltage e described later from the read signal a to the A / D converter 16. The A / D converter 16 samples the correction read signal h in accordance with a sampling clock signal supplied from a PLL (phase locked loop) circuit 17 described later and converts it into a digital correction read sample sequence b. The PLL circuit 17 generates a clock signal that is phase-synchronized with the corrected read sample sequence b and uses this as the sampling clock signal for A / A.
It is supplied to the D converter 16. The Viterbi decoder 18 decodes the most likely binary reproduction data based on the corrected read sample series b and outputs it.

The sample extracting circuit 19 sequentially extracts only the sample value existing at the position closest to the zero-cross point from the corrected read sample series b, and supplies this to the D / A converter 20 as the extracted sample series c. To do. FIG.
FIG. 3 is a diagram showing an example of an internal configuration of the sample extracting circuit 19. Further, FIG. 4 is a diagram showing an example of each signal waveform of the sample extracting circuit 19.

In FIG. 3, a D flip-flop 191 is provided.
Takes in each sample value of the corrected read sample series b according to the sampling clock signal, and supplies this to the adder 192 and the D flip-flop 195 as a corrected read sample series p. The D flip-flop 191 and the adder 192 obtain the interpolated value q between each sample in the corrected read sample series b. In the D flip-flop 193 and the exclusive OR circuit 194, the signal logical value of the bit signal r which is the MSB (most significant bit) of the interpolation value q is “1” to “0” or “0” to “1”. The polarity inversion detection pulse signal s is generated when the transition to ". The D flip-flop 195 takes in the corrected read sample series p according to the polarity inversion detection pulse signal s and outputs it as the extracted sample series c.

That is, in the sample extracting circuit 19 shown in FIG. 3, the sample value obtained from the corrected read sample series b at the time when the polarity of the interpolation value q of the corrected read sample series b is inverted, that is, , The sample value existing at the closest position at the zero crossing point in the corrected read sample sequence b is extracted. The D / A converter 20 converts each sample value in the extracted sample sequence c into an analog signal having a level corresponding to the magnitude of the value, and uses this as an error signal d for LPF (low
pass filter) 21. The LPF 21 supplies a voltage obtained by smoothing the error signal d to the subtractor 15 as an error voltage e.

FIG. 5 is a diagram showing an example of internal operation waveforms (read signal a, corrected read sample series b, extracted sample series c and error signal d) in the recording information reproducing apparatus shown in FIG. Here, when the information reproduction is performed, if the offset component is superimposed due to the characteristic variation of the recording disk 12 and the error of various servos on the reproducing device side, the value of the read sample value actually obtained is the offset component of this offset component. It will be level-shifted by a minute.

For example, in the example of the waveform shown in FIG. 5, the samples b ₁ , b ₄ , b ₇ , b ₁₀ and b ₁₃ among the samples in the corrected read sample series b are originally "0". However, the level is shifted to the positive side as a whole by the amount of the offset component. Therefore, in the present invention, a read sample that should originally be "0" is extracted as an extracted sample series c from the read sample series obtained by sampling the read signal a, and this is converted into an analog signal. Is obtained as the error signal d, and the error signal d is subtracted from the read signal a to remove the offset component.

Therefore, according to the recorded information reproducing apparatus, the offset component in the low frequency band can be removed from the read signal. Therefore, highly reliable information reproduction can be performed even from a recording medium such as a DVD in which a lot of low frequency components remain in the read signal because the 8/16 modulation code is used. In the recorded information reproducing apparatus shown in FIG. 2, the sampling clock signal generated in the PLL circuit 17 and the read signal are assumed to be in synchronization with each other, and the extraction extracted by the sample extraction circuit 19 is performed. The sample sequence c is D / A converted to obtain the error signal d. However, for example, immediately after performing the search operation or the jump operation, the sampling clock signal is in an unstable state, and therefore, there is a possibility of malfunction.

FIG. 6 is a diagram showing the configuration of a recorded information reproducing apparatus according to another embodiment of the present invention made in view of the above point. In the recorded information reproducing apparatus shown in FIG. 6, the sample extracting circuit 19 in the configuration shown in FIG.
And the D / A converter 20 are provided with a switch 30 and a synchronization determination circuit 31.

The synchronization determination circuit 31 determines whether or not the sampling clock signal generated in the PLL circuit 17 and the read signal are synchronized. The synchronization determination circuit 31
During the period in which it is determined that the sampling clock signal is in the synchronous state, the switching control of the switch 30 is performed so that the extracted sample series c output from the sample extracting circuit 19 is supplied to the D / A converter 20. On the other hand, during the period in which it is determined that the sampling clock signal is in the asynchronous state, the switch 30 is switched so as to supply the corrected read sample sequence b output from the A / D converter 16 to the D / A converter 20. Take control.

As described above, in the recording information reproducing apparatus shown in FIG. 6, while the sampling clock is stable, the extracted sample sequence c is D / A converted to obtain the error signal d, while sampling is performed. During a period in which the clock is unstable, the corrected read sample series b is D / A converted to obtain the error signal d. That is,
During the period when the sampling clock signal is in an unstable state, the correction read sample sequence b is less affected by the phase shift of the sampling clock than the extraction sample sequence c is used. The operation is switched to the operation of D / A converting the read sample series b to obtain the error signal d.

In the embodiment shown in FIGS. 2 and 6, the error signal d is obtained by D / A converting each sample of the extracted sample series c. The difference between the period in which the value of each sample of the sample series c is the positive value and the period in which the negative value is the negative value may be obtained as an error signal.

FIG. 7 is a diagram showing the configuration of a recorded information reproducing apparatus according to another embodiment of the present invention made in view of the above points. In FIG. 7, the pickup 11 supplies the RF amplifier 13 with an analog read signal obtained by reading the record information from the recording disk 12. The RF amplifier 13 amplifies the read signal as desired and supplies it to the HPF 14. The HPF 14 subtracts the read signal a obtained by removing the DC component from the amplified read signal by the subtracter 15
To supply.

The subtractor 15 supplies a corrected read signal h obtained by subtracting an error voltage e described later from the read signal a to the A / D converter 16. The A / D converter 16 samples the correction read signal h in accordance with a sampling clock signal supplied from a PLL (phase locked loop) circuit 17 described later and converts it into a digital correction read sample sequence b. The PLL circuit 17 generates a clock signal that is phase-synchronized with the corrected read sample sequence b and uses this as the sampling clock signal for A / A.
It is supplied to the D converter 16. The Viterbi decoder 18 decodes the most likely binary reproduction data based on the corrected read sample series b and outputs it.

The polarity detection circuit 32 detects the polarity in the corrected read sample series b only at the time when the polarity of the corrected read sample series b changes, and outputs the polarity signal f having a logical value corresponding to the detected polarity. It is supplied to the level conversion circuit 33. FIG. 8 shows the polarity detection circuit 32.
FIG. 3 is a diagram showing an internal configuration of the device. In FIG. 8, a D flip-flop 191 takes in each sample value of the corrected read sample series b according to the sampling clock signal, and uses this as a corrected read sample series p as an adder 19
Feed to 2. D flip-flop 191 and adder 1
Reference numeral 92 determines an interpolated value q between each sample in the corrected read sample series b. The D flip-flop 193 and the exclusive OR circuit 194 determine the MSB of the interpolation value q.
(Most significant bit) The signal logical value of the bit signal r is "1" to "0", or "0" to "1"
The polarity inversion detection pulse signal s is generated when the transition to is detected. The D flip-flop 200 takes in the signal logical value of the MSB in the corrected read sample series p in response to the polarity inversion detection pulse signal s and outputs it as the polarity signal f.

The level conversion circuit 33 generates an error signal d having a voltage corresponding to the signal logic value of the polarity signal f. For example, +5 while the polarity signal f of the logical value "0" indicating the positive polarity is supplied from the polarity detection circuit 32.
The error signal d having a voltage of -5 [V] is generated during the period in which the polarity signal f of [V] and the logical value "1" indicating the negative polarity is supplied. The LPF 21 supplies a voltage obtained by smoothing the error signal d to the subtractor 15 as an error voltage e.

According to the operations of the polarity detection circuit 32, the level conversion circuit 33, and the LPF 21, the value of each sample in the extracted sample series c has a positive polarity value and a negative polarity value. The error voltage e corresponding to the difference from the period is obtained. Further, the configuration shown in FIG. 7 may be combined with the switch 30 and the synchronization determination circuit 31 shown in FIG. 6 to obtain the configuration shown in FIG.

In the configuration shown in FIG. 9, during the period in which the sampling clock is stable, the value of each sample in the extracted sample series c is a positive polarity value and a negative polarity value. The error voltage e corresponding to the difference with the current period is calculated. On the other hand, during the period in which the sampling clock is unstable, it corresponds to the difference between the period in which the value of each sample in the corrected read sample series b has a positive polarity value and the period in which it has a negative polarity value. The error voltage e is calculated.

In FIG. 9, the MSB of each sample in the corrected read sample series b is used as a polarity signal indicating whether the corrected read sample series b has a positive polarity or a negative polarity. Further, instead of the D / A converter 20 shown in FIGS. 2 and 6, PWM (puls
An error signal d having a pulse width corresponding to the value of each sample of the extracted sample sequence c may be generated using an ewidth modulation circuit.

Further, the LPF 21 and the subtracter 15 shown in FIGS. 2, 6, 7 and 9 may be constituted by an inverting integration circuit composed of operational amplifiers. Moreover, the above-mentioned FIG. 2 and FIG.
, The analog error signal d after D / A conversion is set to L
Although the error voltage e is obtained by smoothing with the PF 21, the digital extracted sample series before D / A conversion may be smoothed with a digital filter to obtain the error voltage e.

Further, the sample extraction circuit 19 in the above embodiment detects the polarity inversion of the corrected read sample series b, and extracts the smaller absolute value of the two samples immediately before and after this inversion. The sample series c may be used. Further, in the embodiment shown in FIGS. 6 and 9, the synchronization / asynchronous state of the sampling clock signal is determined by the synchronization determination circuit 31, but the function of the synchronization determination circuit 31 is recorded by this recording. It may be executed by a CPU (not shown) provided for performing various controls of the information reproducing apparatus.

Further, a dropout compensating circuit for compensating for dropout due to scratches or stains on the recording disk 12 may be provided in the structure of the above embodiment. For example, in the recording information reproducing apparatus shown in FIGS. 2 and 6, when the dropout is detected, the D / A converter 20 is forcibly supplied with a zero level signal. Further, in the recording information reproducing apparatus shown in FIGS. 7 and 9, when a dropout is detected, the level conversion circuit 32 is forcibly supplied with a signal whose polarity changes at a duty of 50%. Of. With this configuration, when a dropout occurs,
Since the error signal d has a zero level, it is possible to prevent malfunctions when this dropout occurs.

[0031]

As described above, according to the recorded information reproducing apparatus of the present invention, the low frequency band offset component can be removed from the read signal. Therefore, it is possible to perform highly reliable information reproduction even from a recording medium such as a DVD in which a large amount of low frequency components remain in the read signal because the 8/16 modulation code is used. .

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a conventional recorded information reproducing apparatus.

FIG. 2 is a diagram showing a configuration of a recorded information reproducing apparatus according to the present invention.

FIG. 3 is a diagram showing an internal configuration of a sample extraction circuit 19.

FIG. 4 is a diagram showing operation waveforms of a sample extraction circuit 19.

FIG. 5 is a diagram showing operation waveforms of the recorded information reproducing apparatus according to the present invention.

FIG. 6 is a diagram showing another embodiment of the recorded information reproducing apparatus according to the present invention.

FIG. 7 is a diagram showing another embodiment of the recorded information reproducing apparatus according to the present invention.

FIG. 8 is a diagram showing an internal configuration of a polarity detection circuit 32.

FIG. 9 is a diagram showing another embodiment of the recorded information reproducing apparatus according to the present invention.

[Explanation of symbols for main parts]

 11 Pickup 12 Recording Disc 15 Subtractor 16 A / D Converter 19 Sample Extraction Circuit 32 Polarity Detection Circuit

Claims (6)

[Claims] 1. A recorded information reproducing apparatus for reproducing recorded information recorded on a recording medium, comprising: information reading means for reading recorded information from the recording medium to obtain an analog read signal; and the read signal. A subtractor for subtracting an error voltage from the corrected read signal to obtain a corrected read signal; an A / D converter for sampling the corrected read signal and converting it into a digital corrected read sample sequence; Decoding means for performing decoding, sample extracting means for extracting only a sample existing at a position closest to a zero-cross time point in the corrected read sample series from the corrected read sample series to obtain an extracted sample series, and in the extracted sample series Each sample of is converted into an analog signal of a level corresponding to the sample value and is generated as the error voltage. An information recording / reproducing apparatus having an error voltage generating means. 2. A recorded information reproducing apparatus for reproducing recorded information recorded on a recording medium, comprising: information reading means for reading recorded information from the recording medium to obtain an analog read signal; and the read signal. A subtractor for subtracting an error voltage from the corrected read signal to obtain a corrected read signal; an A / D converter for sampling the corrected read signal according to a sampling clock signal to convert it into a digital corrected read sample sequence; A decoding means for decoding the recorded information from the sequence, and a sample extracting means for extracting from the corrected read sample sequence only the sample existing at the position closest to the zero-cross time point in the corrected read sample sequence to obtain an extracted sample sequence; Synchronization determination means for determining whether the sampling clock signal is synchronized with the read signal, When it is determined by the synchronization determination means that the sampling clock signal is synchronized with the read signal, each sample in the extracted sample series is converted into an analog signal having a level corresponding to the sample value. While the error voltage is generated, if the synchronization determination unit determines that the sample is asynchronous, each sample in the corrected read sample series is converted into an analog signal having a level corresponding to the sample value. An information recording / reproducing apparatus comprising: an error voltage generating unit that generates an error voltage. 3. The sample extracting means, an interpolation value calculating means for obtaining an interpolation value for each sample in the corrected read sample series, and a polarity inversion detection signal when it is detected that the polarity of the interpolation value is inverted. 3. The polarity reversal detection means for generating the signal, and the storage means for taking in the corrected read sample series in accordance with the polarity reversal detection signal and outputting the corrected read sample series as the extracted sample series.
Recorded information reproducing apparatus described. 4. A recorded information reproducing apparatus for reproducing recorded information recorded on a recording medium, comprising: information reading means for reading recorded information from the recording medium to obtain an analog read signal; and the read signal. A subtractor for subtracting an error voltage from the corrected read signal to obtain a corrected read signal; an A / D converter for sampling the corrected read signal and converting it into a digital corrected read sample sequence; Recorded information comprising: a decoding unit that performs decoding, and an error voltage generation unit that generates, as the error voltage, a voltage corresponding to the polarity of the sample existing at the position closest to the zero-cross time point in the corrected read sample sequence. Playback device. 5. The error voltage generating means detects whether the polarity of each sample existing at a position closest to the zero-cross time point in the corrected read sample series is positive or negative. 5. The polarity detecting means for generating a polarity signal indicating the polarity, and the level converting means for generating a voltage corresponding to the polarity indicated by the polarity signal and using the voltage as the error voltage. Recorded information reproducing device. 6. The polarity detection means, an interpolation value calculation means for obtaining an interpolation value for each sample in the corrected read sample series, and a polarity inversion detection signal when it is detected that the polarity of the interpolation value is inverted. 6. The polarity reversal detection means for generating the signal and the storage means for taking in the MSB of the sample value in the corrected read sample series in response to the polarity reversal detection signal and outputting it as the polarity signal. Recorded information reproducing apparatus described.