JPH09306196A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] When only some banks have defective products, it is possible to access only other banks.
Provided is a semiconductor device capable of relieving one bank defect of a 6M bit product as an 8M bit product. SOLUTION: When a chip test is performed, a good product and a defective product are judged for each bank, and when it is found that a certain bank is defective, the attribute of the chip is determined by means indicating the defective bank and the detection unit. By providing a means for switching the bank number setting value in the shown DeviceType register and a means for setting the bank selection signal so that only the non-defective bank is accessed, the 16M-bit non-defective article can be made into an 8-Mbit article.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a Rambus type DRA having a plurality of banks.
About M.

[0002]

2. Description of the Related Art Rambus type DRAM (referred to as "RDRAM") for improving data transfer speed between a controller such as a microprocessor and an image processor and a DRAM (dynamic random access memory).
Has been proposed.

In a general-purpose DRAM, an address is input from an address terminal and data is input / output through a data terminal. Therefore, when the memory capacity and the configuration change, the required number of address terminals and data terminals change, and the package and terminal configuration change.

On the other hand, RDRAM uses bus data (B
usData) Adopts a protocol type access method of inputting or outputting address and data using terminals 0 to 8, and access to the memory inputs operation function (read / write etc.), access address etc. by request packet, Read data and write data are performed using data packets. This example is shown in FIG.

A packet called a request packet having operation function and access start address information is sent from the controller to the RDRAM. The RDRAM inputs this request packet in synchronization with the external clock RxClk.

According to the operation and address designated by this request packet, for example, in the case of a read operation, read data is output by a data packet using bus data (BusData) 0-8.

An outline of the request packet is shown in FIG. Here, only an area showing an address is shown, and a blank portion has information such as designation of an operation function.

Adr [9: 2] (second to second address signals)
9 bits), Adr [17:10], Adr [26: 1
8] and Adr [35:27] indicate access start addresses.

As described above, in the RDRAM, since the access is performed using the request packet and the data packet instead of directly inputting the address from the address terminal, the package and the terminal arrangement are common regardless of the memory capacity and the configuration. You can

For example, the RDRAM currently commercialized
The 16M bit product and the 8M bit product have exactly the same package and terminal arrangement.

In RDRAM, the sense amplifier of general-purpose DRAM is used as a sense amplifier cache.
ROW accessed from the controller last time
If the address is a (row) address, data is exchanged with the sense amplifier without accessing the memory cell.

It has been considered to divide the memory cell array into a plurality of banks in order to increase the hit rate of the sense amplifier cache. For example, a 16M-bit RDRAM has a two-bank structure (one bank is 8M bits). Note that 8M has a one-bank configuration.

The number of banks in this RDRAM is stored in an area called Bankbits in a part of the device type (DeviceType) register, and it is determined by reading the contents of the device type register from the controller. .

FIG. 8 shows the device type (D
2 shows the configuration of the deviceType register. The device type register has a 9-bit width (0 to 8 bits) and a 4-byte area. Here, the bit indicated by “R” indicates reserve, and the current RD
It means that it is not used in RAM.

This device type (DeviceType
e) In the register, the number of bits of the row address of the RDRAM (RowBits), the number of bits of the column address (ColumnBits), whether the data width is 8 bits or 9 bits (Bonus), and the version of the RDRAM (Vers)
section), the type of RDRAM (Type), and a bit (BankBits) indicating the number of banks.

The controller reads these contents and reads R
Determine the attributes of the DRAM.

The value of BankBits is "0" in one bank, "1" in two banks, and "2" in four banks. Since the 16Mbit RDRAM has a two-bank configuration, BankBits is "1", 8Mbit RDRAM
BankBits is "0" because it has one bank. Also, since the 32-Mbit RDRAM has a 2-bank configuration, BankBits is "1", and the 64-Mbit RDRAM is
BankBits is "2" because it has 4 banks.

Bits other than Bankbits are set to the same value in 16M DRAM and 8M DRAM.

FIG. 9 shows a conventional 16 Mbit RDRAM.
FIG. 10 is a block diagram showing the configuration of the 8-Mbit product.

The conventional 16 Mbit RDRAM is Ram
bus control unit 1, 8 Mbit upper bank (Upp
erBank; upper bank) cell array 2, 8 Mbit lower bank (lower bank)
Cell array 3, device type register (DiceT
typeRegister) 14.

The 16M-bit product has two banks with the 8-Mbit memory cell array as one bank. The device type register 14 is configured as shown in FIG. 9, and when a read request of the device type register is input by a request packet from the controller, a register read enable (Register).
The Read Enable signal 142 becomes High level, and the bank bit (Bank) that is the output of the AND gate is output.
Bits) 141 becomes High level, and Rambu
"1" is read from the s control unit 1 to indicate that it is a two-bank product.

At the time of accessing the memory portion, when accessing the upper bank (UpperBank) cell array 2, the bank select (BankSelect) signal 10
1 becomes High level, and the upper bank (Uppe
rBank) Cell array 2 is selected. In the case of access to the lower bank cell array 3, a bank select signal 1
01 becomes Low level, and the lower bank (Lowe
rBank) Cell array 3 is selected.

Next, referring to FIG. 10, an 8M bit RD
The RAM will be described. Ra for 8-Mbit RDRAM
mbus controller 21, 8M bit cell array 20, (D
deviceTypeRegister) 24.

When a read request is input from the controller to the device type register (DeviceTypeRegister) 24, the register read enable (RegisterReadEnable) signal 212 is set to High level, and the bank bit (Ban).
kBits211) becomes Low level and "0" is read out, indicating that it is a 1-bank product.

The bank selection signal is always the cell array 2
0 is selected, and the cell array 20 to the data bus 20
Input and output data through 01.

[0026]

As described above, 16M
The bit product and the 8M bit product are the same in the package and the like except for the capacity and the bank configuration. Therefore, when a defective bit exists in only one bank out of two banks in a 16 Mbit product, the product can be used as an 8 Mbit product by accessing only the other bank.

However, in the conventional RDRAM, the device type register (D
1 bank product or 2 bank product is set in the device type register (ROM state), and it is impossible to use 16M of the good bank product as 8M as it is.

This is because when the controller reads the device type register of the non-defective 16 Mbit bank,
Recognized as a 16 Mbit product, 16 from the controller
It may be accessed as an M-bit product.

For the 16M-bit product, the bank to be accessed is determined by the bank address from the controller. For this reason, a bank with a 16 Mbit product is 8
When trying to use as an M-bit product, normal operation cannot be performed unless a good bank is specified from the controller, but it is difficult for the controller to detect and specify a defective bank of the RDRAM.

Therefore, the present invention has been made in view of the above circumstances, and an object thereof is to make it possible to access only another bank when a defective product exists in only one bank. For example, it is to provide a semiconductor device capable of relieving one bank defect of a 16 Mbit product as an 8 Mbit product.

[0031]

In order to achieve the above object, a semiconductor memory device of the present invention has a Ra structure of a plurality of banks.
In mbus type DRAM, at the time of chip test,
When a non-defective product and a defective product are determined for each bank and a certain bank is found to be a defective product, a means for indicating that the bank is defective, and a device type register for indicating the chip attribute by the means. And a means for setting a bank selection signal so that only non-defective banks are accessed.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows the configuration of the first embodiment of the present invention, and is a block diagram showing the configuration when the present invention is applied to a 16-Mbit RDRAM having a 2-bank configuration.

Referring to FIG. 1, a 16M DRAM according to a first embodiment of the present invention includes a Rambus controller 1, an 8M-bit upper bank (UpperBan).
k) Cell array 2, 8 Mbit lower bank (Lo)
cell bank 3, device type register (DeviceTypeResitor) 4, bank selection circuit 5, lower bank (Lower Bank) detection circuit 6, and upper bank (Upper Bank).
It is composed of a detection circuit 7.

The lower bank detection circuit 6 has a fuse 61 that is cut when a defective bit exists in the lower bank cell array 3, and an output 6 when the fuse 61 is cut.
N-channel transistor 62 for fixing 01 to Low level.

Similarly, the upper bank detection circuit 7 includes a fuse 71 that is cut when a defective bit exists in the upper bank cell array 2 and a fuse 71.
And an n-channel transistor 72 for fixing the output 701 to the Low level at the time of cutting.

The n-channel transistors 62 and 72 normally have a large channel length L in order to suppress the current when the fuses 61 and 71 are not cut.

The bank selection circuit 5 outputs the outputs 601 and 701 of the lower bank and upper bank detection circuits 6 and 7.
And the bank select (Ba
nkSelect) 101 from the bank selection signal 501,
502 is output.

The device type register 4 determines the Ramb according to the levels of the outputs 601 and 701 of the detection circuits 6 and 7.
Register read enable from the us controller 1 (Reg
If isterReadEnable) 102 is at a high level, bank bits (Bank bits) 401
Is output to the Rambus control unit 1.

Next, the operation of the first embodiment of the present invention will be described. FIG. 2 shows a flowchart for the chip test.

During the chip test, if there is no defective bit in both the upper and lower banks, neither of the fuses 61 and 71 of the detection circuits 6 and 7 is cut. In this case, the detection circuits 601 and 701 are High.
It is fixed at the h level.

It is assumed that a request packet for reading the device type register 4 is input to this chip.

The register read enable 102 from the Rambus control unit 1 becomes High level, the Bank bit 401 is outputted as High level, and the Rambus
A bank bit "1" indicating that the chip has a two-bank configuration is output from the controller 1 to a controller (not shown) (step 203 in FIG. 2).

Next, it is assumed that there is a memory access from the controller to the upper bank cell array 2. In this case, the bank select 101 becomes the High level indicating the upper bank access.

The bank selection circuit 5 has a bank select 10
1 is at the high level and the outputs 601 and 701 of the detection circuits 6 and 7 are at the high level.
The upper bank selection signal 501 is set to High level, the upper bank cell array 2 is accessed, and data is output to the Rambus control unit 1 through the data bus 201.

Similarly, in the case of access to the lower bank cell array 3, the bank select 101 is at the low level indicating the lower bank access, and the bank selection circuit 5 indicates that the bank select 101 is at the low level and the detection circuit. Outputs 601 and 701 of 6 and 7 are High
Since it is at the h level, the lower bank selection signal 5
02 is set to the high level, the lower bank cell array 3 is accessed, and the Rambu is passed through the data bus 301.
Data is output to the control unit 1.

Here, it is assumed that there is a defect in the lower bank cell array 2 during the chip test (see step 202 in FIG. 2).

In this case, only the fuse 61 of the lower bank detection circuit 6 is cut (see step 205 in FIG. 2). As a result, the output 6 of the lower bank detection circuit 6
01 is fixed to the Low level. The output 701 of the upper bank detection circuit 7 is at high level.

In the bank selection circuit 5, since the output 601 of the lower bank detection circuit 6 is at the low level, the upper bank selection signal 501 output from the bank selection circuit 5 is at the high level and the lower bank selection signal 502 is at the low level. Fixed to the level.

Further, no matter what level the bank select 101 from the Rambus controller 1 is, the output of the bank select circuit 5 is not affected.

As a result, the upper bank cell array 2 is always selected for this chip.

Next, assume that a request packet for reading the device type register 4 is input to this chip.

The register read enable 102 from the Rambus control unit 1 becomes High level, but since the output 601 of the lower bank detection circuit 6 is Low level, the bank select 401 outputs Low level,
The Rambus controller 1 outputs "0" indicating that the chip has a one-bank configuration to the controller (step 207).

On the other hand, if the upper bank cell array 2 is defective, the fuse 701 of the upper bank detection circuit 7 is cut (step 206 in FIG. 2). As a result, the output 701 of the upper bank detection circuit 7 becomes Lo.
Fixed to w level. The output 601 of the lower bank detection circuit 6 is at high level.

In the bank selection circuit 5, since the output 701 of the upper bank detection circuit 7 is Low level, the upper bank selection signal 501 output from the bank selection circuit 5 is L level.
The lower bank selection signal 502 becomes High at the ow level.
It is fixed at the h level.

As a result, the lower bank cell array 3 is always selected for this chip. When a request packet for reading the device type register 4 is input, similarly, the bank bit 401 is Low.
The Rambus control unit 1 outputs "0" to the controller, which indicates that the chip has a one-bank configuration.

The above is summarized as shown in FIG.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram of the second embodiment of the present invention. In a 64 Mbit DRAM having 16 Mbits as one bank and 4 banks, there is a defect in any bank. If you do, 2
An example of repairing as a 32 Mbit product having a bank configuration is shown.

In the second embodiment of the present invention, 2
An example will be shown in which one bank is used as one group and if one of them has a defect, the other bank is used as a two-bank product.

64M DRAM according to this embodiment
Is the Rambus controller 41, 16 Mbit bank 0
The cell array 21 includes a bank 1 cell array 22, a bank 2 cell array 23, a bank 3 cell array 24, a device type register 44, a bank selection circuit 45, a bank 23 detection circuit 46, and a bank 01 detection circuit 47.

The bank 23 detection circuit 46 includes a fuse 61 that is cut when a defective bit exists in the bank 2 cell array 23 or the bank 3 cell array 24, and an n-channel transistor that fixes the output 4601 to a low level when the fuse 61 is cut. 62 and.

Similarly, the bank 01 detection circuit 47 includes a fuse 71 which is cut when a defective bit exists in the bank 0 cell array 21 or the bank 2 cell array 22, and
An n-channel transistor 72 for fixing the output 701 to a low level when the fuse 71 is cut.

The transistors 62 and 72 are the fuse 6
In order to suppress the current when not cutting 1, 71,
Usually, the channel length L is increased.

The bank selection circuit 45 includes the banks 23 and 01.
The outputs 4601 and 4701 of the detection circuits 46 and 47 and Ra
Bank select 4101, 4 from the mbus controller 41
From 102, bank selection signals 4501, 4502, 450
3, 4504 is output.

The device type register 45 is provided in the bank 2
Outputs 4601 and 4701 of the 3,01 detection circuits 46 and 47
When the register read enable 4112 from the Rambus control unit 41 is High level,
The bank bits 401 and 402 are set to the Rambus control unit 41.
Output to

In the 64M DRAM, the number of banks is 4, and the bank bit (Ban of the device type register 4 is
kBits) indicates 2, and in the case of this embodiment, the lower bits of the bank bits (BankBits) are represented by bank bits 4401 and the upper bits are represented by bank bits 4402.

Bank bits (BankBit) output from the signals 4401 and 4402 and the Rambus control unit 41.
The relationship with s) is shown in the table below.

[0067]

[Table 1]

Next, the operation of the second embodiment of the present invention will be described.

If there is no defective bit in both banks during the chip test, the fuse 6 of the detection circuits 46 and 47 is used.
Neither fuse 1 nor 71 is cut. In this case, the detection circuit outputs 4601 and 4701 are Hi.
It is fixed at gh level.

It is assumed that a request packet for reading the device type register 44 is input to this chip. When the register read enable 4112 from the Rambus control unit 41 becomes High level, the bank bit 4
401 outputs Low level, and bank bit 440
2, the high level is output, and as a result, “2” is output as the bank bit from the Rambus control unit 41, and it is output to the controller that the chip has four banks.

Next, it is assumed that there is a memory access from the controller to the bank 0 cell array 21. in this case,
Low levels of the bank selects 4101 and 4102 are output from the Rambus control unit 41.

The bank selection circuit 45 uses the bank selection 4
The bank 0 selection signal 4501 is Hi because the outputs 101 and 4102 are Low level and the outputs 4601 and 4701 of the detection circuits 46 and 47 are High level.
The bank 0 cell array 21 is accessed and the Rambus control unit 4 is accessed through the data bus 2101.
Output data to 1.

At this time, if it is found during the chip test that the bank 0 cell array 21 has a defect, only the fuse 71 of the bank 01 detection circuit 47 is cut.

As a result, the output 4701 of the detection circuit 47 is obtained.
Is fixed to the Low level. Further, the output 4601 of the bank 23 detection circuit 46 remains at the high level.

Since the output 4701 of the detection circuit 47 is low level, the bank selection circuit 45 outputs the signal 4 of the selection circuit 45.
505 is a low level and 4506 is a high level. As a result, the bank 0 selection signal 4501 and the bank 1
The selection signal 4502 is fixed at Low level. The bank 2 selection signal 4502 and the bank 3 selection signal 4503 are Ra.
Bank select signal 4101 from the mbus controller 41
The bank 2 or the bank 3 is selected depending on the level of, and the bank 0 having the defect is not accessed.

Next, it is assumed that a request packet for reading the device type register 44 is input to this chip.

When the register read enable 4112 is output from the Rambus control unit 41 at the High level, the output 4701 of the detection circuit 47 is at the Low level, the bank bit 4401 is output at the High level, and the bank bit 4402 is output at the Low level. Rambus
The control unit 41 outputs "1" indicating that the chip has a two-bank configuration to the controller.

The same operation is performed for the other banks, which are summarized as shown in FIG.

[0079]

As described above, according to the present invention, for example, a one-bank non-defective product of 16 Mbit product can be salvaged as an 8 Mbit product, and a chip that should be a defective product of 16 Mbit product is an 8 Mbit product. Becomes a product as
This will reduce the cost of the entire 6 Mbit product.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart showing an operation during a chip test according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a list of operations according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a list of operations according to the second embodiment of the present invention.

FIG. 6 is a diagram showing an outline of access to RDRAM.

FIG. 7 is a diagram showing an outline of a request packet.

FIG. 8 is a diagram showing a configuration of a device type (DeviceType) register.

FIG. 9 is a block diagram showing a configuration of a conventional 16 Mbit RDRAM.

FIG. 10 is a block diagram showing a configuration of an 8-Mbit RDRAM.

[Explanation of symbols]

1, 21, 41 Rambus control unit 2 Upper bank (UpperBank) cell array 3 Lower bank (LowerBank) cell array 4, 14, 24, 44 Device type register (De)
ViceTypeRegister 5, 45 bank (Bank) selection circuit 6 lower bank (Lower Bank) detection circuit 7 upper bank (Upper Bank) detection circuit 20 8M bit cell array 21 bank 0 (Bank0) cell array 22 bank 1 (Bank1) cell array 23 2 bank 2 (Bank) ) Cell array 24 Bank 3 (Bank 3) cell array 46 Bank 23 (Bank 23) detection circuit 47 Bank 01 (Bank 01) detection circuit 61, 71 Fuse 62, 72 n-channel transistor 101, 4101, 4102 Bank select (Ban)
kSelect signal 102, 142, 212, 4112 Register read enable signal (RegisterReadEnable) signal 201 Upper bank (UpperBank) data bus 301 Lower bank (LowerBank) data bus 601 Upper bank (UpperBank) selection circuit 6 output line 701 Lower bank (LowerBank) Select circuit 7 output line 2001 8M bit cell array data bus 2101 bank 0 (Bank 0) cell array data bus 2102 bank 1 (Bank 1) cell array data bus 2103 bank 2 (Bank 2) cell array data bus 2104 bank 3 (Bank 3) cell array data bus 4505 bank 01 (Bank01) selection signal 4506 Bank 23 (Bank2) ) Selection signal 141,212,401,4401,4402 bank bit (BankBits) signal

Claims (2)

[Claims] 1. A Rambus type DR having a plurality of banks
In the AM, at the time of a chip test, a non-defective product and a defective product are determined for each bank, and when a certain bank is found to be a defective product, means for indicating that the bank is defective, and said means, The semiconductor memory device comprising: means for switching the bank number set value in the device type register indicating the attribute of; and means for setting a bank selection signal so that only non-defective banks are accessed. 2. The defect based on the outputs of means for holding information on presence / absence of a defect in a cell array forming a bank in units of one or a plurality of banks, and means for holding information on presence / absence of a defect in units of one or a plurality of banks. And a means for selecting a bank of a non-defective cell array, and a means for notifying how many banks are currently configured on the basis of the output of the means for holding information on presence / absence of a defect in units of one or a plurality of banks. A semiconductor memory device comprising: