JPH09321601A - Level conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level conversion circuit from which a pulse signal not affected by parasitic capacity and dispersion in a manufacturing process of components. SOLUTION: When a pulse is inputted to an input terminal IN and a pulse level of an emitter of a transistor(TR) Q5 goes to a low level, a TR Q11 brings forcibly a discharge voltage based on a time constant consisting of a resistance of a resistor R3 and a parasitic capacitance C1 to a low level. Thus, a pulse not affected by a delayed voltage due to discharge is outputted from an emitter of a Tr Q5 . The pulse is fed to a differential amplifier consisting of TRs Q1 , Q2 . Thus, an accurate pulse not affected by the discharge voltage is outputted from the collectors of the TRs Q1 , Q2 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit suitable for sending drive pulses to circuits such as sample and hold used in electronic still cameras and the like.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a configuration example of a conventional level conversion circuit. This level conversion circuit inputs a pulse to the input terminal IN and outputs 18 pulses to the output terminals OUT1 and OUT2.
Outputs pulses with 0 ° phase difference. Referring to FIG. 9, this level conversion circuit includes NTN transistors Q ₁ and Q ₂ and a resistor R.
_A differential amplifier consisting of ₁ , R ₂ , and a constant current source I ₀₁ , and NTN
Transistor Q ₃ , diodes D ₁ and D ₂ and constant current source I ₀₂
A level shift circuit consisting of an NTN transistor Q ₄ , diodes D ₃ , D ₄ and a constant current source I _03, and an emitter follower circuit consisting of an NTN transistor Q ₅ and a resistor R ₃ .

As shown in the figure, a predetermined bias potential V _REF1 is connected to the base of the transistor Q ₂ , and the base of the transistor Q ₁ is the emitter of the transistor Q ₅ and the resistor.
A pulse is supplied to the input terminal IN connected to R ₃ and connected to the base of the transistor Q ₅ . The emitter follower circuit buffers the pulse input to the input terminal IN, in this example the pulse shown in Fig. 10 (a), and transfers it from the emitter to the differential amplifier.
The pulse indicated by the solid line is sent to (b). The differential amplifier converts the level of this pulse and sends the pulse shown by the solid line in Fig. 10 (c) from the collector of transistor Q _{1 to} the base of transistor Q ₄ , and from the collector of transistor Q _{2 to} the base of transistor Q ₃ . The pulse shown by the solid line in Fig. 10 (d) is sent.

[0004] Thus, the transistors Q base-emitter voltage V _BE3 of the base to supply a pulse of ₃ transistor Q ₃ and a diode D _1, the forward voltage of each of the D ₂ V _D1, V _D2
The level is shifted by the amount of and output from the output terminal OUT1.
The pulse supplied to the base of the other transistor Q ₄ is level-shifted by the base-emitter voltage V _BE4 of the transistor Q ₄ and the forward voltages V _D3 and V _D4 of the diodes D ₃ and D ₄ , respectively, and output. Output from terminal OUT2.

Such a level conversion circuit is shown in FIG.
Used as a drive circuit for the sample and hold circuit shown in 11. This sample and hold circuit has a signal input terminal SI
N receives the image signal V _sig to be sampled and held from, for example, a CCD (charge coupled device), and samples this
Hold and output to the signal output terminal SOUT.

Referring to FIG. 11, this sample and hold circuit has input terminals IN1 and IN2 which are respectively connected to the output terminals OUT1 and OUT2 of FIG. 9, and the base has the input terminal IN1 and IN2.
Consisting of NTN transistor Q _8, Q ₉ is connected to IN2 differential pair is formed. The emitters of the transistors Q ₈ and Q ₉ are connected to the ground via the constant current source I ₀₅ , and the base and emitter are connected in series between their collectors.
Transistor Q ₁₀ is provided.

The base of this NTN transistor Q ₁₀ is a resistor
Transistor Q ₁₁ emitter and constant current source via R ₅
The image signal V _sig to be sampled and held is supplied to the signal input terminal SIN connected to I ₀₄ and connected to the base of the transistor Q ₁₁ . In addition, NTN transistor Q ₁₀
The emitter of is connected to the ground via the holding capacitor C and outputs the hold voltage accumulated in the holding capacitor C from the signal output terminal SOUT.

As mentioned before, when a pulse is applied to the input terminal IN of the circuit shown in FIG. 9, the output terminals OUT1 and OUT2 are output.
Outputs pulses whose phases are 180 degrees different from each other.
These pulses are supplied to the input terminals IN1 and IN2 of the circuit shown in FIG. As a result, when the transistor Q ₈ is turned off and the transistor Q ₉ is turned on, the image signal V _sig input to the capacitor C is sampled and accumulated, and when the transistor Q ₈ is turned on and the transistor Q ₉ is turned off, the capacitor C is turned on. The electric charge of the image signal V _sig stored in is held.

FIG. 12 is a block diagram showing another configuration example of a conventional level conversion circuit. In FIG. 12, the same reference numerals as those in FIG. 9 are equivalent to those. Differences from FIG. 9 will be described.

The circuit of FIG. 12 corresponds to a reduction in power supply voltage of a pulse generator or the like. In order to lower the threshold level, instead of the emitter follower circuit composed of the NTN transistor Q ₅ and the resistor R _{3 of} FIG. Transistor Q ₆
And an emitter follower circuit consisting of a resistor R ₄ is provided. The circuit is also provided with a PNP transistor Q ₇ whose base is connected to a predetermined bias potential V _REF2 to prevent saturation of the NPN transistor Q ₁ forming the differential pair.

The collectors of the PNP transistors Q ₆ and Q ₇ are connected to the ground, and the common emitters of the transistors Q ₆ and Q ₇ are connected to the power supply V _CC via the resistor R ₄ . The base of the transistor Q ₆ is connected to the input terminal IN, and a pulse is supplied to this terminal IN. The emitter follower circuit is the input terminal IN
In this example, the pulse shown in FIG. 13 (a) is buffered, and the pulse shown by the solid line in FIG. 13 (b) is sent from the emitter to the differential amplifier. The differential amplifier converts the level of this pulse and sends the pulse shown by the solid line in Fig. 13 (c) from the collector of transistor Q _{1 to} the base of transistor Q ₄ , and from the collector of transistor Q _{2 to} the base of transistor Q ₃ . Figure
The pulse shown by the solid line is sent to 13 (d). These pulses are also sent to the sample and hold circuit shown in FIG. 11, similarly to the level conversion circuit shown in FIG.

[0012]

However, in the conventional level conversion circuit of FIG. 9, the emitter of the transistor Q ₅ , the resistor R ₃ , the base of the transistor Q ₁ and the ground are actually used as shown by the dotted line in FIG. A parasitic capacitance C ₁ exists between them. Therefore, the falling waveform of the pulse of the emitter of the transistor Q ₅ depends on the time constant of the parasitic capacitance C ₁ and the resistance R ₃ .
It becomes as shown by the dotted line in (b). Therefore, the rising waveform of the pulse of the collector of the transistor Q ₁ is shown in Fig. 10 (c).
And the falling waveform of the pulse of the collector of the transistor Q ₂ is as shown by the dotted line in FIG. 10 (d). Specifically, it means that the rise time of the pulse of the collector of the transistor Q ₁ is shifted from the position of the solid line to the position of the dotted line, that is, the rise time is delayed and the width of the pulse fluctuates. The same applies to the pulse of the collector of the transistor Q ₂ .

In this way, the rising or falling time of the pulse is delayed, and the pulse width thereof fluctuates. In other words, in this example, the sampling end time is delayed and its period is long, and the hold start time is delayed and its period is short. Become. As described above, the change in the sampling period and the hold period poses a problem particularly when the circuit is operated at high speed. Also, there is a problem in a system that creates a fine pulse from this pulse.

Specifically, in the circuit of FIG. 9, when the resistance R ₃ is 20 KΩ and the parasitic capacitance C ₁ is 0.1 pF, the time constant τ = C ₁ · R ₃ is 2 ns. Then, to the input terminal IN of the circuit of FIG. 9 having such a time constant, for example, a sample and hold pulse of 15 MHz, which is the same as when reading out the image signal stored in the CCD (both positive and negative pulse widths are 33 ns). When a positive pulse width of 35 ns and a negative pulse width of 31 ns are output from the output terminal OUT1, a negative pulse width of 35 ns is output from the output terminal OUT2. A pulse with a sex pulse width of 31 ns is output. In this case, the sampling end time is delayed by 2ns, the period is increased by 2ns, and the hold start time is 2ns.
Delay The period is shortened by 2ns. In this way, the change of the sampling period and the hold period becomes remarkable in a system operating at higher speed and becomes a problem.

Also, due to process (manufacturing) variations
C ₁ and R ₃ vary considerably. Therefore, the amount of pulse delay varies accordingly. For example, if R ₃ varies by ± 20%, it will vary by 1.6 to 2.4 ns in the above example, resulting in the disadvantage that the system performance will vary. This problem becomes noticeable in a system that requires high-speed operation.

Further, in the conventional level conversion circuit of FIG. 12,
Actually, as shown by a dotted line in FIG. 12, a parasitic capacitance C ₂ exists between the emitter of the transistor Q ₆ , the resistor R ₄ , the emitter of the transistor Q ₇ , the base of the transistor Q ₁ and the ground. Therefore, the rising waveform of the pulse of the emitter of the transistor Q ₆ depends on the time constant of the parasitic capacitance C ₂ and the resistance R ₄ .
It becomes as shown by the dotted line in (b). Therefore, the falling waveform of the pulse of the collector of transistor Q ₁ is shown in Fig. 13 (c).
And the rising waveform of the pulse of the collector of the transistor Q ₂ is as shown by the dotted line in FIG. 13 (d).

Specifically, referring to the waveform of the pulse of the collector of the transistor Q ₁ , it means that the rising time is shifted from the position of the solid line to the position of the dotted line, that is, the rising time is delayed and the width of the pulse is increased. Has changed. The same applies to the pulse of the collector of the transistor Q ₂ . Therefore, the circuit of FIG. 12 also suffers from the same problem as the circuit of FIG.

The present invention eliminates the drawbacks of the prior art and reduces the fluctuation of the pulse width due to the influence of the parasitic capacitance and the level conversion capable of reducing the fluctuation of the pulse width due to the influence of the process variation of the device. The purpose is to provide a circuit.

[0019]

In order to solve the above-mentioned problems, the level conversion circuit of the present invention includes a first transistor to which a pulse is input to the base and a first transistor to which a predetermined bias voltage is supplied to the base. A differential amplifier circuit configured by two transistors and differentially amplifying a pulse input to the base;
An emitter follower circuit including a third transistor having an emitter connected to the base of the first transistor and also connected to ground via a resistor or a constant current source, and a base connected to an input terminal; Connected to the emitter, the base connected to the input terminal,
And a pulse width variation prevention circuit including a fourth transistor whose collector is connected to the ground.
The level conversion circuit is further characterized by having a saturation prevention circuit including a fifth transistor having an emitter connected to the emitter of the third transistor, a base connected to the bias power supply, and a collector connected to the power supply. .

In order to solve the above-mentioned problems, another level conversion circuit of the present invention includes a first transistor to which a pulse is input to the base and a second transistor to which a predetermined bias voltage is supplied to the base. And a differential amplifier circuit that differentially amplifies the pulse input to the base, the emitter is connected to the base of the first transistor, and is connected to the power supply via a resistor or a constant current source, and the base is connected to the input terminal. A pulse width variation prevention circuit including an emitter follower circuit including a connected third transistor, a fourth transistor including an emitter connected to the emitter of the third transistor, a base connected to an input terminal, and a collector connected to a power supply It is characterized by having a circuit. The level conversion circuit is further characterized in that it has a saturation prevention circuit including a fifth transistor whose emitter is connected to the emitter of the third transistor, whose base is connected to the bias power supply, and whose collector is connected to the ground. .

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a level conversion circuit according to the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows a first embodiment of the level conversion circuit of the present invention. In addition, in FIG.
Those having the same reference numerals as are equivalent to those. Therefore, differences from FIG. 9 will be described.

The circuit of FIG. 1 further includes the components of FIG.
This is the addition of an NP transistor Q ₁₁ , which forcibly brings the voltage accumulated and discharged in the parasitic capacitance C ₁ to a low level when the pulse of the emitter of the transistor Q ₅ becomes a low level. The emitter of this transistor Q _{11 is connected to} the emitter of transistor Q ₅ , the base of transistor Q ₁ and resistor R ₃ , the collector of transistor Q ₁₁ is connected to ground, the base of transistor Q _{11 is} the base of transistor Q ₅ and the input. It is connected to the terminal IN and a pulse is supplied to this input terminal IN.

When the pulse shown in FIG. 2 (a) (the same pulse as in FIG. 10 (a)) is input to the input terminal IN, the transistor
The Q ₅ emitter outputs the falling pulses shown by the solid and dotted lines in Fig. 2 (b). In detail, the transistor
If there is no Q ₁₁ is outputs the falling edge of the pulse shown by the dotted line of the emitter of the parasitic capacitance affected by C ₁ transistor Q ₅ FIG 10 (b) as described above, if there is a transistor Q ₁₁ is When the pulse of the emitter of the transistor Q ₅ becomes low level, the transistor Q ₁₁ discharges the electric charge accumulated in the parasitic capacitance C ₁ and forcibly makes the voltage low level. Actually, in the falling part, as shown in FIG. 2 (b), there is no delay in the low level part above the base-emitter voltage V _BE11 of the transistor Q ₁₁ , and in the lower part as shown by the dotted line. The voltage due to the discharge remains.

Then, such a pulse is supplied to the differential amplifier. Since the differential amplifier does not use the discharge voltage portion of the input pulse, the collector of the transistor Q ₁ outputs a pulse having no pulse width variation due to the pulse delay as shown in FIG. 2 (c). The same applies to the pulse output from the collector of the transistor Q ₂ . A differential pair including PNP transistors or the like may be used instead of the differential pair including the NTN transistors Q ₁ and Q ₂ , the resistors R ₁ and R ₂ , and the constant current source I ₀₁ .

FIG. 3 shows a second embodiment of the level conversion circuit of the present invention. In addition, in FIG.
Those having the same reference numerals as are equivalent to those. Therefore, differences from FIG. 12 will be described.

The circuit of FIG. 3 has the components of FIG.
It is the addition of transistor Q ₁₂ , which charges the parasitic capacitance C ₂ and forces the voltage to a high level when the pulse of the emitter of transistor Q ₆ goes high. The emitter of this transistor Q ₁₂ is transistor Q
₆ , emitter of Q ₇ , base of transistor Q ₁ and resistor R
Connected to ₄ and the collector of transistor Q ₁₂ is the power supply V _CC
Connected to the base of transistor Q ₁₂ is a transistor
This input terminal is connected to the base of Q ₆ and the input terminal IN
IN is pulsed.

When the pulse shown in FIG. 4 (a) (the same pulse as in FIG. 13 (a)) is input to the input terminal IN, the transistor
The Q ₆ emitter outputs the pulses shown by the solid and dotted lines in Fig. 4 (b). In particular, if there is no transistor Q ₁₂ is to output the rise of the pulse indicated by the dotted line in the emitter of the influence of the parasitic capacitance C ₂ transistor Q ₆ is FIG. 13 (b) as described above, the transistor Q ₁₂ If so, transistor Q ₁₂ charges parasitic capacitance C ₂ and forces the voltage to a high level when the pulse of the emitter of transistor Q ₆ goes to a high level. In the falling part, as shown in Fig. 4 (b), the delay due to the capacitance C ₂ disappears in the high level part below the base-emitter voltage V _BE12 of the transistor Q ₁₂ , and in the upper part it is indicated by the dotted line. As shown, the voltage due to the discharge remains.

Then, such a pulse is supplied to the differential amplifier. Since the differential amplifier does not use the part of the discharge voltage of the input pulse, the collector of the transistor Q ₁ outputs a pulse whose pulse width does not fluctuate as shown in FIG. 4 (c). The same applies to the pulse output from the collector of the transistor Q ₂ . Note that R ₄ shown in FIG. 3 may be a constant current source, or NT
A differential pair made up of PNP transistors or the like may be used instead of the differential pair made up of N transistors Q ₁ and Q ₂ , resistors R ₁ and R ₂ and constant current source I ₀₁ .

FIG. 5 shows a third embodiment of the level conversion circuit of the present invention. In addition, in FIG.
And the same reference numerals as those in FIG. 12 are equivalent to those. Therefore, differences from FIGS. 3 and 12 will be described.

The circuit of Figure 5 is configured to change the R ₄ in FIG. 12 to the constant current source I _06, a resistor R ₇ to the emitter of the transistor Q ₇ as shown in the components of FIG. 12, the transistor Q ₁₂ A resistor R ₆ is added to the emitter, which prevents overcurrent of the transistors Q ₇ and Q ₁₂ . In this circuit, either of the resistors R ₆ and R ₇ may be added.

Referring to FIG. 5, the collectors of the transistors Q ₆ and Q ₇ are connected to the ground, and the emitter of the transistor Q ₇ is connected via the resistor R ₇ to the base of the transistor Q ₁ , the emitter of the transistor Q ₆ , and the resistor R _6. And connected to a constant current source I ₀₆ . The collector of the transistor Q ₁₂ is connected to the power supply, the emitter of the transistor Q ₁₂ is connected via the resistor R ₆ to the base of the transistor Q ₁ , the emitter of the transistor Q ₆ , and the resistor.
Connected to R ₇ and the constant current source I ₀₆ , the base of the transistor Q ₁₂ is connected to the base of the transistor Q ₆ and the input terminal IN, and a pulse is supplied to this input terminal IN.

Input terminal if transistor Q ₁₂ is not present
For example, when the pulse shown in Fig. 6 (a) is input to IN and the pulse of the emitter of the transistor Q ₆ becomes high level, the parasitic capacitance is charged by the constant current source I ₀₆ and the straight line shown by the dotted line in Fig. 6 (b). Output the pulse of the normal rising. The maximum amount of delay due to the falling edge shown by this dotted line is, for example, I ₀₆ = 100 μ.
When A, C ₃ = 0.1pF and V _CC = 5.0V, it becomes 3.5ns.

Further, in the case where the transistor Q ₁₂ is provided, when the pulse of the emitter of the transistor Q ₆ becomes high level, the parasitic capacitance C ₃ is charged and the voltage is forcedly made high level. The rising pulse shown by the solid line is output. That is, a pulse with no delay is output with respect to the waveform input to the input terminal IN.

Then, such a pulse is supplied to the differential amplifier. From the collector of the transistor Q ₁
As shown in (c), a pulse with no pulse width variation due to pulse delay is output. The same applies to transistor Q ₂
The same applies to the pulse output from the collector of.

FIG. 7 shows a fourth embodiment of the level conversion circuit of the present invention. In addition, in FIG.
Those having the same reference numerals as are equivalent to those. Therefore, differences from FIG. 9 will be described.

The circuit of FIG. 7 further includes the components of FIG.
An emitter follower circuit consisting of a PN transistor Q ₁₃ and a constant current source I ₀₇ , an NPN transistor Q ₁₄ whose base is connected to a predetermined bias potential V _REF1 to prevent saturation of the constant current source I ₀₆ , and pulse width fluctuation A PNP transistor Q ₁₅ for preventing the above is added, and a resistor R ₈ and a resistor R ₉ for preventing overcurrent of the PNP transistor Q ₁₅ and the NPN transistor Q ₁₄ are added.

The capacitance C _{3 in} the figure is the NPN transistor Q.
The parasitic capacitance between the emitter of ₁₃ , the constant current source I ₀₇ , the resistors R ₈ and R ₉ , the base of the NPN transistor Q ₁ and the ground. Further, in this circuit, either of the resistors R ₈ and R ₉ may be added, or neither of the resistors R ₈ and R ₉ may be added.

Referring to FIG. 7, transistors Q ₁₃ and Q ₁₄
Is connected to the power supply V _CC, and the emitter of the transistor Q ₁₄ is connected through the resistor R ₉ to the base of the transistor Q ₁ , the emitter of the transistor Q ₁₃ , the resistor R ₈ and the constant current source I _07.
It is connected to the. The collector of the transistor Q ₁₅ is connected to ground, the emitter of the transistor Q ₁₅ is connected via the resistor R ₈ to the base of the transistor Q ₁ , the emitter of the transistor Q ₁₃ , the resistor R ₉ and the constant current source I ₀₇ , the transistor Q ₁₅ The base of ₁₅ is connected to the base of the transistor Q ₁₃ and the input terminal IN, and a pulse is supplied to this input terminal IN.

Input terminal if no transistor Q ₁₅
When the pulse shown in Fig. 8 (a) is input to IN, the charge accumulated in the parasitic capacitance C ₃ is discharged by the constant current source I ₀₇ .
The linear falling pulse shown by the dotted line in 8 (b) is output. The maximum delay amount due to the fall shown by this dotted line is
For example, I ₀₆ = 100μA, C ₃ = 0.1pF, V _CC = 5.0V, 3.
It will be 5 ns.

When the transistor Q ₁₅ is provided, when the pulse of the emitter of the transistor Q ₁₃ becomes low level, the charge accumulated in the parasitic capacitance C ₃ is transferred to the transistor Q _15.
Since it is forcibly set to the low level by _{15, the} falling pulse shown by the solid line in FIG. 8 (b) is output. That is, a pulse with no delay is output with respect to the waveform input to the input terminal IN.

Then, such a pulse is supplied to the differential amplifier. From the collector of the transistor Q ₁
As shown in (c), a pulse with no pulse width variation due to pulse delay is output. The same applies to transistor Q ₂
The same applies to the pulse output from the collector of.

As described above, this embodiment is provided with a circuit for preventing fluctuation of the pulse width, which is composed of a transistor or the like. Therefore, by adding such a pulse width variation prevention circuit, it is possible to form a level conversion circuit which is not affected by the parasitic capacitance and is not affected by the process variation of the element.

[0044]

According to the level conversion circuit of the present invention, the pulse width variation prevention circuit is based on the time constants of the resistance value and the parasitic capacitance value when the pulse level of the emitter of the third transistor becomes a low level value. The discharge voltage is forcibly set to a low level based on the discharge characteristics determined by the constant current source current value and the parasitic capacitance value.

Further, according to the level conversion circuit of the present invention, the pulse width variation prevention circuit is based on the time constants of the resistance value and the parasitic capacitance value when the pulse level of the emitter of the third transistor becomes the high level value. The voltage to be charged or the voltage to be charged is forcibly set to a high level based on the charging characteristics determined by the constant current source current value and the parasitic capacitance value.

Therefore, if such a pulse width variation prevention circuit is used, it is possible to effectively obtain a pulse that is not influenced by parasitic capacitance, is not affected by process variation of the element, that is, has no pulse width variation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a level conversion circuit according to a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the level conversion circuit shown in FIG.

FIG. 3 is a circuit diagram of a level conversion circuit according to a second embodiment of the present invention.

4 is an explanatory diagram of the operation of the level conversion circuit shown in FIG.

FIG. 5 is a circuit diagram of a level conversion circuit according to a third embodiment of the present invention.

6 is an explanatory diagram of the operation of the level conversion circuit shown in FIG.

FIG. 7 is a circuit diagram of a level conversion circuit according to a fourth embodiment of the present invention.

8 is an explanatory diagram of the operation of the level conversion circuit shown in FIG.

FIG. 9 is a circuit diagram of a conventional level conversion circuit.

10 is an explanatory diagram of the operation of the level conversion circuit shown in FIG.

FIG. 11 is a circuit diagram of a conventional sample and hold circuit.

FIG. 12 is a circuit diagram of another conventional level conversion circuit.

13 is an explanatory diagram of the operation of the level conversion circuit shown in FIG.

[Explanation of symbols]

D ₁ , D ₂ , D ₃ , D ₄ Diode IN input terminal I ₀₁ , I ₀₂ , I ₀₃ , I ₀₄ , I ₀₅ , I ₀₆ , I ₀₇ Constant current source OUT1, OUT2 output terminal Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ , Q ₇ , Q ₈ , Q ₉ , Q ₁₀ , Q ₁₁ , Q ₁₂ , Q ₁₃ , Q ₁₄ , Q ₁₅
Transistors R ₁ , R ₂ , R ₃ , R ₄ , R ₅ , R ₆ , R ₇ , R ₈ , R ₉ resistors

Claims (7)

[Claims] 1. A differential amplifier comprising a first transistor having a base to which a pulse is input and a second transistor having a base to which a predetermined bias voltage is supplied, for differentially amplifying a pulse input to the base. A circuit, an emitter follower circuit including an emitter connected to the base of the first transistor and a third transistor connected to the ground via a resistor or a constant current source, and a base connected to an input terminal; And a pulse width variation prevention circuit including a fourth transistor connected to the emitter of the third transistor, connected to the input terminal at the base, and connected to the ground at the collector. 2. The level conversion circuit according to claim 1, wherein the level conversion circuit further has an emitter connected to the emitter of the third transistor, a base connected to a bias power supply, and a collector connected to a power supply. A level conversion circuit having a saturation prevention circuit including a fifth transistor. 3. A differential amplifier comprising a first transistor having a base to which a pulse is input and a second transistor having a base to which a predetermined bias voltage is supplied, and differentially amplifying a pulse input to the base. A circuit, an emitter connected to the base of the first transistor and connected to a power supply via a resistor or a constant current source,
An emitter follower circuit including a third transistor whose base is connected to an input terminal; and a fourth transistor whose emitter is connected to the emitter of the third transistor, whose base is connected to the input terminal, and whose collector is connected to a power supply. A level conversion circuit having a pulse width variation prevention circuit including the following. 4. The level conversion circuit according to claim 3, wherein the level conversion circuit further has an emitter connected to the emitter of the third transistor, a base connected to a bias power supply, and a collector connected to ground. A level conversion circuit having a saturation prevention circuit including a fifth transistor. 5. The level conversion circuit according to claim 2 or 4, wherein the level conversion circuit further comprises a first resistor between the emitter of the third transistor and the emitter of the fourth transistor. A level conversion circuit comprising: 6. The level conversion circuit according to claim 2 or 4, wherein the level conversion circuit further includes a second resistor between the emitter of the third transistor and the emitter of the fifth transistor. A level conversion circuit comprising: 7. The level conversion circuit according to claim 2, wherein the level conversion circuit further includes a first resistor between the emitter of the third transistor and the emitter of the fourth transistor. And a second resistor provided between the emitter of the third transistor and the emitter of the fifth transistor.