JPH0933606A - Jig for inspection of semiconductor element - Google Patents
Jig for inspection of semiconductor elementInfo
- Publication number
- JPH0933606A JPH0933606A JP7205136A JP20513695A JPH0933606A JP H0933606 A JPH0933606 A JP H0933606A JP 7205136 A JP7205136 A JP 7205136A JP 20513695 A JP20513695 A JP 20513695A JP H0933606 A JPH0933606 A JP H0933606A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- semiconductor element
- circuit board
- anisotropic conductive
- conductive sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000007689 inspection Methods 0.000 title claims abstract description 24
- 229920001971 elastomer Polymers 0.000 claims abstract description 9
- 239000005060 rubber Substances 0.000 claims abstract description 9
- 230000000149 penetrating effect Effects 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- 229920002725 thermoplastic elastomer Polymers 0.000 description 2
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
- 229920000181 Ethylene propylene rubber Polymers 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229920000459 Nitrile rubber Polymers 0.000 description 1
- 239000005062 Polybutadiene Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 239000004830 Super Glue Substances 0.000 description 1
- 229920006311 Urethane elastomer Polymers 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000003522 acrylic cement Substances 0.000 description 1
- 229920000800 acrylic rubber Polymers 0.000 description 1
- 150000001336 alkenes Chemical class 0.000 description 1
- 229920005549 butyl rubber Polymers 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- FGBJXOREULPLGL-UHFFFAOYSA-N ethyl cyanoacrylate Chemical compound CCOC(=O)C(=C)C#N FGBJXOREULPLGL-UHFFFAOYSA-N 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 239000003779 heat-resistant material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229920003049 isoprene rubber Polymers 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- JRZJOMJEPLMPRA-UHFFFAOYSA-N olefin Natural products CCCCCCCC=C JRZJOMJEPLMPRA-UHFFFAOYSA-N 0.000 description 1
- 229920001084 poly(chloroprene) Polymers 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 229920002857 polybutadiene Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 229920003048 styrene butadiene rubber Polymers 0.000 description 1
- 229920003051 synthetic elastomer Polymers 0.000 description 1
- 239000005061 synthetic rubber Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、半導体素子検査
用治具に関し、特に、半導体素子(半導体パッケージ)
に熱負荷等を加えて行うバーンインテスト等に用いられ
る半導体素子検査用治具に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device inspection jig, and more particularly to a semiconductor device (semiconductor package).
The present invention relates to a jig for inspecting a semiconductor element used for a burn-in test performed by adding a heat load to
【0002】[0002]
【従来の技術】半導体素子の検査工程を大別すると、半
導体素子の機能を評価するファンクションテストと初期
の不良を振るい落とすためのバーンインテストとに分類
することができる。ファンクションテストは、ハンドラ
ーを用い比較的短時間で行うことが可能であり、検査時
間が比較的長いメモリーでも1個を1分程度で検査する
ことができる。これに対して、バーンインテストは信頼
性評価試験で、半導体素子に熱ストレスと電源ストレス
とを長時間(長いものでは48時間)印加して行う。こ
のため、バーンインテストは数百〜数千個の半導体素子
を同時に評価している。2. Description of the Related Art A semiconductor element inspection process can be roughly classified into a function test for evaluating the function of the semiconductor element and a burn-in test for eliminating an initial defect. The function test can be performed in a relatively short time using a handler, and one memory can be inspected in about 1 minute even in a memory having a relatively long inspection time. On the other hand, the burn-in test is a reliability evaluation test, in which heat stress and power source stress are applied to the semiconductor element for a long time (48 hours for a long one). Therefore, the burn-in test evaluates hundreds to thousands of semiconductor devices at the same time.
【0003】従来、バーンインテストに際しては、検査
用治具として複数個のICソケットが実装されたバーン
インボードを用い、各ICソケットに半導体素子が取り
付けられた数枚〜数十枚のバーンインボードをバーンイ
ン装置(外観はオーブン)に装着する。そして、上述し
たファンクションテストに用いるハンドラーでは半導体
素子とICソケットとを電気的に接続するための圧力を
ハンドラー自体で印加することができるが、バーンイン
テストではICソケットにその機能を付加する必要があ
るため蓋付きのICソケットを使用している。Conventionally, in a burn-in test, a burn-in board having a plurality of IC sockets mounted thereon is used as an inspection jig, and several to several tens of burn-in boards each having a semiconductor element attached to each IC socket are burned in. Attach to the device (appearance is oven). In the handler used for the above-described function test, the pressure for electrically connecting the semiconductor element and the IC socket can be applied by the handler itself, but in the burn-in test, it is necessary to add the function to the IC socket. Therefore, an IC socket with a lid is used.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、上述し
た従来のバーンインボードにあっては、ICソケットに
蓋の開閉機構や半導体素子を圧接するための機構を組み
付けなければならずICソケット自体が比較的大きく、
また、このICソケットには1つの半導体素子が実装で
きるに過ぎないため、1つのバーンインボードに実装で
きる半導体素子の数も少なく、バーンインテストの処理
能力を低下させる原因となっているという問題があっ
た。この発明は、上記問題に鑑みてなされたもので、よ
り多くの半導体素子を装着することができる半導体素子
検査用治具を提供し、バーンインテスト等を効率的に行
えるようにすることを目的とする。However, in the above-described conventional burn-in board, the opening / closing mechanism of the lid and the mechanism for press-contacting the semiconductor element have to be assembled to the IC socket, and the IC socket itself is relatively large. big,
In addition, since only one semiconductor element can be mounted on this IC socket, the number of semiconductor elements that can be mounted on one burn-in board is small, which causes a decrease in burn-in test processing capacity. It was The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor element inspection jig capable of mounting a larger number of semiconductor elements and to efficiently perform a burn-in test or the like. To do.
【0005】[0005]
【課題を解決するための手段】上記目的を達成するた
め、この発明にかかる半導体素子検査用治具は、半導体
素子を位置決めして着脱自在に装填可能な複数の装填穴
が表裏を貫通して形成されたフレームの一面側を回路基
板に位置決めして組み付けるとともに、ゴム弾性を有す
る絶縁性のシート体に表裏を貫通する複数の導電ワイヤ
を貫通させて異方導電性シートを構成し、該異方導電性
シートを前記回路基板と前記フレームとの間に前記装填
穴開口に臨ませ、かつ、前記回路基板の電極と当接させ
て設けるとともに、前記フレームの他面側を被蓋可能な
蓋を備え、該蓋に前記装填穴内の半導体素子を前記異方
導電性シートに向けて付勢する押圧部材を設けた。In order to achieve the above object, a semiconductor element inspecting jig according to the present invention has a plurality of loading holes which are capable of positioning a semiconductor element and being detachably loaded through the front and back. The one side of the formed frame is positioned and assembled to the circuit board, and a plurality of conductive wires penetrating the front and back are penetrated through an insulating sheet body having rubber elasticity to form an anisotropic conductive sheet. A lid which is provided between the circuit board and the frame so as to face the loading hole opening and is in contact with an electrode of the circuit board, and which can cover the other surface side of the frame. The lid is provided with a pressing member for urging the semiconductor element in the loading hole toward the anisotropic conductive sheet.
【0006】そして、この発明にかかる半導体素子検査
用治具は、内周部に小さな半導体素子を位置決めして装
填可能な装填穴が形成された枠状のサイズアダプタ部材
を、前記フレームの装填穴に位置決めして装填可能に備
える態様(請求項2)に構成することができる。In the semiconductor element inspection jig according to the present invention, a frame-shaped size adapter member having a loading hole for positioning and loading a small semiconductor element in the inner peripheral portion is provided in the loading hole of the frame. The present invention can be configured in such a manner that it can be positioned and loaded for loading (claim 2).
【0007】[0007]
【作用】請求項1記載の発明にかかる半導体素子検査用
治具によれば、フレームの各装填穴に半導体素子を装填
してフレームを蓋により被蓋することで、半導体素子が
蓋の押圧部材により異方導電性シート側へ押圧され、半
導体素子は端子が異方導電性シートに圧接し異方導電性
シートを介して回路基板の電極と接続する。そして、こ
の発明の半導体素子検査用治具は、複数の装填穴が形成
されたフレームと回路基板との間に異方導電性シートを
介設するとともに、フレームに蓋を設けることで達成さ
れるため、1つの半導体素子の装着に要するスペース
(面積)が少なく、多くの半導体素子を装着でき、バー
ンインテスト等の検査を効率的に行える。According to the semiconductor element inspection jig of the first aspect of the present invention, the semiconductor element is loaded in each of the loading holes of the frame and the frame is covered by the lid, so that the semiconductor element is a pressing member of the lid. Is pressed toward the anisotropic conductive sheet, and the terminal of the semiconductor element is pressed against the anisotropic conductive sheet and connected to the electrode of the circuit board through the anisotropic conductive sheet. The semiconductor element inspection jig of the present invention is achieved by providing an anisotropic conductive sheet between the frame in which a plurality of loading holes are formed and the circuit board, and providing the frame with a lid. Therefore, a space (area) required for mounting one semiconductor element is small, many semiconductor elements can be mounted, and an inspection such as a burn-in test can be efficiently performed.
【0008】また、請求項2記載の発明にかかる半導体
素子検査用治具によれば、フレームの装填穴にサイズア
ダプタ部材を装填し、このサイズアダプタ部材の小装填
穴にサイズの小さな異種の半導体素子を装填でき、この
異種の半導体素子の検査も行えるため、高い汎用性が達
成される。According to the semiconductor element inspecting jig of the second aspect of the present invention, the size adapter member is loaded in the loading hole of the frame, and the small loading hole of the size adapter member is of a different size and different type. High versatility is achieved because elements can be loaded and the inspection of these different types of semiconductor elements can be performed.
【0009】[0009]
【発明の実施の形態】以下、この発明の実施例を図面を
参照して説明する。図1から図4はこの発明の一実施例
にかかるバーンインボード(半導体素子検査用治具)を
示し、図1aが模式断面図、図1bが図1aのA−A矢
視図、図2が異方導電性シートの模式断面図、図3が回
路基板の斜視図、図4が他の半導体素子を装着した状態
の模式断面図である。Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 show a burn-in board (jig for semiconductor device inspection) according to one embodiment of the present invention, FIG. 1a is a schematic sectional view, FIG. 1b is a view taken along the line AA of FIG. 1a, and FIG. FIG. 3 is a schematic cross-sectional view of the anisotropic conductive sheet, FIG. 3 is a perspective view of the circuit board, and FIG. 4 is a schematic cross-sectional view of a state in which another semiconductor element is mounted.
【0010】図1,4において、10はフレームであ
り、フレーム10には、裏面(図中、下面)が回路基板
20に接合され、表面に蓋30が着脱自在に設けられ
る。フレーム10は、セラミック等の耐熱性材料からな
り、表裏を貫通する複数の装填穴11が行列状に整列さ
れて形成され、また、これら装填穴11間の適宜位置に
複数の取付孔12が表裏を貫通して形成される。取付孔
12は回路基板20の後述する取付孔および蓋30の取
付孔と連続し、これら孔12にボルト等の締結部材(図
示せず)が挿通される。In FIGS. 1 and 4, reference numeral 10 denotes a frame. The frame 10 has a rear surface (lower surface in the drawings) joined to the circuit board 20 and a lid 30 removably provided on the front surface. The frame 10 is made of a heat-resistant material such as ceramic, and has a plurality of loading holes 11 penetrating through the front and back arranged in a matrix, and a plurality of mounting holes 12 are provided at appropriate positions between the loading holes 11. Is formed so as to penetrate through. The mounting hole 12 is continuous with a mounting hole of the circuit board 20 described later and a mounting hole of the lid 30, and a fastening member (not shown) such as a bolt is inserted into the hole 12.
【0011】装填穴11は、PLCC等の半導体素子C
の外形より小さな相似形状である角形の平面視形状(断
面形状)を有し、PLCC等の半導体素子Cまたはサイ
ズアダプタ部材50(図4参照)が着脱自在に装着され
る。これら装填穴11は表側開口端の4辺部分にそれぞ
れ中心側へ向かって下向きに傾斜した案内面11aを有
し、これら案内面11aが装填穴11内への半導体素子
C等の装着を案内する。The loading hole 11 has a semiconductor element C such as PLCC.
The semiconductor element C such as PLCC or the size adapter member 50 (see FIG. 4) is detachably mounted and has a rectangular plan view shape (cross-sectional shape) that is a similar shape smaller than the outer shape. Each of the loading holes 11 has a guide surface 11a inclined downward toward the center side on each of four sides of the front opening end, and these guide surfaces 11a guide the mounting of the semiconductor element C or the like into the loading hole 11. .
【0012】また、フレーム10には、各装填穴11の
裏側開口端にざぐり部11bが形成され、各装填穴11
の裏側開口端に異方導電性シート40がざぐり部11b
の段差面と接着剤等により接着されて設けられる。これ
ら異方導電性シート40は、少なくとも一部が装填穴1
1の裏面側開口を閉止して半導体素子Cの端子と当接可
能に配置され、裏面側が回路基板20の後述する電極と
電気的に導通して接触する。Further, in the frame 10, a countersunk portion 11b is formed at the open end of each loading hole 11 on the back side.
The anisotropic conductive sheet 40 is provided at the opening end on the back side of the countersunk portion 11b.
It is provided by being adhered to the stepped surface of (1) with an adhesive or the like. At least a part of these anisotropically conductive sheets 40 is the loading hole 1.
The back side opening of 1 is closed so as to be able to come into contact with the terminals of the semiconductor element C, and the back side electrically contacts with the electrodes of the circuit board 20 to be described later.
【0013】異方導電性シート40は、図2に示すよう
に、ゴム弾性を有する絶縁性材料からなるシート体41
に金細線等の複数の導電性線状体42を所定角度θ傾斜
させて貫通埋設して構成される。導電性線状体42は、
その両端に球状等に拡径する端子部42a,42bがレ
ーザー加工等によって形成され、これら端子部42a,
42bの一部あるいは全部がシート体41表面から突出
する。この導電性線状体42の傾斜角度θは、導電性線
状体41の座屈の防止とシート体41の圧縮変形の容易
化のため5°以上に、また、導電性線状体42の端子部
42a,42bを回路基板20の電極等に適正な接触圧
力で確実に接触させるため60°以下が好ましい。な
お、導電性線状体42は、端部に必ずしも球形の端子部
42a,42bを成形する必要は無く、端子部42a,
42bの成形は任意である。The anisotropic conductive sheet 40, as shown in FIG. 2, is a sheet body 41 made of an insulating material having rubber elasticity.
Is formed by burying a plurality of conductive linear bodies 42 such as gold wires at a predetermined angle θ. The conductive linear body 42 is
Terminal portions 42a and 42b, which are expanded in a spherical shape or the like, are formed on both ends thereof by laser processing or the like.
A part or all of 42b projects from the surface of the sheet body 41. The inclination angle θ of the conductive linear body 42 is 5 ° or more for preventing buckling of the conductive linear body 41 and facilitating compressive deformation of the sheet body 41. It is preferably 60 ° or less in order to surely bring the terminal portions 42a and 42b into contact with the electrodes and the like of the circuit board 20 with an appropriate contact pressure. The conductive linear body 42 does not necessarily need to have the spherical terminal portions 42a and 42b formed at the ends thereof.
The molding of 42b is optional.
【0014】シート体41は、半導体素子Cの支持と弾
性変形とを両立させるためショアA硬度が10°H以上
60°H未満、望ましくは、繰り返しに対する耐久性を
考慮してショアA硬度が20°H以上60°H未満とす
る。このシート体41を構成するゴム様弾性材料として
は、スチレンブタジエンゴム、アクリロニトリルブタジ
エンゴム、ブタジエンゴム、イソプレンゴム、クロロプ
レンゴム、エチレンプロピレンゴム、ブチルゴム、シリ
コーンゴム、フッソゴム、ウレタンゴム、アクリルゴ
ム、スチレン系、オレフィン系、ウレタン系あるいはエ
ステル系等の熱可塑性エラストマから適宜目的に応じて
選択される。The sheet body 41 has a Shore A hardness of not less than 10 ° H and less than 60 ° H in order to achieve both support of the semiconductor element C and elastic deformation. Desirably, the Shore A hardness is 20 in consideration of durability against repetition. The temperature is not less than ° H and less than 60 ° H. Examples of the rubber-like elastic material forming the sheet body 41 include styrene-butadiene rubber, acrylonitrile-butadiene rubber, butadiene rubber, isoprene rubber, chloroprene rubber, ethylene propylene rubber, butyl rubber, silicone rubber, fluorine rubber, urethane rubber, acrylic rubber, and styrene-based rubber. , An olefin-based, urethane-based or ester-based thermoplastic elastomer, which is appropriately selected according to the purpose.
【0015】導電性線状体42は、それぞれが一様に規
則性をもって配列される。この導電性線状体42には導
電性の高いものを適宜用いることができるが、例を挙げ
れば、ニッケル、金、銀、銅、タングステン、銅合金、
スズ合金等の金属細線から選択でき、また、銅や銅合金
の細線であればニッケルめっきを施してニッケルめっき
上に金めっきをさらに施した細線、他の金属細線であれ
ば直接に金めっきを施した細線等を用いることができ
る。そして、上記金めっきを施す場合は高い密着力が得
られる電解めっきが望ましく、また、そのめっき厚さは
導電性の改善とめっき膜の剥離等の防止の両立を図る観
点から0.1μm以上5.0μm以下が望ましい。The conductive linear members 42 are uniformly arranged with regularity. As the conductive linear body 42, one having high conductivity can be appropriately used, and nickel, gold, silver, copper, tungsten, copper alloy,
You can select from thin metal wires such as tin alloy, and if it is thin wire of copper or copper alloy, it is nickel plated and then gold plated on top of nickel plated.Other metal thin wires can be directly gold plated. It is possible to use a thin wire or the like. In the case of applying the gold plating, electrolytic plating is preferable because of high adhesion, and the thickness of the plating is 0.1 μm or more from the viewpoint of improving conductivity and preventing peeling of the plating film. 0.0 μm or less is desirable.
【0016】回路基板20は、周知のエポキシ樹脂等か
ら構成され、フレーム10の下面にフレーム10に突設
された位置決めピン等を用い位置決めして組み付けられ
る。この回路基板20には、表面(図1a中上面)に電
極21がパターン印刷等によって形成され、また、表裏
を貫通して取付孔22が形成される。電極21は、図3
に示すように、フレーム10の各装填穴11と対応した
複数の矩形領域にそれぞれ二重角形状に配置され、各領
域の外側の電極21aが大きなサイズの半導体素子C
(図1)の端子Caに、内側の電極21bが小さなサイ
ズの半導体素子C’(図4)の端子Caと対応する。取
付孔22は、前述したフレーム10の取付孔12と同軸
的に連続し、ボルト等の締結部材が挿通する。なお、図
示および説明は割愛するが、電極21はバーンイン装置
等に装着されるとコネクタ等を介して計測装置等に接続
される。The circuit board 20 is made of a known epoxy resin or the like, and is positioned and assembled on the lower surface of the frame 10 using positioning pins or the like protruding from the frame 10. Electrodes 21 are formed on the surface (upper surface in FIG. 1a) of this circuit board 20 by pattern printing or the like, and mounting holes 22 are formed penetrating the front and back. The electrode 21 is shown in FIG.
As shown in FIG. 6, the semiconductor element C is arranged in a plurality of rectangular areas corresponding to the respective loading holes 11 of the frame 10 in a doubly-angled shape, and the electrodes 21a outside the respective areas are large in size.
The inner electrode 21b corresponds to the terminal Ca of (FIG. 1) and the terminal Ca of the small-sized semiconductor element C ′ (FIG. 4). The mounting hole 22 is coaxially continuous with the mounting hole 12 of the frame 10 described above, and a fastening member such as a bolt is inserted therethrough. Although illustration and description are omitted, when the electrode 21 is attached to a burn-in device or the like, it is connected to a measuring device or the like via a connector or the like.
【0017】蓋30は、セラミック等の耐熱性に優れた
材料の板状部材からなり、複数の取付孔31が表裏を貫
通して形成され、また、裏面(図中下面)に複数の押圧
部材32がフレーム10の装填穴11と対応した位置に
固着される。この蓋30は、各取付孔31,12,22
を貫通したボルトやナットを用いてフレーム10に取外
し自在に固定され、フレーム10の上側を被蓋する。The lid 30 is made of a plate-shaped member made of a material having excellent heat resistance such as ceramics, a plurality of mounting holes 31 are formed through the front and back surfaces, and a plurality of pressing members are provided on the back surface (lower surface in the figure). 32 is fixed to the frame 10 at a position corresponding to the loading hole 11. The lid 30 has mounting holes 31, 12, 22
It is detachably fixed to the frame 10 by using a bolt or a nut that penetrates through, and the upper side of the frame 10 is covered.
【0018】取付孔31は、フレーム10の取付孔12
に対応して形成され、蓋30の被蓋時に取付孔12と連
続する。押圧部材32は、シリコーンゴム等の合成ゴム
や熱可塑性エラストマ等の板状部材からなり、接着剤等
により蓋30の裏面に固着される。この押圧部材32
は、蓋30の被蓋時においてフレーム10の装填穴11
内に装填された半導体素子Cの上面と当接して半導体素
子Cを押圧する。The mounting hole 31 is the mounting hole 12 of the frame 10.
Corresponding to, and is continuous with the mounting hole 12 when the lid 30 is covered. The pressing member 32 is made of a synthetic rubber such as silicone rubber or a plate member such as a thermoplastic elastomer, and is fixed to the back surface of the lid 30 with an adhesive or the like. This pressing member 32
Is the loading hole 11 of the frame 10 when the lid 30 is covered.
The semiconductor element C is pressed against the upper surface of the semiconductor element C loaded therein.
【0019】なお、上述した蓋30は取付孔31等を挿
通するボルト等によりフレーム10に固定されてフレー
ム10の上面を被蓋するが、蓋30の一側部をヒンジ等
により取り付けることも可能である。また、その押圧部
材32もゴム等の板に限らず、コイルスプリングを用い
ることも可能である。The lid 30 described above is fixed to the frame 10 by bolts or the like that pass through the mounting holes 31 and the like to cover the upper surface of the frame 10. However, one side of the lid 30 may be attached by a hinge or the like. Is. The pressing member 32 is not limited to a plate made of rubber or the like, and a coil spring can be used.
【0020】半導体素子C(図4に示す半導体素子C’
も同じ)は、表面実装型のPLCCであり、下部の4辺
部分に複数のJ型の端子Caを有する。ただし、この発
明の半導体素子検査用治具はPLCCに限られるもので
はなくBGAやQFP等の半導体素子にも適用すること
ができるものである。そして、述べるまでもないが、こ
れらBGA等の半導体素子に適用する場合は、その端子
の配列等に応じて上述した回路基板20の電極21のパ
ターンも調整する。Semiconductor element C (semiconductor element C'shown in FIG. 4
Is also a surface mount type PLCC, and has a plurality of J-type terminals Ca on the lower four sides. However, the semiconductor element inspection jig of the present invention is not limited to PLCC, but can be applied to semiconductor elements such as BGA and QFP. And, needless to say, when applied to these semiconductor elements such as BGA, the pattern of the electrodes 21 of the circuit board 20 described above is also adjusted according to the arrangement of the terminals and the like.
【0021】サイズアダプタ部材50は、セラミック等
の耐熱性に優れた材料から平面視四角形の枠状に形成さ
れる。図4に示すように、このサイズアダプタ部材50
は、外周部がフレーム10の装填穴11と相似で該装填
穴11内に着脱自在に装着可能な寸法を有し、内周部に
図1に示す半導体素子Cよりも小さな半導体素子C’を
位置決めして着脱自在に装着可能な四角形状の小装填穴
51が形成される。この小装填穴51もフレーム10の
装填穴11と同様に表側開口端の4辺部分にそれぞれ傾
斜した案内面51aを有する。The size adapter member 50 is made of a material having excellent heat resistance such as ceramics and is formed in a rectangular frame shape in a plan view. As shown in FIG. 4, this size adapter member 50
Has a size such that the outer peripheral portion is similar to the loading hole 11 of the frame 10 and can be removably mounted in the loading hole 11, and a semiconductor element C ′ smaller than the semiconductor element C shown in FIG. A square small loading hole 51 that can be positioned and detachably mounted is formed. Like the loading hole 11 of the frame 10, the small loading hole 51 also has inclined guide surfaces 51a on the four sides of the front opening end.
【0022】この実施例の半導体素子検査用治具にあっ
ては、複数の装填穴11が形成されたフレーム10を用
い、このフレーム10の各装填穴11の裏面側開口にそ
れぞれ異方導電性シート40を固着し、フレーム10の
裏面側に回路基板20を、フレーム10の表側に蓋30
を設けることで達成され、フレーム10に多数の装填穴
11を形成して多数の半導体素子Cを装着できる。した
がって、1つの半導体素子の装着に要するスペース(面
積)が少なく、多くの半導体素子を装着でき、バーンイ
ンテスト等の検査を効率的に行える。In the semiconductor device inspecting jig of this embodiment, a frame 10 having a plurality of loading holes 11 is used, and anisotropic conductivity is provided in the openings on the back side of the loading holes 11 of the frame 10. The sheet 40 is fixed, the circuit board 20 is provided on the back side of the frame 10, and the lid 30 is provided on the front side of the frame 10.
This is achieved by providing a large number of mounting holes 11 in the frame 10 and a large number of semiconductor elements C can be mounted. Therefore, a space (area) required for mounting one semiconductor element is small, many semiconductor elements can be mounted, and inspection such as burn-in test can be efficiently performed.
【0023】そして、バーンインテストを行う場合は、
フレーム10の各装填穴11内にそれぞれ半導体素子C
を装着した後、蓋30をフレーム10の上面に被せて蓋
30の取付孔31、フレーム10の取付孔12および回
路基板20の取付孔22にボルトを挿通し、このボルト
にナットを螺着させてフレーム10に蓋30を固定、す
なわち、フレーム10の上側を被蓋し、この状態でバー
ンイン装置内に装着する。When performing the burn-in test,
A semiconductor element C is provided in each loading hole 11 of the frame 10.
After mounting, the lid 30 is put on the upper surface of the frame 10 and a bolt is inserted through the mounting hole 31 of the lid 30, the mounting hole 12 of the frame 10 and the mounting hole 22 of the circuit board 20, and a nut is screwed to the bolt. The lid 30 is fixed to the frame 10, that is, the upper side of the frame 10 is covered and mounted in this state in the burn-in device.
【0024】ここで、フレーム10の装填穴11内に装
着された半導体素子Cは、図1に示すように、上面が蓋
30の裏面の押圧部材32により押圧されるため、端子
Caが異方導電性シート40に圧接して異方導電性シー
ト40を介し回路基板20の電極21aと接続する。Here, as shown in FIG. 1, the upper surface of the semiconductor element C mounted in the loading hole 11 of the frame 10 is pressed by the pressing member 32 on the back surface of the lid 30, so that the terminal Ca is anisotropic. The conductive sheet 40 is pressed and connected to the electrode 21 a of the circuit board 20 through the anisotropic conductive sheet 40.
【0025】また、より小さな半導体素子C’のバーン
インテストを行う場合は、図4に示すように、フレーム
10の装填穴11にサイズアダプタ部材50を装着し、
このサイズアダプタ部材50の小装填穴51内に半導体
素子C’を装着する。そして、この半導体素子C’は、
前述した大きな半導体素子Cと同様に、端子Caが異方
導電性シート40を介し回路基板20の電極21bと接
続する。したがって、フレーム10等を変えること無く
大きな半導体素子Cと小さな半導体素子C’のテストが
行え、優れた汎用性が得られる。When performing a burn-in test on a smaller semiconductor device C ', a size adapter member 50 is attached to the loading hole 11 of the frame 10 as shown in FIG.
The semiconductor element C ′ is mounted in the small loading hole 51 of the size adapter member 50. And this semiconductor element C'is
Similar to the large semiconductor element C described above, the terminal Ca is connected to the electrode 21b of the circuit board 20 via the anisotropic conductive sheet 40. Therefore, the large semiconductor element C and the small semiconductor element C ′ can be tested without changing the frame 10 and the like, and excellent versatility can be obtained.
【0026】図5および図6はこの発明の他の実施例に
かかるバーンインボードを示す分解斜視図である。な
お、上述した実施例と同一の部分には同一の番号を付し
て説明を割愛する。この実施例にあっては、回路基板2
0は表面にフレーム10の装填穴11と対応した複数の
矩形領域にそれぞれ複数の電極23が対角線で仕切られ
る4群に区画されて形成される。電極23は、各群にお
いて中央が最も長く、両側が短くなるように平行に全体
として山状をなすように複数が配置される。5 and 6 are exploded perspective views showing a burn-in board according to another embodiment of the present invention. The same parts as those in the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, the circuit board 2
0 is formed by dividing a plurality of rectangular electrodes corresponding to the loading holes 11 of the frame 10 into four groups into which a plurality of electrodes 23 are divided by diagonal lines. In each group, a plurality of electrodes 23 are arranged in parallel so that the center is longest and both sides are short, and the electrodes 23 are arranged in a mountain shape as a whole.
【0027】また、フレーム10は、各装填穴11の開
口縁部の4辺部分にそれぞれ合計4枚の異方導電性シー
ト40が1辺部を接着剤等により接着されて設けられ
る。異方導電性シート40は、三角形シート状をなし、
前述した実施例と同様に多数の導電性線状体42がシー
ト体41を斜めに表裏を貫通して構成される。これら異
方導電性シート40は、一面を半導体素子Cの端子Ca
と接触可能に装填穴11の開口に望ませ、他面を回路基
板20の電極23と接触させて配置される。Further, the frame 10 is provided with four anisotropic conductive sheets 40 in total, which are bonded to the four sides of the opening edge of each loading hole 11 by one side. The anisotropic conductive sheet 40 has a triangular sheet shape,
Similar to the above-described embodiment, a large number of conductive linear bodies 42 are formed by obliquely penetrating the sheet body 41 on the front and back sides. These anisotropically conductive sheets 40 have, on one surface, terminals Ca of the semiconductor element C.
It is arranged so that it can be contacted with the opening of the loading hole 11 and the other surface is in contact with the electrode 23 of the circuit board 20.
【0028】そして、前述した実施例と同様に、フレー
ム10の装填穴11は小装填穴51を有するサイズアダ
プタ部材50と半導体素子Cが着脱自在に装着可能な大
きさ(断面積)を有し、サイズアダプタ部材50の小装
填穴51が小さなサイズの半導体素子C’を着脱自在に
位置決めして装填可能な大きさを有する。なお、15は
フレーム10に形成された位置決めピン、25は回路基
板20に形成された位置決め孔であり、フレーム10と
回路基板20が組み付けられた状態でピン15が孔25
に嵌入する。As in the above-described embodiment, the loading hole 11 of the frame 10 has a size (cross-sectional area) in which the size adapter member 50 having the small loading hole 51 and the semiconductor element C can be removably mounted. The small loading hole 51 of the size adapter member 50 has such a size that the small-sized semiconductor element C ′ can be removably positioned and loaded. In addition, 15 is a positioning pin formed in the frame 10, 25 is a positioning hole formed in the circuit board 20, and the pin 15 has a hole 25 when the frame 10 and the circuit board 20 are assembled.
Fit in.
【0029】この実施例にあっても、フレーム10、回
路基板20および異方導電性シート40等の少ない部
品、簡単な構造でバーンインボードが構成されてバーン
インボードを安価に製造することができ、また、サイズ
アダプタ部材50を用いることで大きさの異なる半導体
素子C,C’にも適用でき高い汎用性が得られる。特
に、この実施例は、回路基板20の矩形領域に対角線で
仕切られる4つの三角形部分にそれぞれ長さが異なる複
数の電極23を中央が長く、両端が短くなるように平行
に配置するため、各端子Caが同一の入出力ポートで大
きさが異なる半導体素子C,C’、すなわち、大きさの
みが異なる半導体素子C,C’の検査も同一のバーンイ
ンボードを用いて行うことができる。Also in this embodiment, the burn-in board can be manufactured at a low cost because the burn-in board is constituted by a small number of parts such as the frame 10, the circuit board 20 and the anisotropic conductive sheet 40, and a simple structure. Further, by using the size adapter member 50, it can be applied to semiconductor elements C and C ′ having different sizes, and high versatility can be obtained. In particular, in this embodiment, a plurality of electrodes 23 having different lengths are arranged in parallel in four rectangular portions partitioned by diagonal lines in the rectangular area of the circuit board 20 so that the central portions are long and the both ends are short. The same burn-in board can be used to inspect semiconductor devices C and C ′ having the same terminal Ca and different sizes, that is, semiconductor devices C and C ′ having different sizes.
【0030】なお、上述した各実施例においては、異方
導電性シート40のフレーム10等への取付構造の説明
を省略しているが、本出願人が先に提出した特願平7−
164504号に記載されるような構造等を採用するこ
とができる。すなわち、フレーム10には装填穴11の
開口縁部にざぐり部を形成し、このざぐり部の段差底面
に異方導電性シート40の縁部をアクリル系やシアノア
クリレート系等の接着剤で接着する。そして、ざぐり部
は、段差高さ寸法が異方導電性シート40の厚み以下
(望ましくは、異方導電性シート40の厚みより0.2
mm小さくなるように)、段差底面幅寸法が2mm〜5
mm程度となるように形成される。In each of the above-mentioned embodiments, the description of the mounting structure of the anisotropically conductive sheet 40 to the frame 10 and the like is omitted, but the applicant of the present application filed Japanese Patent Application No. 7-
The structure as described in No. 164504 can be adopted. That is, a counterbore is formed on the opening edge of the loading hole 11 in the frame 10, and the edge of the anisotropic conductive sheet 40 is bonded to the bottom surface of the step of the counterbore with an acrylic or cyanoacrylate adhesive. . The step height of the counterbore portion is equal to or smaller than the thickness of the anisotropic conductive sheet 40 (preferably 0.2 than the thickness of the anisotropic conductive sheet 40.
mm), the bottom width of the step is 2 mm to 5 mm.
It is formed to have a size of about mm.
【0031】また、上述した実施例は、バーンインテス
トへの適用例を例示するが、この発明の半導体素子検査
用治具はバーンインテストに限らずファンクションテス
ト等の種々のテストに用いることが可能である。さら
に、上述した実施例においては蓋に設けた押圧部材とし
て弾性を有するゴムやスプリングを例示するが、異方導
電性シート自体がゴム弾性を有するため、蓋に一体形成
した突起等で押圧部材を構成することも可能である。Further, although the above-mentioned embodiment exemplifies the application to the burn-in test, the semiconductor element inspection jig of the present invention can be used not only for the burn-in test but also for various tests such as a function test. is there. Further, in the above-mentioned embodiment, rubber or spring having elasticity is exemplified as the pressing member provided on the lid, but since the anisotropic conductive sheet itself has rubber elasticity, the pressing member is formed by the protrusions integrally formed on the lid. It is also possible to configure.
【0032】[0032]
【発明の効果】以上説明したように、この発明にかかる
半導体素子検査用治具によれば、複数の装填穴が形成さ
れたフレームの裏面側に異方導電性シートを介装して回
路基板と組み付けるとともに、フレームの表側に押圧部
材が固着された蓋を設け、フレームの装填穴に半導体素
子を装着して被蓋した蓋の押圧部材により押圧し、半導
体素子の端子を異方導電性シートに圧接させて異方導電
性シートを介し回路基板の電極と接続するように構成し
たため、1つの半導体素子の装着に要するスペース(面
積)が少なく、多くの半導体素子を装着でき、バーンイ
ンテスト等の検査を効率的に行える。As described above, according to the semiconductor element inspecting jig of the present invention, the anisotropic conductive sheet is interposed on the back side of the frame in which the plurality of loading holes are formed, and the circuit board is provided. A cover to which a pressing member is fixed is provided on the front side of the frame, and the semiconductor element is mounted in the loading hole of the frame and pressed by the pressing member of the covered lid, and the terminal of the semiconductor element is anisotropically conductive sheet. Since it is configured to be pressed into contact with and connected to the electrodes of the circuit board through the anisotropic conductive sheet, the space (area) required for mounting one semiconductor element is small, and many semiconductor elements can be mounted, and burn-in test, etc. Inspection can be done efficiently.
【0033】また、請求項2記載の発明にかかる半導体
素子検査用治具によれば、フレームの装填穴にサイズア
ダプタ部材を装填し、このサイズアダプタ部材の小装填
穴にサイズの小さな異種の半導体素子を装填できるた
め、フレーム等を代えること無く異種の半導体素子の検
査も行え、高い汎用性が達成される。According to the semiconductor element inspecting jig of the second aspect of the invention, the size adapter member is loaded in the loading hole of the frame, and the small loading hole of the size adapter member is of a different size and different type. Since the elements can be loaded, different semiconductor elements can be inspected without changing the frame and the like, and high versatility is achieved.
【図1】この発明の一実施例にかかる半導体検査用治具
を示し、aが模式断面図、bがaのA−A矢視図であ
る。FIG. 1 shows a semiconductor inspection jig according to an embodiment of the present invention, in which a is a schematic sectional view and b is a view taken along the line AA of a.
【図2】同半導体検査用治具に用いられた異方導電性シ
ートの模式断面図である。FIG. 2 is a schematic cross-sectional view of an anisotropic conductive sheet used in the semiconductor inspection jig.
【図3】同半導体検査用治具に用いられた回路基板の一
部を模式的に示す斜視図である。FIG. 3 is a perspective view schematically showing a part of a circuit board used in the semiconductor inspection jig.
【図4】同半導体検査用治具にサイズの小さな半導体素
子を装着した状態を示す模式断面図である。FIG. 4 is a schematic cross-sectional view showing a state where a small-sized semiconductor element is mounted on the semiconductor inspection jig.
【図5】この発明の他の実施例にかかる半導体検査用治
具の一部を拡大した分解斜視図である。FIG. 5 is an enlarged perspective view of a part of a semiconductor inspection jig according to another embodiment of the present invention.
【図6】同半導体検査用治具にサイズの小さな半導体素
子を装着した状態を示す分解斜視図である。FIG. 6 is an exploded perspective view showing a state in which a small-sized semiconductor element is mounted on the semiconductor inspection jig.
10 フレーム 11 装填穴 12 取付孔 20 回路基板 22 電極 22a 電極 22b 電極 23 電極 30 蓋 32 押圧部材 40 異方導電性シート 50 サイズアダプタ部材 C 半導体素子(半導体パッケージ) C’ 半導体素子(半導体パッケージ) Ca 端子 10 frame 11 loading hole 12 mounting hole 20 circuit board 22 electrode 22a electrode 22b electrode 23 electrode 30 lid 32 pressing member 40 anisotropic conductive sheet 50 size adapter member C semiconductor element (semiconductor package) C'semiconductor element (semiconductor package) Ca Terminal
Claims (2)
数の装填穴が表裏を貫通して形成されたフレームの一面
側を回路基板に位置決めして組み付けるとともに、ゴム
弾性を有する絶縁性のシート体に表裏を貫通する複数の
導電ワイヤを貫通させて異方導電性シートを構成し、該
異方導電性シートを前記回路基板と前記フレームとの間
に前記装填穴開口に臨ませ、かつ、前記回路基板の電極
と当接させて設けるとともに、前記フレームの他面側に
被蓋可能な蓋を備え、該蓋に前記装填穴内の半導体素子
を前記異方導電性シートに向けて付勢する押圧部材を設
けたことを特徴とする半導体素子検査用治具。1. An insulating sheet body having a rubber elasticity while positioning and assembling one side of a frame, which has a plurality of mounting holes for positioning and detaching a semiconductor element and penetrating through the front and back sides, to a circuit board. To form a anisotropic conductive sheet by penetrating a plurality of conductive wires penetrating the front and back sides, the anisotropic conductive sheet is exposed to the loading hole opening between the circuit board and the frame, and A cover that is provided in contact with the electrodes of the circuit board and that can be covered on the other side of the frame, and presses the cover to urge the semiconductor element in the loading hole toward the anisotropic conductive sheet. A jig for inspecting a semiconductor device, which is provided with a member.
可能な装填穴が形成された枠状のサイズアダプタ部材
を、前記フレームの装填穴に位置決めして装填可能に備
える請求項1記載の半導体素子検査用治具。2. A frame-shaped size adapter member having a loading hole for positioning and loading a semiconductor element on the inner periphery thereof is provided so as to be positioned and loaded in the loading hole of the frame. Jig for semiconductor element inspection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7205136A JPH0933606A (en) | 1995-07-20 | 1995-07-20 | Jig for inspection of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7205136A JPH0933606A (en) | 1995-07-20 | 1995-07-20 | Jig for inspection of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0933606A true JPH0933606A (en) | 1997-02-07 |
Family
ID=16502027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7205136A Pending JPH0933606A (en) | 1995-07-20 | 1995-07-20 | Jig for inspection of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0933606A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998007041A1 (en) * | 1996-08-09 | 1998-02-19 | Advantest Corporation | Semiconductor device testing apparatus |
| EP0922964A1 (en) * | 1996-07-02 | 1999-06-16 | Shin-Etsu Polymer Co., Ltd. | Socket for inspection of semiconductor device |
| US6407563B2 (en) | 1999-03-12 | 2002-06-18 | Oki Electric Industry Co, Ltd. | Semiconductor device test apparatus |
| JP2006292727A (en) * | 2005-03-18 | 2006-10-26 | Alps Electric Co Ltd | Semiconductor transfer tray, burn-in board using the same, inspection apparatus for burn-in test, burn-in test method, and semiconductor manufacturing method |
| WO2007010610A1 (en) * | 2005-07-21 | 2007-01-25 | Advantest Corporation | Pusher, pusher unit and semiconductor testing apparatus |
| KR100744152B1 (en) * | 2004-10-21 | 2007-08-01 | 삼성전자주식회사 | Sockets for semiconductor chip package inspection for easy multi test |
| KR101398632B1 (en) * | 2008-01-07 | 2014-05-22 | 삼성전자주식회사 | apparatus for testing semiconductor device package and multi-level pusher used the same |
| JP2018028524A (en) * | 2016-08-19 | 2018-02-22 | 合同会社Pleson | Tray-replaceable burn-in test unit |
-
1995
- 1995-07-20 JP JP7205136A patent/JPH0933606A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0922964A1 (en) * | 1996-07-02 | 1999-06-16 | Shin-Etsu Polymer Co., Ltd. | Socket for inspection of semiconductor device |
| US5975915A (en) * | 1996-07-02 | 1999-11-02 | Shin-Etsu Polymer Co., Ltd. | Socket for inspection of semiconductor device |
| WO1998007041A1 (en) * | 1996-08-09 | 1998-02-19 | Advantest Corporation | Semiconductor device testing apparatus |
| US6320398B1 (en) | 1996-08-09 | 2001-11-20 | Advantest Corporation | Semiconductor device testing apparatus |
| US7262610B2 (en) | 1999-03-12 | 2007-08-28 | Oki Electric Industry Co., Ltd. | Method for manufacturing and testing semiconductor devices on a resin-coated wafer |
| US6879169B2 (en) | 1999-03-12 | 2005-04-12 | Oki Electric Industry Co., Ltd. | Method for manufacturing and batch testing semiconductor devices |
| US6407563B2 (en) | 1999-03-12 | 2002-06-18 | Oki Electric Industry Co, Ltd. | Semiconductor device test apparatus |
| US7639027B2 (en) | 1999-03-12 | 2009-12-29 | Oki Semiconductor Co., Ltd. | Method of testing circuit elements on a semiconductor wafer |
| KR100744152B1 (en) * | 2004-10-21 | 2007-08-01 | 삼성전자주식회사 | Sockets for semiconductor chip package inspection for easy multi test |
| JP2006292727A (en) * | 2005-03-18 | 2006-10-26 | Alps Electric Co Ltd | Semiconductor transfer tray, burn-in board using the same, inspection apparatus for burn-in test, burn-in test method, and semiconductor manufacturing method |
| WO2007010610A1 (en) * | 2005-07-21 | 2007-01-25 | Advantest Corporation | Pusher, pusher unit and semiconductor testing apparatus |
| US7804316B2 (en) | 2005-07-21 | 2010-09-28 | Advantest Corporation | Pusher, pusher unit and semiconductor testing apparatus |
| KR101398632B1 (en) * | 2008-01-07 | 2014-05-22 | 삼성전자주식회사 | apparatus for testing semiconductor device package and multi-level pusher used the same |
| JP2018028524A (en) * | 2016-08-19 | 2018-02-22 | 合同会社Pleson | Tray-replaceable burn-in test unit |
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