JPH0936178A - Integrated circuit package, manufacturing method thereof, and pad layout conversion method - Google Patents

Abstract

(57) [Abstract] [Problem] In packaging integrated circuit chips,
"Array pad type small integrated circuit package" is manufactured by a simple process called thermocompression bonding. In packaging of an integrated circuit chip, there is provided an anisotropic conductive sheet (10) containing conductive particles showing conductivity only in a pressure direction, and an array wiring (14) is provided on one side thereof.
After the device surface 13 of the chip 11 and the surface of the anisotropic conductive sheet 10 on which the array wiring 14 is not formed are temporarily attached (step A), the chip 11 is subjected to thermocompression bonding. The peripheral electrode pad 12 and the array wiring 14 of the anisotropic conductive sheet 10 are electrically connected (step B). Next, a bump 17 is formed on the array electrode pad 16 on the array wiring 14 and a mold resin 18 is formed.
The resin is sealed with (step C).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for an integrated circuit, a method for manufacturing the same, and a method for converting a pad arrangement. In particular, the present invention is a package for an integrated circuit in which the pad arrangement is converted into an array, and it is not necessary to open a through hole, and moreover, an "array pad type chip is formed by a simple process of thermocompression bonding. The present invention relates to a package which can be a package for an integrated circuit having a size close to the above, and a method for manufacturing the same, and particularly relates to a method for converting an electrode pad arrangement in packaging an integrated circuit chip.

[0002]

2. Description of the Related Art As the degree of integration and the number of pins of integrated circuit chips have increased, in the case of packages having electrode terminals on the periphery,
If the electrode terminal pitch is narrowed to reduce the size, the pattern formation of the board becomes complicated and the mounting becomes difficult.

Therefore, in the case of a package having a large number of electrode terminals, a wiring is provided on the wiring board so that the electrode pads are arranged in an array, and a pin grid array (where pins are provided in an array on the bottom surface of the board). A ball grid array (hereinafter abbreviated as "BGA") in which an array of solder balls is provided on the bottom surface of the substrate is often used. By using these methods, the package size can be reduced, and the pitch of the electrode terminals does not have to be narrowed, so that there is an advantage that the mounting can be facilitated.

As shown in FIG. 5, a conventional PGA has electrode pads 53 (electrode pads 53 on the wiring board 50 side connected to the peripheral electrode pads 52 of the chip 51) on the surface of the wiring board 50 made of ceramic or the like. , Wiring is arranged so that it can be converted into an array-shaped electrode pad arrangement, and the wiring board 50 is provided with through holes.
55 is opened, and pins 56 are provided on the bottom face in an array at 2.54 mm intervals. The chip 51 is mounted in the cavity 54, electrically connected to the wiring board 50 by wire bonding, and sealed by the cap 57.

The PGA shown in FIG. 5 is called a "cavity-up type". In this type, the pins 56 can be arranged over the entire bottom surface of the wiring board 50, so that the PGA can be made smaller easily. Although it has an advantage, it has a drawback that heat dissipation is poor.

On the other hand, in the case of the "cavity down type" shown in FIG. 6, the chip 61 is inserted from the bottom side of the wiring board 60.
Since the pins 66 cannot be arranged on the entire bottom surface of the wiring board 60 because of the mounting, the miniaturization cannot be expected as compared with the above-mentioned "cavity-up type", but the structure has excellent heat dissipation. In FIG. 6, 62 is a chip
61 peripheral electrode pads, 63 electrode pads on the wiring board 60 side,
64 is a cavity and 67 is a cap.

By the way, although a material using a TAB tape or a printed wiring board has been conventionally known as a wiring board material, the basic structure thereof is the same as that shown in FIG. 5 or FIG. . The PGA is mounted on the mother board by inserting the pins 56 and 66 into the electrode pads and soldering them, or by using a socket or the like.

Next, a conventional BGA will be described with reference to FIG. 7. This is as shown in FIG. 7, in which a wiring board 70 made of ceramic or the like is provided with an array of electrode pads similar to the conventional PGA. Wiring is provided so as to be converted into an arrangement, a through hole 75 is opened in the wiring board 70, and an array-shaped solder ball 78 is provided on the bottom surface. And the chip 71 is
The structure is such that it is electrically connected to the wiring board 70 by flip chip, wire bonding, TAB, etc., and sealed by a cap 77. In FIG. 7, 72 is a peripheral electrode pad of the chip 71, and 73 is an electrode pad on the wiring board 70 side.

The BGA is mounted on the mother board by the B
The solder ball 78 of the GA and the electrode pad of the mother board are aligned with each other, and the solder ball 78 is melted and connected. Therefore, BGA has the advantages that it can be mounted on a substrate more easily than PGA described above, a high yield can be easily obtained, and cost reduction can be achieved.

[0010]

In the conventional electrode pad layout conversion method, as shown in FIGS. 5 to 7, wiring is also provided outside the area where the chip is mounted on the wiring board (chip area). Therefore, the package size has a drawback that it is larger than the chip size. Also, FIG.
As shown in No. 7, since a large number of through holes have to be opened in the wiring board, the number of working steps becomes complicated, resulting in a problem of increased cost.

In the present situation where high density is demanded, there is a strong demand today for a package size as close to the chip size as possible, and a package for an integrated circuit which has few working steps and can be easily manufactured. The appearance of is strongly demanded.

SUMMARY OF THE INVENTION The present invention has a technical object of providing a package for an integrated circuit which meets the above-mentioned demands, and more specifically, solves the drawbacks and problems of the prior art, and particularly
An integrated circuit with a pad arrangement converted to an array, which does not require opening of a hole and can be made into an "integrated circuit package of a size close to an array pad type chip" by a simple process of thermocompression bonding. It is a technical object to provide a package for use in a package and a method for manufacturing the same. Another object of the present invention is to provide a pad layout conversion method capable of converting a pad layout into an array.

[0013]

As means for converting the arrangement of electrode pads according to the present invention, an anisotropic conductive sheet having a size similar to that of a chip is connected to a peripheral board of the chip on a wiring board side. The electrode pad is wired so that it can be converted into an array-shaped electrode pad arrangement. Further, the anisotropic conductive sheet with wiring is thermocompression bonded to the chip to electrically connect the electrode pad of the chip and the electrode pad on the bottom surface of the anisotropic conductive sheet. Characterize.

That is, the package for an integrated circuit according to the present invention is "a conductive sheet containing conductive particles.
An anisotropic conductive sheet that exhibits conductivity only in the direction in which it is pressed is used, and the electrode pads of the chip are electrically connected to the array wiring provided on the anisotropic conductive sheet surface by thermocompression bonding. A package for an integrated circuit, characterized by being sealed with resin. (Claim 1) is the gist.

Further, the method of manufacturing a package for an integrated circuit according to the present invention is described in "(1) Anisotropic conductive sheet surface containing conductive particles having array wiring provided on the surface and a device surface of a chip. And (2) thermocompression-bonding the anisotropic conductive sheet to electrically connect the electrode pad of the chip and the array wiring of the anisotropic conductive sheet, (3) ) A method of manufacturing a package for an integrated circuit, including a step of filling a mold resin. "(Claim 2).

Further, the pad arrangement conversion method according to the present invention is, "In the method for converting the pad arrangement of an integrated circuit chip, the conductive particle-containing resin sheet is pressed in the direction in which the sheet is pressed. A method for converting a pad arrangement, which comprises converting the pad arrangement into an array by using an anisotropic conductive sheet exhibiting conductivity only in "." (Claim 3). The gist is a structure of an integrated circuit package in which the pad arrangement is converted into an array and a mounting method using the integrated circuit package.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Anisotropic conductive sheet used in the present invention.
This will be described in detail with reference to FIG. FIG. 4 is a diagram showing an example of the anisotropic conductive sheet used in the present invention, (A) is a plan view thereof, and (B) is a of (A).
FIG.

The anisotropic conductive sheet 10 shown in FIG.
Conductive particles 32 with a diameter of about 5-10 μm in a sheet composed of
When the sheet 10 is applied with a certain pressure or more, the sheet 10 is electrically conductive only in the direction in which the pressure is applied in the area where the pressure is applied. As the conductive particles 32, it is possible to use particles made of conductive particles such as Au or those in which a conductive material such as Ni or Au is formed on the surface of a resin ball by vapor deposition or plating. it can.

The anisotropic conductive sheet used in the present invention is also used.
The sheet thickness of 10 is preferably about 50 μm. In the present invention, the sheet 10 is bonded to the chip by thermocompression bonding, but after the bonding, a sheet of about 50 μm is formed.
The thickness of the conductive particles 31 is equal to or smaller than the particle diameter of the conductive particles 31, and as a result, as described above, conductivity is exhibited only in the direction in which pressure is applied. The anisotropic conductive sheet used in the present invention is not limited to the above-mentioned conductive particles (including its material and particle diameter) and the sheet thickness, but "the direction in which pressure is applied". It is possible to appropriately change it as long as it has conductivity only.

[0020]

EXAMPLES Next, the present invention will be specifically described with reference to examples of the present invention, but the present invention is not limited to the following examples and is within the scope of the gist of the present invention. Various changes are possible with.

(Embodiment 1) FIG. 1 shows an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a package for an integrated circuit showing (Example 1). As shown in the figure, the package for an integrated circuit of the first embodiment has an anisotropic conductive sheet 10, a chip 11, a peripheral electrode pad 12 of the chip 11, an array wiring 14, and an array electrode pad 1.
6, consisting of bumps 17 and mold resin 18.

FIG. 2 shows a method of manufacturing the package for the integrated circuit.
It will be described based on. 2A to 2C are cross-sectional views in order of the manufacturing steps including steps A to C of the package for the integrated circuit shown in FIG.

First, the anisotropic conductive sheet 10 having a thickness of about 50 .mu.m shown in FIG. 4 is used, and the anisotropic conductive sheet 10 (FIG. 2 Step A) is prepared. Further, a chip 11 (see step A in FIG. 2) in which the electrode pad 12 is provided only in the peripheral portion is prepared. The electrode pad 12 is made of Ni, by electroless plating or the like.
A bump such as Cu may be provided.

Next, as shown in FIG.
The device surface 13 and the surface of the anisotropic conductive sheet 10 on which the array wiring 14 is not provided are aligned and temporarily attached. continue,
As shown in step B of FIG. 2, heating is performed at about 100 to 150 ° C., and pressure is applied to the entire surface of the anisotropic conductive sheet 10. (Note that this pressure can be applied only to the anisotropic conductive sheet 10 portion corresponding to the peripheral electrode pad 12 of the chip 11.)

By this pressurization, the thickness of the anisotropic conductive sheet 10 was initially about 50 μm, but after adhesion, it contained conductive particles 32 (see FIG. 4 above). The thickness is about the particle size or less. Then, the peripheral electrode pad 12 of the chip 11 and the surface 15 portion of the anisotropic conductive sheet 10 (the peripheral electrode pad 12 of the chip 11 and the array wiring 14 of the anisotropic conductive sheet 10 opposite thereto) are electrically connected. Will be done.

Next, as shown in FIG. 2C, after forming bumps 17 on the array electrode pads 16 provided on the array wiring 14, a mold resin 18 (for example, an epoxy resin having a low coefficient of thermal expansion) is formed. ). Note that bump 17
Can be formed into stud bumps by the ball bump method, or can be formed into solder bumps by solder electroless plating, molten solder dip, or the like.

In the first embodiment, since the arrangement of the electrode pads is converted by using the anisotropic conductive sheet 10 as described above,
It is not necessary to open a through hole as in the case of using a ceramic carrier, and an integrated circuit package of a size close to an array pad type chip can be obtained by a simple process of thermocompression bonding. Therefore, the cost can be reduced.

As an example of the size of the package for an integrated circuit according to the first embodiment, for example, in the case of a 5 mm square chip, the chip thickness is 300 μm and the anisotropic conductive sheet thickness is 5 μm.
m, mold resin wall thickness 50 μm, bump electrode height 10
If it is 0 μm, the package size is 5.1 mm □ and the thickness is about 455 μm.

(Embodiment 2) FIG. 3 shows another embodiment of the present invention.
FIG. 6 is a sectional view of an integrated circuit package showing (Embodiment 2). The package for an integrated circuit according to the second embodiment is shown in FIG.
As shown in FIG. 3, the anisotropic conductive sheet 10, the chip 21, the peripheral electrode pad 22 of the chip 21, the array wiring 24, the array electrode pad 26, the bump 27, and the mold resin 28 In this example, the position is different from that of the first embodiment.

The package for an integrated circuit of the second embodiment can be manufactured by the same method as that of the first embodiment. That is, first, the array wiring 24 is provided on one surface, and the anisotropic conductive sheet 10 provided with the array electrode pads 26 on the opposite surface (opposite surface) is aligned with the device surface of the chip 21 and temporarily attached. However,
In the second embodiment, the array wiring 24 is on the chip 21 side of the anisotropic conductive sheet 10 contrary to the first embodiment.

Next, the temperature is raised to about 100 to 150 ° C., pressure is applied to the array electrode pad 26 portion of the anisotropic conductive sheet 10,
Array wiring 24 on the side of the chip 21 on the anisotropic conductive sheet 10,
The electrical continuity with the array electrode pad 26 provided on the opposite side is ensured, and the peripheral electrode pad 22 of the chip 21 and the corresponding array electrode pad 26 corresponding thereto are electrically conducted. (Note that the pressure may be applied to the entire surface of the anisotropic conductive sheet 10.) Thereafter, the bumps 27 are formed on the array electrode pads 26 in the same manner as in Example 1, and the chip 21 is formed by the mold resin 28.
Coating.

In the second embodiment, the arrangement of the electrode pads is converted by the above method to manufacture the integrated circuit package, and the same effect as that of the first embodiment is produced.

[0033]

As described in detail above, according to the present invention, since the electrode pad arrangement of the chip is converted into the array pad arrangement by using the anisotropic conductive sheet, it is necessary to open the through hole. In addition, a simple process of thermocompression bonding is used to "integrate an integrated circuit package of a size close to an array pad type chip.
The effect that can be said to be "

For example, in the case of a 5 mm square 225-pin chip as an integrated circuit package according to the present invention, the chip thickness is
If the thickness of the anisotropic conductive sheet is 300 μm, the thickness of the anisotropic conductive sheet is 5 μm, the thickness of the molded resin is 50 μm, and the bump electrode height is 100 μm, the package size is 5.1 mm □ and the thickness is about 455 μm. On the other hand, in the case of the conventional technique, the BGA package has a thickness of 25 to 30 mm □ and a thickness of 1 to 2 mm.

Furthermore, MCM (multi-chip module)
In the case where a bare chip is used as a package, the conventional integrated circuit package has a difficulty in quality assurance because the bare chip test technology has not been established on the shipping side. However, the package for an integrated circuit according to the present invention is difficult. In the case of (i), the quality can be assured and the product can be shipped, and there is an effect that it can be used for the MCM as a substitute for the bare chip.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an integrated circuit package showing an embodiment (Embodiment 1) of the present invention.

2A to 2C are steps A to C of the package for the integrated circuit shown in FIG.
Cross-sectional view of manufacturing process consisting of

FIG. 3 is a sectional view of a package for an integrated circuit showing another embodiment (second embodiment) of the present invention.

FIG. 4 is a diagram showing an example of an anisotropic conductive sheet used in the present invention, (A) is a plan view thereof, and (B) is a sectional view taken along the line aa of (A).

FIG. 5 is a sectional view showing a conventional PGA (cavity-up type).

FIG. 6 is a cross-sectional view showing a conventional PGA (cavity down type).

FIG. 7 is a sectional view showing a conventional BGA.

[Explanation of symbols] 10 anisotropic conductive sheet 11, 21 chip 12, 22 electrode pad 13, -device surface 14, 24 array wiring 15, -anisotropic conductive sheet surface 16, 26 array electrode pad 17 , 27 bumps 18, 28 mold resin 31 resin 32 conductive particles 50, 60, 70 wiring board 51, 61, 71 chip 52, 62, 72 chip peripheral electrode pad 53, 63, 73 wiring board side electrode pad 54, 64, -cavity 55,-, 75 through-hole 56, 66, -pin 57, 67, 77 cap-,-, 78 solder ball

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Teruo Kusaka 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation

Claims (3)

[Claims] 1. An electrode pad of a chip by thermocompression bonding, using an anisotropic conductive sheet which is a conductive particle-containing resin sheet and exhibits conductivity only in the direction in which the resin sheet is pressed. A package for an integrated circuit, characterized in that it is electrically connected to the array wiring provided on the anisotropic conductive sheet surface and is resin-sealed. 2. A step of (1) aligning and temporarily attaching a device surface of a chip and an anisotropic conductive sheet surface containing conductive particles, the surface of which is provided with array wiring, and (2) above The method is characterized by including a step of thermocompression-bonding the anisotropic conductive sheet to electrically connect the electrode pad of the chip and the array wiring of the anisotropic conductive sheet, and (3) a step of filling a mold resin. Method for manufacturing package for integrated circuit. 3. A method for converting a pad arrangement of an integrated circuit chip, comprising: an electrically conductive particle-containing resin sheet, which is electrically conductive only in a direction in which the resin sheet is pressed. -A pad arrangement conversion method, characterized in that the pad arrangement is converted into an array using a switch.