JPH0936237A - Verification method in LSI development - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding the method of verifying the circuit function in LSI development, an LSI circuit of a breadboard for hard simulation is created based on the circuit information of the LSI created on EWS or CAD. It is an object of the present invention to provide a verification method for LSI development in which the entire verification work is automatically performed without particularly spending time and cost for creating a peripheral circuit for operating the peripheral circuit. [Configuration] The data of the verification result of the soft simulation is converted into a predetermined format and expanded in the ROM, and the output of the ROM is used as the test data of the LSI circuit of the breadboard for hardware simulation, and the verification result of the hardware is The output is stored in RAM, and the read output is used as test data for soft simulation, and the verification work of the LSI circuit of the breadboard for hard simulation is automatically performed in a closed loop.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for verifying circuit function in LSI development. Conventionally, the circuit function verification work in the LSI development employs a method of performing two verification methods in parallel, that is, software simulation and hardware simulation that have no commonality, but they are related to each other. By that,
It is desired that the turn of the simulation as a whole be shortened and the efficiency of verification be improved, and at the same time that there be no omission of verification and the reliability of verification be high.

[0002]

2. Description of the Related Art The verification work of the circuit function in the development of an LSI requires a hard simulation because the actual operation of the LSI cannot be verified only by the soft simulation. A conventional work flow for executing the soft simulation and the hard simulation in parallel will be described below. The work content of the soft simulation is EWS
(Enginering Work Station) or CAD (Computer Aid)
ed Design) creates test data on the software based on the circuit information created on the ed design), and verifies the logical operation of the circuit model on the software with the test data.
The content of the work of the hard simulation is to focus on the verification of the asynchronous operation of the logic circuit that cannot be verified by software and the verification of the actual operation that changes the operation speed.
Create a breadboard of LSI circuits based on the above circuit information. In addition, a peripheral circuit (input signal generator for the LSI circuit) for operating the LSI circuit is also prepared in the breadboard. Then, the logic operation of the LSI and other operation functions were verified on the breadboard thus created.

[0003]

As described above, this conventional method requires the hard simulation because it is not possible to verify the entire operation of the LSI by only the soft simulation. However, in order to perform a hard simulation, it is necessary to create an LSI circuit based on the circuit information created on the EWS or CAD and a peripheral circuit for operating the LSI circuit in the breadboard. There is a problem in that it takes time and cost to create the breadboard, and verification work also takes time. An object of the present invention is to create an LSI circuit of a breadboard for hard simulation, but it does not particularly take time and cost to create a peripheral circuit for operating the breadboard, and the verification work of the LSI circuit of the hard simulation can be performed. It is to provide a verification method in LSI development that is automatically performed.

[0004]

The method of verification work of LSI development of the present invention for achieving the above object is as follows: (1) Created on EWS or CAD with reference to the principle work flow chart of FIG. Based on the circuit information (FTDL) obtained from the obtained circuit information,
Create an LSI circuit section equivalent to the LSI circuit information in the breadboard. (2) As a peripheral circuit of the LSI circuit section in the breadboard, a ROM as a storage section for storing the result of the verification previously performed on the verification model with the software test data as hardware test data, and the ROM And a RAM as a storage unit for storing the result of the verification by the hardware, which has been output as the test data, as the software test data. (3) The data of the verification result verified by the verification model using the test data of the simulation created on the software is formatted into the data of the ROM. (4) If the test data of the simulation has an expected value (value of the verification result at the time of normal operation), only that expected value is used as another ROM data. (5) The ROM
When the breadboard is operated by reading the data of the above, the data output from the ROM is the LSI of the above (1).
The test data is input to the circuit section. (6) The data of the verification result output from the LSI circuit unit is loaded into the RAM. (7) The RAM data is format-converted and added to the soft simulation test data as an expected value for the verification result during normal operation. (8) To create a breadboard, a speed setting unit that sets an arbitrary read speed is provided by making maximum use of the field programmable gate array FPGA, and the RO driven by its output is used.
Configure to have M.

[0005]

In the present invention, when the expected value which is the value of the verification result at the time of normal operation exists in the test data for soft simulation, the test data and the expected value are
By converting to ROM data, the output data of the ROM is verified as the test data of the LSI circuit in the hardware simulation by the breadboard, and the verification result is written to the RAM and read out to be the test data for the soft simulation. As a result, the work of verifying the LSI circuit using the ROM becomes a closed loop and can be automated, so that special time is not required for the verification work.

In addition, a programmable gate array (FPGA) is used in the field to create the LSI circuit section in the breadboard for hardware simulation and the ROM and RAM as its peripheral circuits. It is possible to reduce the scale of board creation and the time it takes to create it, and it is also possible to have versatility. When the expected value does not exist in the soft simulation test data, the result of the hard simulation can be directly used as the expected value of the soft simulation.

[0007]

2 is a block diagram of a breadboard according to an embodiment of the present invention. As the flow of LSI development, first, EWS
And circuit information created on CAD (eg, Fujitsu's logic language FLDL: Fusitsu Logic Description La
(1) L equivalent to LSI based on
The SI circuit section is created using, for example, a standard IC. Next, the test data (FT
DL: Fusitsu TestData Description Language)
It is converted into a ROM data format (for example, INTEL or MOTOROLA format) by using a conversion program from test data (FTDL) to ROM data, and (2) it is used in the test data generation unit (ROM). When the data read speed from the ROM is different from the required speed, it is divided into different ROMs and used so that the read speed can be set to an arbitrary speed.
(3) Create the speed setting part using (ate Array).

By executing the hard simulation using the output data of the ROM as the test data, (1) the verification result data output from the LSI circuit unit is stored in the RAM of the (4) test data storage unit and the soft simulation is expected. It has ROM data converted to the ROM data format for storing values. (5) Comparison with the output data of the expected value data generator is performed in (6) result comparison unit, closing the verification work of the development LSI. It becomes a loop and automation is realized.

When the result of the hard simulation is used as the expected value of the soft simulation, (5)
Using a data conversion program that converts ROM data stored in advance in the ROM of the expected value data generation unit into test data FTDL, test data for soft simulation with expected values is created.

[0010]

As described above, according to the present invention, an LSI that normally requires verification in both software and hardware
It becomes possible for the verification work of development to use the ROM in which the test data used in the previous soft simulation has been written, in the peripheral circuit as the input signal generation unit required for operating the LSI circuit unit of the hard simulation. . It is also possible to write and read the result of the hard simulation into the RAM and use it as test data for the soft simulation. Furthermore, by effectively using a field-programmable gate array FPGA to create a breadboard for hard simulation,
It has versatility, and it has the effect of reducing the production scale and the production period.

[Brief description of drawings]

FIG. 1 is a basic flowchart of a verification method in LSI development of the present invention.

FIG. 2 is a configuration diagram of a breadboard according to an embodiment of the present invention.

[Explanation of symbols]

(1) is the LSI circuit section in the breadboard for hardware simulation, (2) is the ROM as the test data generation section of the LSI circuit section, and (3) is the read speed of the ROM.
A speed setting unit which is arbitrarily set using A, (4) is a test data storage unit which has a built-in RAM for storing the test results of the LSI circuit unit and stores its output as test data for soft simulation, (5) is An expected value data generator that has a built-in ROM that stores the expected value for the soft simulation test result in advance. (6) is the test data storage unit 4
Is a result comparing section that compares the output of the above-mentioned and the output of the expected value data generating section 5 and outputs the comparison result to the result judging section.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/04 A

Claims (2)

[Claims] 1. Based on circuit information (FTDL) obtained from circuit information created on EWS or CAD, an operation of an LSI circuit unit equivalent to the circuit information of an LSI created in a breadboard for hardware simulation is performed. In the verification method, the verification result data (FTDL) for the verification model based on the test data of the soft simulation based on the circuit information is converted into a predetermined format and prewritten.
An OM, and a RAM that includes read data of the ROM as test data of the LSI circuit unit created for the hard simulation, and a RAM that verifies the operation and writes and reads the verification result data of the LSI circuit unit. The read data of the ROM is converted into a predetermined format to be used as the test data of the soft simulation, so that the operation of verifying the operation of the LSI circuit section created in the breadboard for the hard simulation can be performed by the ROM and the R.
A verification method in LSI development characterized by being automatically executed in a closed loop by AM. 2. A read data from the ROM driven by an output of the speed setting unit, which is provided with a speed setting unit for arbitrarily setting a data reading speed of the ROM by a field programmable gate array (FPGA). 2. The LSI according to claim 1, wherein the test data is used as a test data to verify an actual operation such as an asynchronous operation when an operation speed of an LSI circuit section created in the breadboard as the hardware is different. Verification method in development.