JPH0936242A - Semiconductor integrated circuit device - Google Patents

Abstract

Kind Code: A1 A semiconductor integrated circuit device is provided which has a low threshold voltage logic circuit which operates at a low voltage and is further increased in speed, and which consumes less current during standby. A gate of a low-threshold-voltage field-effect transistor is provided in a semiconductor integrated circuit device in which a circuit including a low-threshold-voltage field-effect transistor and a circuit including a high-threshold-voltage field-effect transistor are connected in series between power lines. The thickness of the insulating film is thinner than the gate insulating film of the high threshold voltage field effect transistor, or the gate length of the low threshold voltage field effect transistor is shorter than the gate length of the high threshold voltage field effect transistor, or the low threshold voltage. The gate insulating film of the field effect transistor is thinner than the gate insulating film of the high threshold voltage field effect transistor, and the gate length of the low threshold voltage field effect transistor is shorter than the gate length of the high threshold voltage field effect transistor. .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including a field effect transistor having a threshold voltage of a level, and particularly a power supply voltage of 2.5 V.
The present invention relates to a semiconductor integrated circuit device including a logic circuit that can operate at a low voltage at high speed and consumes less current during standby.

[0002]

2. Description of the Related Art As a logic circuit capable of operating at high speed even when the power supply voltage is lowered and reducing current consumption during standby, a logic circuit composed of field effect transistors having two threshold voltages of a low threshold value and a high threshold value. Is proposed. This logic circuit is disclosed in, for example, a paper (S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki and
J.Yamada ,: 1V High-Speed Digital Circuit Technolo
gy with 0.5 μm Multi-Threshold CMOS, IEEE ASIC Con
ference, pp.186-189, Sept., 1993.) or a paper published in NTT R & D published by the Telecommunications Association (Yasuyuki Matsutani, Shinichiro Muto, Junzo Yamada, Takakuni Doseki:
0.5μm low voltage full custom LSI design technology, NTT
R & D, 43, No. 3, pp. 273-282,1
994. ), The configuration will be described below with reference to the connection diagram of FIG.

FIG. 1 is connected to one power supply terminal of a low threshold voltage logic circuit (LLC) including logic circuit elements composed of low threshold voltage field effect transistors (Q3, Q4, Q5, Q6). First pseudo power line (VDD
V) and the first pseudo power line and the first power line (VDD)
A first power supply circuit configured by a first field-effect transistor (Q1) having a high threshold voltage connected between the second pseudo voltage control circuit and the second power supply terminal of the low threshold voltage logic circuit. Second power supply constituted by a power supply line (GNDV) and a second field effect transistor (Q2) having a high threshold voltage arranged between the second pseudo power supply line and the second power supply line (GND) It has both or one of the circuits. The low threshold voltage logic circuit (LLC) has a low threshold voltage of the field effect transistor that constitutes it, so that the power supply voltage (voltage between VDD and GND) supplied to the entire circuit is low, and therefore the power supply voltage supplied to the LLC ( VDDV and G
Even if the voltage between NDV) is low, it operates at high speed. During standby, both or one of the field effect transistors (Q1, Q2) is turned off, and the threshold voltage of these transistors is high, so that current consumption is suppressed. Since the gate oxide film of the field effect transistor having a plurality of threshold voltages used in this logic circuit is formed in the same process, it is the same in all field effect transistors. Also,
The gate length of the low-threshold voltage transistor is set to be the same as or larger than the gate length of the high-threshold voltage transistor as a result of the determination that the gate length dependence of the threshold voltage is reduced.
Therefore, the adjustment of the threshold voltage between the high threshold voltage field effect transistor and the low threshold voltage field effect transistor has been performed exclusively by changing the amount of impurities introduced into the well region or the semiconductor substrate by channel doping ion implantation. A conventional method for manufacturing a semiconductor integrated circuit device including the logic circuit of FIG. 1 having low threshold voltage and high threshold voltage field effect transistors will be described below with reference to the drawings.

32 to 40 are structural cross-sectional views for explaining, in the order of steps, a method of manufacturing a conventional semiconductor integrated circuit device including field effect transistors having a low threshold voltage and a high threshold voltage. First, from the surface of the p-type silicon substrate 51, p-well 52 and p
N to be a region where a MOS field effect transistor is formed
Well 53 is formed (FIG. 32). LOCOS for element isolation by selectively oxidizing the substrate surface other than the active region
An oxide film 54 is formed (FIG. 33). After forming the gate oxide film 55, channel dope ion implantation for controlling the threshold voltage is performed. When high-concentration phosphorus-doped polysilicon is used as the gate electrode, the nMOS field-effect transistor is a surface channel type, and the pMOS field-effect transistor is a buried channel type, channel-doped ion implantation for controlling the threshold voltage is boron as an impurity, and acceleration energy is used. As 5
When the keV is constant, the ion implantation amount for the low threshold voltage nMOS field effect transistor can be set to a value smaller than the high threshold voltage nMOS field effect transistor, the high threshold voltage pMOS field effect transistor, and the low threshold voltage pMOS field effect transistor. Therefore, first, the entire surface of the substrate is ion-implanted without a resist mask under the channel doping conditions of the low threshold voltage nMOS field effect transistor with the smallest amount of ion implantation (FIG. 34). Next, a resist pattern 56 for opening only the active region of the high threshold voltage nMOS field effect transistor is formed by a normal photolithography method, and then boron is accelerated with an acceleration energy of 5 keV with an ion implantation amount so as to obtain a desired threshold voltage. Ion implantation (Fig. 3)
5). After removing the resist pattern by dissolving it in a mixed solution of sulfuric acid and hydrogen peroxide solution, a resist pattern 57 is formed which opens only the active region of the high threshold voltage pMOS field effect transistor, and ions are formed so as to have a desired threshold voltage. Boron is ion-implanted at an acceleration energy of 5 keV with an implantation amount (FIG. 36). Similarly, after removing the resist pattern by dissolving it in a mixed solution of sulfuric acid and hydrogen peroxide, the low threshold voltage pMO
A resist pattern 58 that opens only in the active region of the S field effect transistor is formed, and boron is ion-implanted at an acceleration energy of 5 keV with an ion implantation amount that provides a desired threshold voltage (FIG. 37). After the channel doping process is completed, a gate electrode 59 made of high-concentration phosphorus-doped polysilicon is formed, and arsenic or phosphorus is ion-implanted using the resist pattern 60 that opens the active region of the nMOS field effect transistor as a mask. The drain diffusion layer 61 is formed (FIG. 38). Similarly, in the pMOS field effect transistor, boron is ion-implanted using the resist pattern 62 for opening the active region as a mask to form the source / drain diffusion layer 63 (FIG. 39). Further, after the insulating film 64 made of the atmospheric pressure CVD oxide film, the BPSG film or the like is formed on the surface of the substrate, the process of forming the contact hole and the first layer wiring 65 is completed (FIG. 40).

[0005]

A conventional semiconductor integrated circuit device including field effect transistors having the same gate oxide film thickness and a plurality of threshold voltages has a gate oxide film thickness higher than a power supply voltage. It is necessary to secure the reliability of the gate oxide film of the high threshold voltage field effect transistor which constitutes the interface circuit for processing a signal, and in the case of the high threshold voltage field effect transistor, the gate induced drain leakage current ( Gate Induced Drain Lea
kage) and gate insulating film tunnel leakage current without causing leakage current. Therefore, as a low threshold voltage field effect transistor having a high allowable leakage current because only a low power supply voltage is applied, the gate oxide film thickness was unnecessarily large in terms of both reliability and leakage current suppression. . As a result, there is a drawback that the operation speed of the low threshold voltage logic circuit (LLC) is slow.

Further, conventionally, the gate length of a high threshold voltage field effect transistor is reduced by the drain induced barrier reduction (Drain In
The length required to realize a high threshold voltage and a low off-state leakage current without causing a channel leakage current due to duced barrier lowering (channel leakage current due to the reduction of the source-channel barrier due to the influence of the drain electric field). It was set to Moreover, the gate length of the low threshold voltage field effect transistor is the same as or larger than the gate length of the high threshold voltage field effect transistor. As a result, there is a drawback that the operation speed of the low threshold voltage logic circuit (LLC) is slow.

Further, the field effect transistors of low threshold voltage and high threshold voltage have the same gate oxide film thickness and the same gate length, or the low threshold voltage field effect transistor is longer than the high threshold voltage field effect transistor. In this case, in order to separately create two types of threshold voltages for the nMOS field effect transistor and the pMOS field effect transistor, for example, first, ion implantation is performed under the conditions of channel doping for a low threshold voltage nMOS field effect transistor on the entire surface of a wafer without using a resist mask. After implantation, for high threshold voltage nMOS field effect transistor, high threshold voltage pMO
It is necessary to repeat the resist mask formation for channel doping and the ion implantation for the S field effect transistor and the low threshold voltage pMOS field effect transistor, and there is a drawback that the process is complicated.

The present invention has been made in view of the above circumstances, and aims to further increase the speed of a low threshold voltage logic circuit which operates at a low voltage, and to provide a semiconductor integrated circuit device which consumes less current during standby. The purpose is to provide.

[0009]

To achieve the above object, the present invention provides a circuit composed of a field effect transistor having a low threshold voltage and a circuit composed of a field effect transistor having a high threshold voltage in series between power supply lines. In the semiconductor integrated circuit having the configuration, the thickness of the gate insulating film of the low threshold voltage field effect transistor is thinner than the gate insulating film of the high threshold voltage field effect transistor, or the gate length of the low threshold voltage field effect transistor. Is shorter than the gate length of the high threshold voltage field effect transistor, or the thickness of the gate insulating film of the low threshold voltage field effect transistor is thinner than the gate insulating film of the high threshold voltage field effect transistor, The gate length of the field effect transistor must be shorter than that of the high threshold voltage field effect transistor. , The most important feature.

In the conventional structure, the field-effect transistor of low threshold voltage and the field-effect transistor of high-threshold voltage have the same gate oxide film thickness, and the gate length of the field-effect transistor of low-threshold voltage is the same as that of the high-threshold voltage. The gate length of the effect transistor is the same as or different from that of the gate length.

Since the gate oxide film thickness or the gate length of the low threshold voltage field effect transistor is made thinner than the gate oxide film thickness of the high threshold voltage field effect transistor and is made shorter than the gate length of the high threshold voltage field effect transistor. ,
It becomes possible to operate a logic circuit composed of a field effect transistor having a low threshold voltage at a higher speed than before. The standby circuit consumes less current because the logic circuit including the low-threshold voltage field effect transistor and the power supply circuit including the high-threshold voltage field effect transistor are connected in series to the power line. Can be suppressed.

Further, since the threshold voltage of the field effect transistor decreases when the gate oxide film is thinned even if the impurity concentration in the well region and the channel region is the same, the field effect transistor having a thin gate oxide film has a low threshold voltage.
A thick gate oxide field effect transistor can have a high threshold voltage. Therefore, even in a CMOS having a two-level threshold voltage, by setting the gate oxide film thickness to an optimal combination, the channel mask resist mask formation and the ion implantation are performed in the same manner as a CMOS having a normal single-level threshold voltage. Maskless full-face ion implantation and pMO for channel doping of nMOS field effect transistor
Only ion implantation with a mask for S field effect transistor channel doping can be performed. In the process of forming two types of gate oxide films on the same wafer, a resist mask forming step for changing the film thickness is additionally required, but a resist mask forming step for channel dope ion implantation is required. Since the number of resist masks can be reduced, a single subtraction step of forming the resist mask can be omitted, and the steps can be shortened. Further, the threshold voltage of the field effect transistor decreases when the channel is shortened even if the impurity concentration of the well region and the channel region is the same. Therefore, the field effect transistor with a short gate length has a low threshold voltage and the field effect with a long gate length. The transistor can have a high threshold voltage. Therefore, a CMO having a two-level threshold voltage
Even in S, the CMO having a normal single-level threshold voltage is used for the formation of the channel-doped resist mask and the ion implantation by setting the optimum combination of the gate lengths.
Similar to S, it is possible to perform only ion implantation without mask for channel doping of nMOS field effect transistor and ion implantation with mask for channel doping of pMOS field effect transistor. In this case, since a new resist mask forming step for obtaining the two-level threshold voltage is not necessary, the resist mask forming step can be omitted twice as compared with the conventional technique, and the steps can be shortened. become.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 2 to 11 show the embodiments of claims 1 and 2 of the present invention, and these drawings show a method of manufacturing a semiconductor integrated circuit device including field effect transistors of low threshold voltage and high threshold voltage in the order of steps. It is the structure sectional view shown. First, from the surface of the p-type silicon substrate 1, nMO
A p-well 2 which will be a region where an S field effect transistor will be formed and an n-well 3 which will be a region where a pMOS field effect transistor will be formed are formed (FIG. 2). LOC for element isolation by selectively oxidizing the substrate surface other than the active region
The OS oxide film 4 is formed (FIG. 3). A gate oxide film 5 having a film thickness tI is formed in all active regions. However, when the gate oxide film thickness of the high-threshold voltage field effect transistor is tH and the gate oxide film thickness of the low-threshold voltage field effect transistor is tL (tL <tH),
The oxide film having a thickness tI is set to have a thickness tH when additional oxidation is performed under the condition of forming an oxide film having a thickness tL. Then, a resist pattern 6 for opening the active region of the low-threshold voltage field effect transistor is formed by a normal photolithography method (FIG. 4). After etching the gate oxide film 5 formed in the active region of the low threshold voltage field effect transistor with the resist pattern 6 as a mask with a buffered hydrofluoric acid solution, the resist pattern 6 is dissolved with a mixed solution of sulfuric acid and hydrogen peroxide solution. And remove (FIG. 5). Next, when the gate oxide film 7 is formed so that the oxide film thickness becomes tL in the active region of the low threshold voltage field effect transistor where the silicon substrate is exposed, the gate oxide film 8 of the high threshold voltage field effect transistor has a film thickness. Becomes thicker from tI to tH (FIG. 6). High-concentration phosphorus-doped polysilicon is used as the gate electrode, and nM
OS field effect transistor is a surface channel type, pMOS
When the field-effect transistor is a buried channel type, if the channel-doped ion implantation for controlling the threshold voltage is boron as an impurity and the acceleration energy is constant at 5 keV, the amount of ion implantation into the nMOS field-effect transistor is smaller than that of the pMOS field-effect transistor. can do. Therefore, first, the ion implantation amount is small n
Ion implantation is performed on the entire surface of the substrate without a resist mask under the channel doping conditions of the MOS field effect transistor (FIG. 7). Next, a resist pattern 10 for opening the active region of the pMOS field effect transistor is formed by a normal photolithography method, and then channel dope ion implantation of the pMOS field effect transistor is performed (FIG. 8). After depositing the high-concentration phosphorus-doped polysilicon 11, a resist pattern 12 for the gate electrode is formed by a normal photolithography method (FIG. 9). The high-concentration phosphorus-doped polysilicon 11 is etched using the resist pattern 12 as a mask to form a polysilicon gate electrode 13 (FIG. 10). Source / drain diffusion layer 14 and pMOS of nMOS field effect transistor
After forming the source / drain diffusion layer 15 of the field effect transistor, an insulating film 16 made of a normal pressure CVD oxide film, a BPSG film or the like is formed on the surface of the substrate, and a contact hole or a first layer wiring 17 is formed. The manufacturing process ends (FIG. 11). In the above manufacturing process, the number of resist mask forming processes is reduced once compared with the conventional technique, and the process is shortened.

FIG. 12 is a diagram showing electric characteristics of the field effect transistor used in the semiconductor integrated circuit device according to the first and second aspects of the present invention. Generally, the relationship between the absolute value of the threshold voltage of the MOS field effect transistor and the gate oxide film thickness is represented by a linear curve as shown in FIG. 12A, and the threshold voltage decreases as the gate oxide film thickness decreases. The present invention utilizes this tendency to reduce the threshold voltage of the low threshold voltage field effect transistor. By reducing the gate insulating film thickness of the low threshold voltage field effect transistor, the transconductance and the saturation drain current are increased, and the low threshold voltage logic circuit (L
The operating speed of LC) is improved, but in some cases, as shown in FIG.
Gate insulating film tunnel leakage current and gate induced drain leakage current (Gate Induced Drain L
eakage) may increase. The former is one in which a tunnel current or an FN (Fowler-Nordheim) tunnel current flows directly in the gate insulating film, and particularly when the transistor is off (gate-source voltage 0), a leak flows between the drain and gate. It becomes an electric current. In the latter, a band-to-band tunnel occurs at the semiconductor / gate insulating film interface in the drain region overlapping with the gate, and a leak current flows between the drain and the substrate. However, in the logic circuit of FIG. 1, the power supply circuit including the field-effect transistor having a high threshold voltage with a small off-current (leakage current between the source and drain with a gate-source voltage of 0 V) is in the off state during standby, Even if the off current of the low threshold voltage field effect transistor is large, the power supply circuit is connected in series to the LLC, so that the standby current consumption of the entire logic circuit is kept at a small value.

13 to 19 show claims 3 and 4 of the present invention.
FIG. 6 is a structural cross-sectional view showing the embodiment of and a method of manufacturing a semiconductor integrated circuit device including field effect transistors having a low threshold voltage and a high threshold voltage, in the order of steps. First, from the surface of the p-type silicon substrate 1, a p-well 2 serving as a region where an nMOS field effect transistor is formed and an n-well 3 serving as a region where a pMOS field effect transistor is formed are formed (FIG. 13). The surface of the substrate other than the active region is selectively oxidized to form a LOCOS oxide film 4 for element isolation (FIG. 14). After forming the gate oxide film 18, channel dope ion implantation for controlling the threshold voltage is performed. High-concentration phosphorus-doped polysilicon is used as the gate electrode, and nMOS is used.
When the field-effect transistor is a surface channel type and the pMOS field-effect transistor is a buried channel type, assuming that the channel-doped ion implantation for controlling the threshold voltage is boron as an impurity and the acceleration energy is constant at 5 keV,
The ion implantation amount for the nMOS field effect transistor can be set to a value smaller than that for the pMOS field effect transistor. Therefore, first, an nMOS with a small ion implantation amount
Ion implantation is performed on the entire surface of the substrate without a resist mask under the channel doping conditions of the field effect transistor (FIG. 1).
5). Next, a resist pattern 10 for opening the active region of the pMOS field effect transistor is formed by a normal photolithography method, and then channel dope ion implantation of the pMOS field effect transistor is performed (FIG. 16). After depositing the high-concentration phosphorus-doped polysilicon 11, resist patterns 19 and 20 for the gate electrodes are formed by a normal photolithography method (FIG. 1).
7). By setting the gate length of the field effect transistor of low threshold voltage short and the gate length of the field effect transistor of high threshold voltage long at the design stage of the photoetching original plate,
The gate electrode resist pattern 20 of the low threshold voltage field effect transistor is short, and the gate electrode resist pattern 19 of the high threshold voltage field effect transistor is long. The high-concentration phosphorus-doped polysilicon 11 is etched using the resist patterns 19 and 20 as masks to form polysilicon gate electrodes 21 and 22 (FIG. 18). Also at this time,
Corresponding to the length of the resist patterns 19 and 20, the polysilicon gate electrode 22 of the low threshold voltage field effect transistor
Is short (length LL) and the polysilicon gate electrode 21 of the high threshold voltage field effect transistor is long (length LH). Note that LL does not have to be the same for pMOS and nMOS, and LH does not have to be the same for pMOS and nMOS. That is, when comparing field effect transistors (pMOS or nMOS) of the same polarity, the gate length of the low threshold voltage field effect transistor may be short and the gate length of the high threshold voltage field effect transistor may be long. After forming the source / drain diffused layer 14 of the nMOS field effect transistor and the source / drain diffused layer 15 of the pMOS field effect transistor, an insulating film 16 made of a normal pressure CVD oxide film, a BPSG film or the like is formed on the surface of the substrate, and contact is made. The manufacturing process is completed after the process of forming the holes and the first layer wirings 17 (FIG. 19). In the above manufacturing process, the number of resist mask forming processes is reduced twice as compared with the conventional technique, and the process is further shortened as compared with the embodiments of claims 1 and 2.

FIG. 20 is a diagram showing electric characteristics of the field effect transistor used in the semiconductor integrated circuit device according to the third and fourth aspects of the present invention. Generally, the relationship between the absolute value of the threshold voltage of the field effect transistor and the gate length is as shown in FIG. 20A, and the threshold voltage decreases as the gate length decreases. This phenomenon is called the "short channel effect".
The present invention utilizes this tendency to reduce the threshold voltage of the low threshold voltage field effect transistor. By shortening the gate length of the low threshold voltage field effect transistor, the transconductance and the saturated drain current increase, the gate capacitance decreases, and the operating speed of the low threshold voltage logic circuit (LLC) improves. However, in some cases, the drain-induced barrier lowering (Drain Induced Barrier Lowe) as shown in FIG.
channel leakage current due to the ring) may increase. This is a leak current between the source and the drain caused by a decrease in the barrier between the source and the channel due to the influence of the drain electric field, and the slope of the ID-VG characteristic decreases (from S2 when the subthreshold swing coefficient is long channel). As a result, the off-current (source-drain leak current when the gate-source voltage is 0 V) is significantly increased as compared with the case where a simple threshold voltage drop occurs. However, in the logic circuit of FIG. 1, the power supply circuit composed of the field effect transistor having a high threshold voltage with a small off current in the standby state is in the off state, and even if the off current of the low threshold voltage field effect transistor is large, the LLC circuit is turned on. On the other hand, since the power supply circuits are connected in series, the standby current consumption of the entire logic circuit is kept at a small value. Here, the sub-threshold swing coefficient means a VG change necessary for the drain current ID to change by one digit in the region of the gate voltage VG lower than the threshold voltage.

21 to 30 show claims 5 and 6 of the present invention.
FIG. 6 is a structural cross-sectional view showing the embodiment of and a method of manufacturing a semiconductor integrated circuit device including field effect transistors having a low threshold voltage and a high threshold voltage, in the order of steps. First, from the surface of the p-type silicon substrate 1, a p-well 2 serving as a region where an nMOS field effect transistor is formed and an n-well 3 serving as a region where a pMOS field effect transistor is formed are formed (FIG. 21). The substrate surface other than the active region is selectively oxidized to form a LOCOS oxide film 4 for element isolation (FIG. 22). A gate oxide film 5 having a film thickness tI is formed in all active regions. However, when the gate oxide film thickness of the high-threshold voltage field effect transistor is tH and the gate oxide film thickness of the low-threshold voltage field effect transistor is tL (tL <tH), the film thickness tI is an oxide film having a thickness tL. The oxide film having a thickness tI is set to have a thickness tH when additional oxidation is performed under the conditions for forming the film. Subsequently, a resist pattern 6 for opening the active region of the low threshold voltage field effect transistor is formed by a normal photolithography method (FIG. 23). The gate oxide film 5 formed in the active region of the low threshold voltage field effect transistor by using the resist pattern 6 as a mask.
Is etched with a buffered hydrofluoric acid solution, and then the resist pattern 6 is dissolved and removed with a mixed solution of sulfuric acid and hydrogen peroxide solution (FIG. 24). Next, the oxide film thickness in the active region of the low threshold voltage field effect transistor where the silicon substrate is exposed is t
When the gate oxide film 7 is formed so as to be L, the gate oxide film 8 of the high threshold voltage field effect transistor is tI to t.
It becomes thicker in H (Fig. 25). When high-concentration phosphorus-doped polysilicon is used as the gate electrode, the nMOS field-effect transistor is a surface channel type, and the pMOS field-effect transistor is a buried channel type, channel-doped ion implantation for controlling the threshold voltage is boron as an impurity, and acceleration energy is used. Assuming that 5 keV is constant, the amount of ion implantation into the nMOS field effect transistor can be made smaller than that of the pMOS field effect transistor. Therefore, first, the entire surface of the substrate is ion-implanted without a resist mask under the channel doping conditions of the nMOS field effect transistor with a small amount of ion implantation (FIG. 26). Then pMO
After forming a resist pattern 10 for opening the active region of the S field effect transistor by a normal photolithography method, p
Channel dope ion implantation of a MOS field effect transistor is performed (FIG. 27). High concentration phosphorus-doped polysilicon 11
After depositing, resist patterns 19 and 20 of the gate electrode are formed by a normal photo-etching method (FIG. 28). In the design stage of the photoetching original plate, the gate length of the field effect transistor with low threshold voltage is short, and the gate length of the field effect transistor with high threshold voltage is long. The pattern 20 is short, and the gate electrode resist pattern 19 of the high threshold voltage field effect transistor is long. Resist pattern 19, 20
By etching the high-concentration phosphorus-doped polysilicon 11 using the mask as a mask, the polysilicon gate electrodes 21, 2
2 is formed (FIG. 29). Also in this case, the resist pattern 1
Corresponding to the length of 9 and 20, the polysilicon gate electrode 22 of the low threshold voltage field effect transistor is short (length L
L), the polysilicon gate electrode 21 of the high threshold voltage field effect transistor is formed long (length LH). In addition,
LL does not have to be the same for pMOS and nMOS.
H does not have to be the same in pMOS and nMOS. That is, when comparing field effect transistors (pMOS or nMOS) of the same polarity, the gate length of the low threshold voltage field effect transistor may be short and the gate length of the high threshold voltage effect transistor may be long. nM
Source / drain diffusion layer 1 of OS field effect transistor
4 and pMOS field effect transistor source / drain diffusion layer 15 is formed, and then a normal pressure CVD oxide film or B is formed on the substrate surface.
The manufacturing process is completed after the step of forming the insulating film 16 made of a PSG film or the like and forming the contact hole and the first layer wiring 17 (FIG. 30). In the above manufacturing process, the resist mask forming process is reduced once compared to the conventional technique,
The same process shortening as the embodiments of claims 1 and 2 is achieved.

The electrical characteristics of the low threshold voltage field effect transistor used in the semiconductor integrated circuit according to claims 5 and 6 of the present invention are the same as those of the low threshold voltage field effect transistors used in the semiconductor integrated circuits according to claims 1 and 2 and 3 and 4. It also has the characteristics of a voltage field effect transistor. Since the gate oxide film thickness is made thin and the gate length is made short at the same time, the effect of performance improvement due to the size reduction of the MOS field effect transistor is greater than that in the case of claims 1 and 2 or 3 and 4, and a low threshold voltage logic circuit is provided. (L
The operating speed of LC) is greatly improved. On the other hand, regarding the off-current of the low threshold voltage field effect transistor (source-drain leakage current when the gate-source voltage is 0 V), the gate insulating film tunnel leakage current, the gate-induced drain leakage current (Gate Induced Drain Leakage), Drain Induced Barrier Lowering
Although it is possible that a channel leak current due to the noise is superimposed, in the logic circuit of FIG. 1, the power supply circuit including the field effect transistor having a high threshold voltage with a small off current in the standby state is in the off state. Even if the off-state current of the field effect transistor is large, since the power supply circuit is connected in series to the LLC, the standby current consumption of the entire logic circuit is kept at a small value.

In addition to the above-described embodiments, a mode in which the present invention and the present invention are combined is also conceivable. That is, a resist mask forming step and an ion implantation step are added to independently adjust the channel doping amount of low-threshold voltage and high-threshold voltage field effect transistors, and at the same time reduce the gate oxide film thickness of the low-threshold voltage field effect transistor. Alternatively, the gate length of the low threshold voltage field effect transistor may be shortened. In this case, the number of resist mask forming steps and the like increase, and the steps are complicated, but there is an advantage that the degree of freedom in setting the threshold voltage increases.

In addition, the size of the low threshold voltage field effect transistor is generally reduced to reduce the low threshold voltage logic circuit (LL).
In order to improve the operation speed of C), in addition to thinning the gate oxide film thickness of the low threshold voltage field effect transistor and shortening the gate length, the source / drain junction of only the low threshold voltage field effect transistor is made shallow. It is also possible to do. In this case, the short channel effect is suppressed, and even a shorter gate length can be used, so that the operation speed of the LLC can be further improved. It is conceivable that the shallow source / drain junction may increase the junction leakage current in the peripheral region of the source / drain diffusion layer, resulting in an increase in off current as shown in FIG. However, in the logic circuit of FIG. 1, the power supply circuit composed of the field effect transistor having a high threshold voltage with a small off current in the standby state is in the off state, and even if the off current of the low threshold voltage field effect transistor is large, the LLC circuit is turned on. On the other hand, since the power supply circuits are connected in series, the standby current consumption of the entire logic circuit is kept at a small value.

In the above embodiments, the case where the p-type silicon substrate is used has been described, but it goes without saying that the same operation can be performed using the n-type silicon substrate. It goes without saying that the impurities and acceleration energy used for the channel dope ion implantation, the material used for the gate electrode, and the like can be changed within the range that complies with the gist of the present invention.

[0022]

As described above, as compared with the high threshold voltage field effect transistor forming the power supply circuit inserted between the power supply line and the pseudo power supply line, it operates with the current supplied from the pseudo power supply line. By reducing the gate oxide film thickness of the low threshold voltage field effect transistor and shortening the gate length, the operating speed of the low threshold voltage logic circuit is significantly improved while keeping the standby current consumption of the entire logic circuit at a small value. be able to.

[Brief description of drawings]

FIG. 1 is a connection diagram showing a configuration example of a logic circuit in which a semiconductor integrated circuit device of the present invention is used.

FIG. 2 is a process chart for explaining an embodiment of claim 1 and claim 2 of the present invention.

FIG. 3 is a process chart for explaining an embodiment of claim 1 and claim 2 of the present invention.

FIG. 4 is a process chart for explaining an embodiment of claim 1 and claim 2 of the present invention.

FIG. 5 is a process chart for explaining an embodiment of claim 1 and claim 2 of the present invention.

FIG. 6 is a process chart for explaining an embodiment of claim 1 and claim 2 of the present invention.

FIG. 7 is a process chart for explaining an embodiment of claim 1 and claim 2 of the present invention.

FIG. 8 is a process chart for explaining an embodiment of claim 1 and claim 2 of the present invention.

FIG. 9 is a process chart for explaining an embodiment of claim 1 and claim 2 of the present invention.

FIG. 10 is a process chart for explaining the embodiments of claims 1 and 2 of the present invention.

FIG. 11 is a process chart for explaining an embodiment of claim 1 and claim 2 of the present invention.

FIG. 12 is a diagram showing electrical characteristics of a field effect transistor used in the semiconductor integrated circuit device according to claim 1 and claim 2 of the present invention.

FIG. 13 is a process chart for explaining an embodiment of claim 3 and claim 4 of the present invention.

FIG. 14 is a process chart for explaining the embodiments of claims 3 and 4 of the present invention.

FIG. 15 is a process chart for explaining an embodiment of claims 3 and 4 of the present invention.

FIG. 16 is a process chart for explaining the embodiments of claims 3 and 4 of the present invention.

FIG. 17 is a process chart for explaining the embodiments of claims 3 and 4 of the present invention.

FIG. 18 is a process chart for explaining the embodiments of claims 3 and 4 of the present invention.

FIG. 19 is a process chart for explaining the embodiments of claims 3 and 4 of the present invention.

FIG. 20 is a diagram showing electrical characteristics of the field effect transistor used in the semiconductor integrated circuit device according to claims 3 and 4 of the present invention.

FIG. 21 is a process chart for explaining the embodiments of claims 5 and 6 of the present invention.

FIG. 22 is a process chart for explaining the embodiments of claims 5 and 6 of the present invention.

FIG. 23 is a process chart for explaining an embodiment of claims 5 and 6 of the present invention.

FIG. 24 is a process chart for explaining the embodiments of claims 5 and 6 of the present invention.

FIG. 25 is a process chart for explaining an embodiment of claims 5 and 6 of the present invention.

FIG. 26 is a process chart for explaining an embodiment of claims 5 and 6 of the present invention.

FIG. 27 is a process chart for explaining the embodiments of claims 5 and 6 of the present invention.

FIG. 28 is a process drawing for explaining the embodiments of claims 5 and 6 of the present invention.

FIG. 29 is a process drawing for explaining the embodiments of claims 5 and 6 of the present invention.

FIG. 30 is a process drawing for explaining the embodiments of claims 5 and 6 of the present invention.

FIG. 31 is a diagram showing electric characteristics of a field effect transistor obtained according to another embodiment of the present invention.

FIG. 32 is a manufacturing process diagram of a conventional technique.

FIG. 33 is a manufacturing process diagram of a conventional technique.

FIG. 34 is a manufacturing process diagram of a conventional technique.

FIG. 35 is a manufacturing process diagram of a conventional technique.

FIG. 36 is a manufacturing process diagram of a conventional technique.

FIG. 37 is a manufacturing process diagram of a conventional technique.

FIG. 38 is a manufacturing process diagram of a conventional technique.

FIG. 39 is a manufacturing process diagram of a conventional technique.

FIG. 40 is a manufacturing process diagram of a conventional technique.

[Explanation of symbols]

Q1 ... High threshold voltage pMOS field effect transistor Q2 ... High threshold voltage nMOS field effect transistor Q3, Q4 ... Low threshold voltage pMOS field effect transistor Q5, Q6 ... Low threshold voltage nMOS field effect transistor SL, SLB ... Control signal LLC ... Low threshold Voltage logic circuit VDD, GND ... Power supply line VDDV, GNDV ...
Pseudo power line 1, 51 ... P-type silicon substrate 2, 52 ... P-well 3, 53 ... N-well 4, 54 ... LOCOS
Oxide film 5, 7, 8, 18, 55 ... Gate oxide film 6, 10, 12, 19, 20, 56, 57, 58, 6
0, 62 ... Resist pattern 11 ... High concentration phosphorus-doped polysilicon 13, 21, 22, 59 ... Polysilicon gate electrode 14, 61 ... Source of nMOS field effect transistor
Drain diffusion layer 15, 63 ... Source of pMOS field effect transistor
Drain diffusion layer 16, 64 ... Insulating film 17, 65 ... First layer wiring

Claims (6)

[Claims] 1. A semiconductor integrated device having a structure in which a low threshold voltage logic circuit including a low threshold voltage field effect transistor and a high threshold voltage circuit including a high threshold voltage field effect transistor are connected in series between power supply lines. In the circuit device, the thickness of the gate insulating film of the low threshold voltage field effect transistor is smaller than the thickness of the gate insulating film of the high threshold voltage field effect transistor. 2. A low threshold voltage logic circuit including a low threshold voltage field effect transistor, a power supply line pair including first and second power supply lines serving as a power supply source to the low threshold voltage logic circuit, and A power supply circuit for supplying power to the low threshold voltage logic circuit, the power supply circuit including a first pseudo power supply line connected to one power supply terminal of the low threshold voltage logic circuit and the first pseudo power supply line. A first power supply circuit configured by a first field effect transistor having a high threshold voltage connected between a power supply line and a first power supply line, and connected to the other power supply terminal of the low threshold voltage logic circuit. And a second power supply circuit constituted by a second field effect transistor having a high threshold voltage connected between the second pseudo power line and the second pseudo power line. Or a semiconductor composed of either In the AND circuit device, the thickness of the gate insulating film of the low threshold voltage field effect transistor is a semiconductor integrated circuit device, characterized in that less than the thickness of the gate insulating film of the high threshold voltage field effect transistor. 3. A semiconductor integrated circuit having a structure in which a low-threshold voltage logic circuit including a low-threshold voltage field effect transistor and a high-threshold voltage circuit including a high-threshold voltage field-effect transistor are connected in series between power supply lines. In the circuit device, the gate length of the low threshold voltage field effect transistor is shorter than the gate length of the high threshold voltage field effect transistor. 4. A low threshold voltage logic circuit including field effect transistors having a low threshold voltage, a power supply line pair including first and second power supply lines serving as a power supply source for the low threshold voltage logic circuit, and A power supply circuit for supplying power to the low threshold voltage logic circuit, the power supply circuit including a first pseudo power supply line connected to one power supply terminal of the low threshold voltage logic circuit and the first pseudo power supply line. A first power supply circuit configured by a first field effect transistor having a high threshold voltage connected between a power supply line and a first power supply line, and connected to the other power supply terminal of the low threshold voltage logic circuit. And a second power supply circuit constituted by a second field effect transistor having a high threshold voltage connected between the second pseudo power line and the second pseudo power line. Or a semiconductor composed of either In the AND circuit device, a semiconductor integrated circuit device having a gate length of the low threshold voltage field effect transistor is characterized in that the shorter than the gate length of the high threshold voltage field effect transistor. 5. A semiconductor integrated circuit having a structure in which a low threshold voltage logic circuit including a low threshold voltage field effect transistor and a high threshold voltage circuit including a high threshold voltage field effect transistor are connected in series between power supply lines. In the circuit device, the thickness of the gate insulating film of the low threshold voltage field effect transistor is thinner than the thickness of the gate insulating film of the high threshold voltage field effect transistor, and the gate length of the low threshold voltage field effect transistor is A semiconductor integrated circuit device characterized by being shorter than the gate length of the high threshold voltage field effect transistor. 6. A low threshold voltage logic circuit including a field effect transistor having a low threshold voltage, a power supply line pair including first and second power supply lines serving as a power supply source to the low threshold voltage logic circuit, and A power supply circuit for supplying power to the low threshold voltage logic circuit, the power supply circuit including a first pseudo power supply line connected to one power supply terminal of the low threshold voltage logic circuit and the first pseudo power supply line. A first power supply circuit configured by a first field effect transistor having a high threshold voltage connected between a power supply line and a first power supply line, and connected to the other power supply terminal of the low threshold voltage logic circuit. And a second power supply circuit constituted by a second field effect transistor having a high threshold voltage connected between the second pseudo power line and the second pseudo power line. Or a semiconductor composed of either In the integrated circuit device, the thickness of the gate insulating film of the low threshold voltage field effect transistor is smaller than the thickness of the gate insulating film of the high threshold voltage field effect transistor, and the gate length of the low threshold voltage field effect transistor is A semiconductor integrated circuit device characterized by being shorter than the gate length of the high threshold voltage field effect transistor.