JPH0936310A - Semiconductor device - Google Patents

Abstract

(57) An object of the present invention is to provide a semiconductor device having a resistance element that can maintain a stable resistance value without depending on a temperature change. A resistance element is formed by connecting a first resistor 11 and a second resistor 12 having a temperature coefficient of α ₁ = −α ₂ and a resistance value R ₂ of R ₁ = R ₂ in series. By setting the value to 10, the absolute value of the change amount of the resistance value of each resistor depending on the temperature change is made equal. As a result, the resistance value of the resistance element 10, which is the combined resistance of the first resistor 11 and the second resistor 12, is maintained at a constant value without depending on the temperature change.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a resistance element.

[0002]

2. Description of the Related Art In recent years, with higher integration and higher performance of semiconductor devices, not only passive elements such as transistors but also active elements such as resistors have reduced power consumption, reduced design margin, and reduced power consumption. There is a demand for higher precision in terms of adjustment and the like. FIG. 9A shows a plan view of a main part of a semiconductor device having a resistance element, and FIG. 9B shows a sectional view taken along the line AA '.

As shown in these figures, the resistance element 9 provided in the semiconductor device is formed by diffusing an impurity 90a in a polysilicon film 93 formed on a substrate 91 via a silicon oxide film 92, for example. The resistor 90 is used. For example, when it is desired to form a P-type resistor 90 having a sheet resistance value ρs = 2 kΩ / □, B is formed on the polysilicon film 93.
F ₂ was introduced at an injection energy of 30 keV by 4.5 × 10 ¹⁴ pieces / cm ² , and this polysilicon film 93 was etched to have a predetermined resistance width W and resistance length L. Used as. The resistor 90 has a predetermined resistance value based on the resistance width W, the resistance length L, and the sheet resistance value ρs. When the resistor 90 is incorporated in a semiconductor device, the resistor 90 is covered with an insulating film 94, and contact holes 95 reaching the resistor 90 are formed in the insulating film 94 at both ends of the resistor 90. Then, two terminal wirings 96 are formed with the contact holes 95 filled.

[0004]

However, the semiconductor device having the above resistance element has the following problems. That is, in the resistor formed by diffusing impurities in the polysilicon film as described above, the number of carriers and the mobility of carriers greatly change with temperature. For example,
The temperature coefficient of the polysilicon resistance set to about the sheet resistance ρs = 2 kΩ / □ is about −1300 ppm / ° C., and the operation compensation temperature range of a general semiconductor device is −20 ° C.
~ 70 ° C. From this, in the above temperature range, the resistance value of the resistance element formed of the above resistor fluctuates within a range of about ± 6%.

When the resistance value of the resistance element varies as described above, not only the accuracy of the semiconductor device varies but also the power consumption of the semiconductor device varies, and as a result, the power consumption of the semiconductor device increases. Therefore, a circuit for correcting the variation of the resistance element due to temperature change may be incorporated in the semiconductor device separately from the resistance element. However, this increases the number of elements of the semiconductor device and becomes a factor that hinders high integration of the semiconductor device.

Therefore, an object of the semiconductor device of the present invention is to provide a semiconductor device having a resistance element which can maintain a constant resistance value independent of temperature change.

[0007]

A semiconductor device according to claim 1 of the present invention for solving the above-mentioned problems is arranged or connected to the first resistor in a state of being bonded to the first resistor. And a resistance element including a second resistor. The second resistor has a resistance value at the same temperature substantially equal to that of the first resistor, a temperature coefficient sign opposite to that of the first resistor, and an absolute temperature coefficient absolute value of the first resistor. It is characterized by being almost equal to.

Since the above semiconductor device is provided with the resistance element including the first resistance body and the second resistance body which is arranged in a state of being bonded to the first resistance body or connected to the first resistance body, the resistance element is concerned. Is a combined resistance of the resistance value of the first resistor and the resistance value of the second resistor. The first resistor and the second resistor have substantially the same resistance value at the same temperature, opposite temperature coefficient signs, and substantially the same absolute value of the temperature coefficient. And the resistance value changes by the same amount in the opposite direction to the second resistor. Therefore, the resistance values of the first resistor and the second resistor compensate for the changes in their respective resistance values and cancel out the changes in their respective resistance values. Therefore, the change in the combined resistance due to the temperature change becomes almost zero.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1 (1) to 1 (3) are views showing the main part of the semiconductor device of the first embodiment. First, these figures and the graph showing the relationship between the temperature coefficient and the sheet resistance value of FIG. 2 are used. The semiconductor device of the first embodiment will be described. FIG.
1A is a plan view of a main part of a semiconductor device, FIG. 1B is a sectional view taken along the line AA ′ of the plan view, and FIG. 1C is a sectional view taken along the line BB ′ of the plan view.

As shown in the figure, this semiconductor device is
A resistance element 1 including a resistor 11 and a second resistor 12
It is equipped with 0. One end of the first resistor 11 and the second
Is connected to one end of the resistor 12 by a connection wiring 13,
The terminal wires 14 and 15 are connected to the other end of the resistor 11 and the other end of the second resistor 12, respectively.
The first resistor 11 and the second resistor 12 are in a state of being connected in series.

The first resistor 11 is, for example, a substrate 21.
Of the diffusion layer formed by introducing the first impurity 11a into the surface layer of (1) and having an effective resistance length of L ₁ and a resistance width of W ₁ . here,
The effective resistance length L ₁ is, for example, a length between contact holes formed so as to reach both ends of the first resistor 11. The first resistor 11 has the first impurity 11a.
Depending on the type and the introduction amount, the temperature coefficient is α ₁ , the temperature t ₀
The sheet resistance at is set to ρs ₀₁ ,
From the resistance length L ₁ , the resistance width W ₁ and the sheet resistance ρs ₀₁ , the resistance value at the temperature t ₀ becomes R ₀₁ .

Here, for example, the first resistor 11 is used.
Is the first impurity 11a on the substrate 21 made of silicon.
5 × 1 with boron ion implantation energy of 35 keV
0¹³Pieces / cm^TwoAnnealing is performed after ion implantation
In this way, the first impurities 11a are activated.
It shall consist of a diffusion layer. First formed in this way
The resistor 11 is a point a on the graph A in FIG.₁As shown
And the temperature coefficient α₁= 1300ppm, t₀At 25 ° C
Sheet resistance ρs₀₁= 600Ω / □, t ₀℃
Resistance value at₀₁= 600Ω / □ × L₁/ W₁Each
Will have anti-properties.

The second resistor 12 is, for example, the substrate 2
1 is arranged on the first layer 1 with a silicon oxide film 22 interposed therebetween. The second resistor 12 is formed by introducing the second impurity 12a into the polysilicon film 23, for example, and has an effective resistance length of L ₂ and a resistance width of W ₂ . The temperature coefficient of the second resistor 12 is set to α ₂ = −α ₁ , the sheet resistance value at the temperature t ₀ is set to ρs ₀₂ , and the temperature t _{0 is} further set according to the type and the introduction amount of the second impurity 12a.
The resistance value at is R ₀₂ = R ₀₁ .

Here, for example, the second resistor 12 is used.
Is the second impurity 1 in the 150 nm-thickness polysilicon film 23.
After the boron difluoride ions of 2a are implanted at 4.5 × 10 ¹⁴ ions / cm ² with an implantation energy of 30 keV, an annealing process is performed to obtain the second impurity 1 described above.
2a is activated. The second resistor 12 thus formed has a temperature coefficient α ₂ = -1300 ppm and a temperature t ₀ , as indicated by a point b ₁ in the graph B of FIG.
The sheet resistance value at is ρs ₀₂ = 2 kΩ / □. Further, for example, here, due to layout problems, it is assumed that the effective resistance length of the second resistor 12 is set to L ₂ = L ₁ , and the resistance width is W ₂ = (ρs ₀₂ / ρs ₀₁ ) × By setting W ₁ , R ₀₂ = ρs ₀₂ × L ₂ / W ₂ = R ₀₁ is set.

The first resistor 11 and the second resistor 12 are covered with an insulating film 24. Then, a contact hole 25 reaching the first resistor 11 and a contact hole 26 reaching the second resistor 12 are formed in the insulating film 24 and the silicon oxide film 22. With the contact holes 25 and 26 buried, the connection wiring 1
3 and terminal wirings 14 and 15 are formed.

In the resistance element 10 having the above structure, the resistance value R of the resistance element 10 becomes a combined resistance when the first resistance body 11 and the second resistance body 12 are connected in series. here,
The first resistor 11 and the second resistor 12 have the same temperature t.
_{At 0} , the resistance value R ₀₁ = R ₀₂ and the temperature coefficient α ₁
= -Α ₂ . From this, it is
Value R ₁ of the resistor 11 and the resistance R of the second resistor 12
It changes by the same amount in the opposite direction to ₂ . Therefore, the combined resistance of the first resistor 11 and the second resistor 12 connected in series is maintained at a constant value regardless of the temperature change.

Therefore, in the semiconductor device having the resistance element 10, it is possible to improve the accuracy of the semiconductor device without providing a circuit for compensating the change in the resistance value due to the temperature change, and the consumption can be improved. It is possible to suppress variations in power and reduce power consumption. And
High integration of the semiconductor device can be achieved.

3 (1) to 3 (5) show a method of manufacturing the semiconductor device. An example of the method for manufacturing the semiconductor device will be described below with reference to these drawings. First, FIG.
In the first step of (1), using the resist pattern (not shown) formed on the substrate 21 as a mask, the ion implantation for forming the first resistor (11) is performed,
The first impurity 11a is formed on the surface layer of the substrate 21 made of silicon.
Is introduced. Here, the resist pattern is formed such that the effective resistance length of the first resistor (11) is L ₁ and the resistance width thereof is W ₁ .

Next, in a second step shown in FIG. 3 (2), a CVD (Chemical Vapor D) in which the film forming temperature is set to 400.degree.
The silicon oxide film 22 is formed on the upper surface of the substrate 21 to a thickness of 150 to 300 nm by an eposition method. Then, by the CVD method in which the film forming temperature is set to 650 ° C.
On the upper surface of the silicon oxide film 22, a polysilicon film 23 to be the second resistor (12) is formed with a film thickness of 150 nm.
Then, the second resistor (1
2) ion implantation is performed to form the second impurity 1
2a is introduced into the polysilicon film 23.

Next, the effective resistance length of the second resistor (12) becomes L ₂ = L ₁ , and the resistance width becomes W ₂ = (ρs ₀₂ / ρ
The polysilicon film 23 is etched so that s ₀₁ ) × W ₁ . Here, for example, anisotropic etching is performed using SF ₆ (sulfur hexafluoride) and C ₂ Cl ₃ F ₃ (trichlorotrifluoroethane) gas as reaction gases.

After etching the polysilicon film 23 as described above, in a third step shown in FIG. 3C, an insulating film 24 having a thickness of 300 nm is formed on the silicon oxide film 22 so as to cover the polysilicon film 23. Form a thick film. The interlayer insulating film 24 is made of, for example, silicon oxide. After that, an annealing treatment is performed at 1000 ° C. for 30 minutes to activate the first impurities 11a and the second impurities 12a, whereby the first resistor 1 made of the diffusion layer in the substrate 21 is formed.
1 and the second resistor 12 made of the polysilicon film 23 are formed. These first resistor 11 and second resistor 1
2 has the above-mentioned resistance characteristics.

Next, in a fourth step shown in FIG. 3D, the first resistor 11 is formed on the silicon oxide film 22 and the insulating film 24.
Hole 25 reaching the upper surface of the second resistor 1 and the second resistor 1
2 and a contact hole 26 reaching the upper surface of 2.
These contact holes 25 and 26 are formed at both ends of the first resistor 11 and the second resistor 12, respectively. Note that only one end side is shown here.

Next, in a fifth step shown in FIG. 3 (5), the insulating film 2 is filled with the contact holes 25 and 26.
1 (1), and a connection wiring 13 for connecting one end of the first resistor 11 and one end of the second resistor 12 by patterning this conductive layer And the terminal wirings (14, 15) are formed. As described above, the resistance element 10 is formed by connecting the first resistor 11 and the second resistor 12 in series.

In the first embodiment described above, a resistance element formed by connecting two resistors in series has been described as an example. However, the resistance element provided in the semiconductor device of the present invention is similar to that shown in FIG.
A plurality of resistors may be connected in parallel as shown in (1) to (3). The configuration of the semiconductor device according to the second embodiment will be described below with reference to these drawings. 4 (1) is a plan view of a main part of the semiconductor device, FIG. 4 (2) is a sectional view taken along the line AA ′ of the plan view, and FIG. 4 (3) is a sectional view taken along the line BB ′ of the plan view.
It is sectional drawing.

As shown in the figure, this semiconductor device is
The resistor element 40 including the resistor 41, the second resistor 42, and the third resistor 43 is provided. One ends of the first resistor 41, the second resistor 42, and the third resistor 43 are connected to each other by a terminal wiring 44, and the first resistor 41, the second resistor 42, and the third resistor The other end of 43 is terminal wiring 4
5 is connected. By connecting the first resistor 41, the second resistor 42, and the third resistor 43 in this manner, the first resistor 41, the second resistor 42, and the third resistor 43 are connected to each other. They are connected in parallel.

The above-mentioned first resistor 41 and second resistor 4
Reference numeral 2 is a diffusion layer similar to the first resistor of the first embodiment, and has an effective resistance length of L, for example.
₁ , L ₂ and resistance widths W ₁ and W ₂ . The first resistor 41 and the second resistor 42 differ in sheet resistance at temperature coefficients α ₁ , α ₂ and temperature t ₀ , for example, depending on the types and introduction amounts of the first impurities 41a and the second impurities 42a. Is set to ρs ₀₁ and ρs ₀₂ .

Here, for example, the first resistor 41 and
And the second resistor 42 are formed on the substrate 21 made of silicon.
Through the silicon oxide film 22 having a thickness of 50 nm, the first impurity
25a of boron ions as 41a and second impurities 42a.
5 × 10 with an injection energy of keV¹³Pieces / cm^Twoion
After the implantation, annealing treatment is performed to
The impurity 41a and the second impurity 42a are activated.
It shall consist of a diffusion layer. First formed in this way
The resistor 41 and the second resistor 42 of the first embodiment are the same as those of the first embodiment.
Like the first resistor of, the temperature coefficient α₁= Α_Two= 1300
ppm, temperature t ₀= Sheet resistance value ρs at 25 ° C₀₁
= Ρs₀₂= 600Ω / □, temperature t₀Resistance value at₀₁
= R₀₂= 600Ω / □ × L₁/ W₁Each resistance characteristic of
Become something.

The third resistor 43 is, for example, a base.
It is arranged on the plate 21 through the silicon oxide film 22.
You. The third resistor 43 is, for example, the polysilicon film 2
3 has the third impurity 43a introduced, and is effective.
Resistance length is L_Three, Resistance width is W _ThreeWas formed in
You. This third resistor 43 is of the type of the third impurity 43a.
And the amount introduced, the temperature coefficient is α_Three= -Α₁= −
α_Two, Temperature t₀Sheet resistance at ρs₀₃Set to
And the temperature t₀Resistance value at₀₃Is the temperature t₀In
The combined resistance of the first resistor 41 and the second resistor 42
Value R₀₁₀₂Is almost equal to.

Here, for example, the third resistor 43 is used.
Is the third impurity 4 in the 650 nm-thickness polysilicon film 23.
As 3a, boron ions are implanted at an implantation energy of 25 keV at 5 × 10 ¹³ ions / cm ² and then an annealing process is performed to activate the third impurities 43a to form a diffusion layer. The second resistor 42 thus formed has a temperature coefficient α ₃ = -1300p.
sheet resistance value at pm and temperature t ₀ ρs ₀₃ = 2 kΩ /
Become □. Further, for example, the effective resistance length of the _third resistor 43 is L ₃ = L ₁ = L here due to layout problems.
₂ and set the resistance width to W ₃ = ρs ₀₃ ×
By setting (W ₁ / ρs ₀₁ + W ₂ / ρs ₀₂ ), R ₀₃ =
It is set so that ρs ₀₃ × L ₃ / W ₃ = R ₀₁₀₂ .

In the resistance element 40 having the above structure, the resistance value R of the resistance element 40 becomes a combined resistance of the first resistance body 41, the second resistance body 42 and the third resistance body 43. here,
Temperature coefficient α _{1 of} the first resistor 41 and the second resistor 42
= Α ₂ , the temperature coefficient of the third resistor 43 α ₃ = −α
₁ = −α ₂ and the combined resistance value and resistance value of the resistors are R ₀₁₀₂ = R ₀₃ at the same temperature t ₀ . Therefore, the amount of change in the combined resistance value of the first resistor 41 and the second resistor 42 and the amount of change in the resistance value of the third resistor 43 due to the temperature change are similar in the opposite direction. Only changes.
Therefore, the amount of change in each resistance value is offset, and it is possible to suppress the change in resistance value of the resistance element 40 due to temperature change.

Therefore, similarly to the first embodiment, the semiconductor device having the resistance element 40 does not need to be provided with a circuit for compensating for the change in the resistance value due to the temperature change, and the semiconductor device can be highly integrated. Planned.

5 (1) to 5 (5) show a method of manufacturing the above semiconductor device. First, in the first step shown in FIG. 5A, a silicon oxide film 22 is formed on the upper surface of the substrate 21 to a thickness of 50 nm by the CVD method. Then 650 ℃
Then, a polysilicon film 23 having a film thickness of 150 nm is formed on the upper surface of the silicon oxide film 22 by the above CVD method. next,
The polysilicon film 23 is etched into the shape of the third resistor (43) which will be formed in a later step.

Next, in a second step shown in FIG. 5B, a resist pattern 51 is formed on the silicon oxide film 22. The resist pattern 51 is formed in a state where the silicon oxide film 22 is exposed with a predetermined width on both sides of the etched polysilicon film 23 as a center. Then, the third impurity 43a is formed in the polysilicon film 23 by ion implantation using the resist pattern 51 as a mask.
While introducing the first impurity 41 on the front surface side of the substrate 21.
The third impurity 43a is introduced as a and the second impurity 42a.

Next, in a third step shown in FIG. 5C, after removing the resist pattern (51), the third resistor 4 is removed.
The insulating film 24 is formed on the silicon oxide film 22 so as to cover the film 3.
The film is formed with a film thickness of 00 nm. The insulating film 24 is made of silicon oxide. After that, annealing treatment is performed at 1000 ° C. for 30 minutes to activate the first impurity 41a, the second impurity 42a, and the third impurity 43a, and thereby the first resistor 41, the second resistor, and the third resistor 43a. The resistor 43 is formed.

Next, in a fourth step shown in FIG. 5 (4), reactive ion etching (Reactive Ion Etching) using a resist pattern not shown here as a mask is performed.
(Hereinafter referred to as RIE), the first to third resistors 41 to 4
A contact hole 27 is formed in the insulating film 24 and the silicon oxide film 22 so that 3 is exposed on the bottom surface. The contact holes 27 are formed at both ends of the first to third resistors 41 to 43. Further, here, the side wall of the insulating film 24 is left on the side wall of the first resistor 41 to ensure the coverage of the terminal wiring (44) formed in the next step. Incidentally, here, only the contact hole 27 on one end side is shown.

Next, in a fifth step shown in FIG. 5 (5), a conductive layer is formed on the insulating film 24 in a state of filling the contact hole 27, and the conductive layer is patterned to form the first to the first layers.
Terminal wiring 44 in a state of connecting the third resistors 41 to 43
To form

As described above, the resistance element 40 is formed by connecting the first resistor 41, the second resistor 42, and the third resistor 43 in parallel. When the resistance element 40 is formed as described above, the third resistor 43 is formed in the same step as the formation of the gate electrode of the MOS transistor, and M
The first resistor 41 and the second resistor 4 are formed in the same step as the formation of the source diffusion layer and the drain diffusion layer of the OS transistor.
2 can be formed. Therefore, in the manufacturing process of the MOS transistor, the resistance element 40 can be formed on the same substrate as the MOS transistor without increasing the mask process.

If the temperature coefficients α _{1 to} α ₃ of the resistors 41 to 43 cannot be adjusted to the predetermined values only by the ion implantation in the second step, the polysilicon film 23 is removed in the first step. Before etching the polysilicon film 2
The second impurity 71a is introduced only in 3 so that the predetermined temperature coefficients α _{1 to} α ₃ can be obtained in the resistors 41 to 43 together with the impurities introduced by the ion implantation in the second step. May be.

Next, FIGS. 6A to 6C are views showing the main part of the semiconductor device of the third embodiment. These figures and FIG.
The semiconductor device of the third embodiment will be described with reference to the graph showing the relationship between the temperature coefficient and the sheet resistance value. Incidentally, FIG.
6A is a sectional view taken along the line AA ′ of the plan view, and FIG. 6C is a sectional view taken along the line BB ′ of the plan view.

As shown in the figure, the semiconductor device of the third embodiment comprises a first resistor 61 and a second resistor 62 which are formed by introducing different impurities into the resistance patterns formed in the same layer. The resistance element 60 is formed as follows. Here, for example, a first resistor 61 formed by introducing a first impurity 61a into a resistance pattern made of a polysilicon film 23 formed on a substrate 21 via a silicon oxide film 22 and a second resistance pattern having the same resistance pattern are used. The second resistor 62 is formed by introducing the impurities 62a. Then, one end of the first resistor 61 and one end of the second resistor 62 are connected to each other by the connection wiring 63.
Connected by the other end of the first resistor 61 and the second resistor 6
Terminal wirings 64 and 65 are connected to the other end of 2, respectively. As a result, the first resistor 61 and the second resistor 62 are connected in series.

The first resistor 61 has an effective resistance length of L ₁ and a resistance width of W ₁ . The first resistor 61 is by the type and the introduction amount of the first impurity 61a, ₁ temperature coefficient alpha, are those sheet resistance at temperature t ₀ is set to .rho.s _01, the resistor length L _1,
Based on the resistance width W ₁ and the sheet resistance ρs ₀₁ , the resistance value at the temperature t ₀ becomes R ₀₁ .

Here, for example, the first resistor 61 is used.
Is the first impurity in the polysilicon film 23 having a thickness of 150 nm.
Arsenic ion implantation energy of 40 keV as 61a
1 x 10¹⁶Pieces / cm^TwoAfter ion implantation, annealing treatment
The first impurity 61a is activated by performing
Let's make it. The first resistor thus formed
The body 61 is a point c on the graph C.₁As shown in, temperature coefficient
α₁= 700ppm, t ₀= Sheet resistance at 25 ℃
Value ρs₀₁= 250Ω / □, t₀Resistance R at ℃₀₁=
250Ω / □ × L₁/ W₁Of each resistance characteristic of
Become.

The second resistor 62 has an effective resistance length L ₂ and a resistance width W ₂ . In the second resistor 62, the temperature coefficient is set to α ₂ = −α ₁ , the sheet resistance at the temperature t ₀ is set to ρs _02, and the resistance at the temperature t ₀ is further set according to the type and the introduction amount of the second impurity 62a. The value is such that R ₀₂ = R ₀₁ .

Here, for example, the second resistor 62 is used.
Is boron difluoride ion as a second impurity 62a in a portion of the resistance pattern made of the polysilicon film 23.
After implanting 1.3 × 10 ¹⁵ ions / cm ² ions with an implantation energy of eV, an annealing process is performed to activate the second impurities 62a. The second resistor 62 formed in this way has the point b _{2 on the} graph B.
As shown in, the temperature coefficient α ₂ = −700 ppm, the temperature t
The sheet resistance value at ₀ ° C. becomes ρs ₀₂ = 900Ω / □. Also, for example, here, due to layout problems, the second
Assume that the effective resistance length of the resistor 62 is set to L ₂ = L ₁ , and the resistance width W ₂ = (ρs ₀₂ / ρs ₀₁ ) × W
_By setting to ₁ , R ₀₂ = ρs ₀₂ × L ₂ / W ₂ = R ₀₁ is set.

In the resistance element 60 having the above structure, the resistance value R of the resistance element 60 becomes a combined resistance when the first resistor 61 and the second resistor 62 are connected in series. here,
The first resistor 61 and the second resistor 62 have resistance values R at the same temperature t ₀ as in the resistor element of the first embodiment.
₀₁ = R ₀₂ and the temperature coefficient α ₁ = −α ₂ . From these facts, the resistance element 60 is maintained at a constant resistance value irrespective of the temperature change as in the case of the resistance element of the first embodiment. Therefore, in the semiconductor device having the resistance element 60, the compensation circuit should be provided. Therefore, accuracy and power consumption of the semiconductor device can be stabilized, and high integration of the semiconductor device can be achieved.

Next, FIGS. 7A to 7C are views showing the main part of the semiconductor device of the fourth embodiment, and the semiconductor device of the fourth embodiment will be described below with reference to these drawings. explain. 7 (1) is a plan view of the main part of the semiconductor device, and FIG.
Is a sectional view taken along the line AA ′ of the plan view, and FIG. 7C is a sectional view taken along the line BB ′ of the plan view.

As shown in the figure, this semiconductor device is
Resistor element 7 including a resistor 71 and a second resistor 72
0, and the second resistor 72 is laminated on the first resistor 71 in a state of being joined to the first resistor 71. Then, terminal wirings 74 and 75 are connected to both ends of the second resistor 72, respectively.
The first resistor 71 and the second resistor 72 are connected in parallel.

The first resistor 71 is, for example, the first resistor 71.
It is composed of the same diffusion layer as the first resistor shown in the embodiment, and has a resistance length L ₁ , a resistance width W ₁ , a temperature coefficient α ₁ , and a sheet resistance ρs ₀₁ at a temperature t ₀ . The resistance value at temperature t ₀ is R ₀₁ . The second resistor 72 is, for example, the first resistor described above.
It is made of a polysilicon film similar to the second resistor shown in the embodiment, and has a temperature coefficient of α ₂ = −α ₁ and a temperature of t _0.
Is set to ρs ₀₂ , and further the resistance length L ₂ = L ₁ and the resistance width W ₂ = (ρs ₀₂ / ρs ₀₁ ) × W ₁ are formed, so that the resistance value at the temperature t ₀ is R ₀₂ = R ₀₁
It becomes something.

The resistance element 70 configured as described above is
Since the first resistor 71 and the second resistor 72, which have the above-mentioned resistance characteristics and are connected in parallel, are laminated, a stable resistance value is obtained irrespective of temperature change. It is possible to reduce the arrangement area of the resistance element 70 that is kept, and it is possible to further improve the integration degree of the semiconductor device.

8 (1) to 8 (5) show a method of manufacturing the above semiconductor device. An example of the method for manufacturing the semiconductor device will be described below with reference to these drawings. First, FIG.
In the first step shown in (1), the substrate 2 is formed by the CVD method.
A silicon oxide film 22 having a film thickness of 100 nm is formed on the upper surface of 1. Next, the silicon oxide film 2 is etched by etching using a resist pattern (not shown) as a mask.
2, a hole pattern 22a having a width W ₁ and a length L ₁ or more is formed.

Then, the silicon oxide film 2 is formed by the CVD method at 650 ° C. in a state of filling the hole pattern 22a.
A polysilicon film 23 having a film thickness of 150 nm is formed on the upper surface of 2. After that, the same second impurity 72a as that described in the first embodiment is introduced into the polysilicon film 23 by the same ion implantation as in the first embodiment. Next, the first
Similar to the embodiment, the polysilicon film 23 is etched into the shape of the second resistor (72).

Then, in the second step shown in FIG.
Similar to the first embodiment, after forming the insulating film 24 on the silicon oxide film 22 in a state of covering the polysilicon film 23,
A second resistor 72 is formed by performing an activation annealing process on the second impurity 72a in the polysilicon film 23. In addition, in this annealing treatment, the second impurity 72a in the second resistor 72 is used as the first impurity 61a to form the substrate 21.
A first resistor 71 is formed by diffusing it inside and introducing a first impurity 71a on the surface side of the substrate 21.

After the first resistor 71 and the second resistor 72 are formed as described above, the third resistor 71 shown in FIG.
In the process, contact holes 26 reaching the upper surface of the second resistor 72 are formed at both ends of the second resistor 72 by RIE of the insulating film 24 using a resist pattern (not shown) as a mask. Here, only the contact hole 26 on one end side is shown.

Next, in the fourth step shown in FIG. 8D, the silicon oxide film 2 is filled with the contact holes 26.
2. A conductive layer is formed on the second conductive layer 2, and the conductive layer is patterned to connect to both ends of the second resistor 72.
4 (75) is formed.

As described above, the second resistor is formed on the first resistor 71.
The resistance element 70 is formed by stacking the resistors 72 of FIG. When the resistance element 70 is formed as described above, for example, the second resistor 72 is formed in the same step as the base electrode forming step of the bipolar transistor having the double polysilicon structure, and the external base diffusion layer of the bipolar transistor is formed. It is possible to form the first resistor 71 in the same process as that of forming the first resistor 71. Therefore, the resistance element 71 can be formed on the same substrate as the bipolar transistor without increasing the mask process in the manufacturing process of the bipolar transistor.

When the temperature coefficient α ₁ of the first resistor 72 cannot be adjusted to a predetermined value only by the impurities solid-phase diffused from the second resistor 72 in the second step, the above first
After the hole pattern 22a is formed in the silicon oxide film 22 in the step, the first impurities 71a are previously introduced into the substrate 21 by ion implantation using the silicon oxide film 22 as a mask, and the solid-phase diffused impurities are removed. In addition, a predetermined temperature coefficient α ₁ may be obtained.

In the fourth embodiment, the first resistor 71 and the second resistor 72 are joined to each other in the first resistor 71.
The case where the second resistor 72 is laminated on the above is taken as an example. However, if the first resistor 71 and the second resistor 72 are not joined but are in a connected state and stacked, the semiconductor device can be highly integrated similarly to the fourth embodiment. Is possible.

In the first to third resistors used in each of the above-mentioned embodiments, if the respective resistance characteristics have the resistance characteristics as shown in each of the above-mentioned embodiments, a diffusion layer or impurities are diffused. It is not limited to polysilicon. Also,
Similarly, the first to third impurities diffused in the first to third resistors are not limited to the above.

[0059]

As described above, according to the semiconductor device of the present invention, the resistance values at the same temperature are substantially the same, the signs of the temperature coefficients are opposite, and the absolute values of the temperature coefficients are substantially the same. By providing the resistance element that is joined or connected to the second resistor, it becomes possible to incorporate the resistance element that can secure a constant resistance value without depending on the temperature change into the semiconductor device. Therefore, the accuracy of the semiconductor device can be ensured without providing the semiconductor device with a circuit for compensating the change in the resistance value of the resistance element due to the temperature change, and the high integration of the semiconductor device can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a main part of a semiconductor device of a first embodiment.

FIG. 2 is a graph showing a relationship between a temperature coefficient and a sheet resistance value.

FIG. 3 is a diagram showing the method of manufacturing the semiconductor device of the first embodiment.

FIG. 4 is a diagram showing a main part of a semiconductor device according to a second embodiment.

FIG. 5 is a diagram showing the method of manufacturing the semiconductor device of the second embodiment.

FIG. 6 is a diagram showing a main part of a semiconductor device according to a third embodiment.

FIG. 7 is a diagram showing a main part of a semiconductor device according to a fourth embodiment.

FIG. 8 is a diagram showing the method of manufacturing the semiconductor device of the fourth embodiment.

FIG. 9 is a diagram showing a main part of a conventional semiconductor device.

[Explanation of symbols]

 10, 40, 60, 70 Resistance element 11, 41, 61, 71 First resistance body 12, 42, 62, 72 Second resistance body 43 Third resistance body

Claims (2)

[Claims] 1. A first resistor and a resistor arranged in a state of being joined to the first resistor or connected to the first resistor, wherein the resistance values at the same temperature are the same as those of the first resistor. Of the second resistor whose temperature coefficient is substantially equal to that of the first resistor and whose temperature coefficient has a sign opposite to that of the first resistor and whose absolute value of the temperature coefficient is substantially equal to that of the first resistor. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein the first resistor and the second resistor are arranged in a stacked state.