JPH0936346A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Construction] The conductive regions of the main surfaces 101 and 102 are formed of an insulating protective film to control the current in the peripheral portion of the semiconductor substrate 10. The protective films 51 and 52 are exposed at least in the portion where there is no electrode, and the electrode 6 is used when the end is chemically treated.
1, 62, 63 and the main surfaces 101, 1 of the semiconductor substrate 10.
No. 02 was not exposed. [Effect] A current does not flow in the peripheral portion of the semiconductor substrate so that the temperature rise can be suppressed, and the side surface of the end portion and a part of the main surface of the semiconductor substrate whose end portion has been processed are exposed and the metal electrode is not exposed. As described above, it is possible to fix with a jig, only the side surface of the end portion can be chemically treated, the metal ion does not adhere to the side surface of the end portion, and the shape of the end portion can be maintained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art FIG. 6 shows an end structure of a conventional gate turn-off thyristor. The semiconductor substrate 10 has a p-type emitter layer 1 exposed on one main surface 101, an n-type base layer 2 adjacent to the p-type emitter layer 2, a p-type base exposed on the other main surface 102 adjacent to the n-type base layer. Layer 3, Adjacent to p-type base layer and n-type emitter layer 4 exposed to the other main surface 102 together with p-type base layer, and n + layer 21 connecting anode electrode and n-type base layer 2 with low resistance Has been done. Such a structure is a known technique for improving the performance of GTO. When gallium or the like is used to form the p-type base layer 3, the n + layer 21 and the p-type emitter layer 1 are formed after removing unnecessary diffusion layers by grinding. p
A pn junction J1, between the n-type base layer 2 and the n-type base layer 2, between the n-type base layer 2 and the p-type base layer 3, and between the p-type base layer 3 and the n-type emitter layer 4, respectively. J2 and J3 are formed, and J2 is the side surface 10 of the semiconductor substrate 10.
3, J1 is the main surface 101, and J3 is the other main surface 10
2 terminates on the side of the etched-down groove. After carrying out a predetermined diffusion, the semiconductor substrate has a protective layer 5 on the main surface 102.
2 to form the electrode 61 larger than the semiconductor substrate and the main surface 1
Alloy with 01 and join. After alloying, the electrodes 62 and 63 on the other main surface 102 are formed. Next, the end portion of the semiconductor substrate is formed into a predetermined shape by a sandblast method or the like. Due to the size relationship between the semiconductor substrate 10 and the electrode 61, the semiconductor substrate 10 is smaller than the electrode 61. FIG. 6 shows an example of beveling at 45 degrees. Then, in order to remove processing strain and the like at the time of forming the end portion, a chemical treatment is performed with a mixed acid or the like that selectively etches only the semiconductor substrate. Using the electrodes 61, 62, 63 and the protective film 52 as protection for the chemical treatment, the semiconductor substrate is immersed in the treatment solution to treat only the end side surface 103. The semiconductor substrate 10 is covered with a protective material 7 to protect the chemically treated side surface.

[0003]

Since a solution such as mixed acid is used as a processing solvent and a metal electrode serves as a protective layer, the metal ions forming the electrode are chemically treated when the end is chemically processed. It melts out and adheres to the side surface of the end portion, the surface electric field changes, the leak current increases, and the breakdown voltage of the element deteriorates. In particular, this is a problem in a semiconductor element having a large withstand voltage in which the pn junction is exposed on the side surface of the semiconductor substrate. In the structure shown in FIG. 6, if the size of the electrode 61 is made smaller than that of the semiconductor substrate 10 and the electrode 61 is surrounded by a jig or the like and protected against chemical treatment, metal contamination can be prevented. However, if the size of the electrode 61 is reduced, the semiconductor substrate is exposed at a part of the main surface 101, and the exposed main surface and the end side surface are chemically treated, so that the shape of the end is deformed. There is. In particular, in the case of a ground surface, there is a problem that the deformation of the end shape is remarkable due to the variation of the chemical treatment due to the processing strain, and the breakdown voltage of the element is lowered. Further, in a pressure contact type semiconductor device which does not alloy with an electrode larger than the semiconductor substrate, it is difficult to make contact with the electrode in the peripheral portion of the semiconductor substrate. Therefore, heat generation in the peripheral portion of the semiconductor substrate becomes a problem.

An object of the present invention is to provide a structure which can obtain good withstand voltage characteristics and reliability.

[0005]

In order to achieve the above object, the present invention limits the conductive region on the main surface with an insulating protective film to control the current in the peripheral portion of the semiconductor substrate. In addition, the protective film is exposed at least in the portion where there is no electrode, and the two main surfaces of the electrode and the semiconductor substrate are not exposed when the end is chemically treated. Further, only the side surface of the end portion can be chemically treated, adhesion of metal ions is prevented, and the shape of the end portion is maintained. In the above structure, a protective film is formed on a predetermined diffused semiconductor substrate, and then the protective film in a region that makes low resistance contact with the electrode is removed by photolithography and etching. At this time, the protective film in the non-conductive region is left.
A metal serving as an electrode is deposited on the surface of the semiconductor substrate patterned in this way, and unnecessary portions of the metal are removed by photolithography and etching, and the ends are processed into a predetermined shape.

[0006]

According to the structure obtained by the above means, the conductive region is limited to the portion without the insulating protective film. As a result, current does not flow in the peripheral portion of the semiconductor substrate, so that temperature rise can be suppressed and reliability is improved. Furthermore, the semiconductor substrate whose end portions have been processed can be fixed with a jig so that the end side surfaces and a part of the main surface are exposed and the metal electrodes are not exposed, and only the semiconductor substrate can be chemically treated. It will be possible. This prevents metal ions from attaching to the side surface of the edge,
Further, since the main surface has the protective film, only the side surface of the end can be processed, so that the shape of the end can be maintained, and the withstand voltage and reliability are improved.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings.

A gate turn-off thyristor (hereinafter referred to as GTO) having a pnpn structure in which the conductivity type of a semiconductor wafer as a starting material is n-type will be described in accordance with a general manufacturing method.

In FIG. 2, the semiconductor substrate 10 has a p-type emitter layer 1 exposed on one main surface 101, an n-type base layer 2 adjacent to the p-type emitter layer 2 and an n-type base layer adjacent to the other main surface 102. The p-type base layer 3 exposed at the n-type, the n-type emitter layer 4 adjacent to the p-type base layer and exposed on the other main surface 102 together with the p-type base layer, and the anode electrode and the n-type base layer 2 are connected with low resistance. It is composed of an n + layer 21. Such a structure is a known technique for improving the performance of GTO. pn is provided between the p-type emitter layer 1 and the n-type base layer 2, between the n-type base layer 2 and the p-type base layer 3, and between the p-type base layer 3 and the n-type emitter layer 4, respectively.
Junctions J1, J2 and J3 are formed, with J2 terminating on the side surface 103 of the semiconductor substrate 10, J1 on the main surface 101 and J3 on the side surface of the etched-down groove on the other main surface 102. A protective film is formed on the two main surfaces 101 and 102. The protective film forms an oxide film by thermal oxidation, thermally diffuses phosphorus, and further deposits the oxide film by a chemical vapor deposition method. Alternatively, there is a method of depositing an oxide film containing phosphorus by a chemical vapor deposition method on the thermal oxide film and further depositing an oxide film not containing phosphorus. Next, as shown in FIG. 3, the conductive region and the non-conductive region around the element are patterned by photolithography, the protective film in the conductive region is removed, and then metal serving as an electrode is formed on the entire surfaces of the two main surfaces 101 and 102. Deposit. Further, after removing an unnecessary portion of the electrode by patterning it by photolithography, the end portion of the semiconductor substrate is formed into a predetermined shape by a sandblast method or the like. FIG. 4 shows an example of beveling at 45 degrees.
In this embodiment, the width of the protective film 51 on the main surface 101 is 2 mm.
And This width does not need to be limited to 2 mm, and the jig 81
If there is a width that can be fixed with. Then, in order to remove the processing strain and the like at the time of forming the end portion, a chemical treatment is performed with a mixed acid or the like that selectively etches only the semiconductor substrate, but at this time, the metal of the electrode is not dissolved in the treatment solution. To Figure 5
The ends are chemically processed using jigs 81 and 82 as shown in FIG. As shown in FIG.
By fixing so that only the end side surface 103 and a part of the protective film are exposed at 82, the metal of the electrode can be treated without being exposed to the treatment solution or the like, so that the metal ions of the electrode are dissolved in the treatment solution. Can be prevented and the metal ions can be prevented from adhering to the side surface. Furthermore, since there are protective films 51 and 52 on the two main surfaces 101 and 102 in the part exposed from the jig, there is no reaction and only the end side surface 103 can be processed, so processing is performed with the end shape maintained. it can. The end portion is covered with a surface protective material to form the structure shown in FIG. Since the semiconductor substrate itself is not exposed at the two main surfaces 101 and 102, contamination by impurities from the outside can be prevented and reliability is improved. The end shape to which the present invention can be applied does not need to be limited to the 45 degree bevel, and can be applied to any shape.

FIG. 7 shows a second embodiment in which a cushioning material having a larger electrode outer diameter is used. By using the buffer materials 91 and 92 having the same size as the semiconductor substrate 10,
This is an example of a structure in which the electric field around the semiconductor substrate side surface 103 and the insulating protective film 51 is controlled to prevent the accumulation of ions that cause a decrease in reliability and improve the reliability.

FIG. 8 shows a third embodiment in which the outer diameter of the electrode 61 is larger than the inner diameter of the insulating protective film 51.
By spreading the electrode layer having a low thermal resistance even over the protective film 51, the heat radiation effect in the peripheral portion of the semiconductor substrate can be improved.

FIG. 9 shows an example in which the present invention is applied to a diode. A semiconductor substrate 10 is exposed on one main surface 102 of an n + layer 31, an n layer 21 adjacent to the n + layer 31, and an n layer 21 adjacent to the n layer 21. The p-layer 11 is exposed on the other main surface 101. In the case of a diode as well, like the GTO, the end shape to which the present invention can be applied need not be limited to a bevel of 45 degrees, and can be applied to any shape.

FIG. 10 shows an example in which the present invention is applied to a thyristor. The semiconductor substrate 10 has a p-type emitter layer 12 exposed on one main surface 101, and n-type base layers 22 and n adjacent to the p-type emitter layer. P type base layer 32 adjacent to mold base layer 22 and exposed on the other main surface 102, and adjacent to p type base layer 32 and p type base layer 32 on the other main surface 10
The n-type emitter layer 42 exposed at 2.
The end shape to which the present invention can be applied need not be limited to the bevel shape of the Greek letter Σ shown in FIG. 8 and can be applied to any shape.

11 to 14 show steps of manufacturing a semiconductor device in which one main surface to which the present invention is applied is ground.
The conductivity type of the starting material semiconductor wafer is n-type, and as shown in FIG. 11, the p-type base layer 3 is formed by diffusion. next,
As shown in FIG. 12, the unnecessary diffusion layer on one main surface 101 is removed by grinding. Then, as shown in FIG.
After forming the type emitter layer 4 and the n + layer 21, the main surface 102 having the p type base layer 3 formed thereon is etched down to form the n type emitter layer 4. Further, after the p-type emitter layer 1 is formed, heat treatment is performed to obtain a predetermined diffusion distribution shown in FIG. The subsequent steps are in accordance with the first embodiment. When one of the main surfaces is ground, the gettering effect of the grinding and the protective film on the main surface make the end face shape sharp, so that the pressure resistance and reliability are improved.

[0015]

According to the present invention, the periphery of the semiconductor substrate is
The current does not flow and the temperature rise can be suppressed. Moreover, since the protective film is provided on the main surface without electrodes, the electrodes are not exposed when the end is chemically treated. As a result, only the side surface of the end of the semiconductor substrate can be chemically treated, adhesion of metal ions can be prevented, and the shape of the end can be maintained, so that the breakdown voltage is improved.

[Brief description of drawings]

1 is a cross-sectional view of an end portion of the present invention.

FIG. 2 is an explanatory view showing a manufacturing process.

FIG. 3 is an explanatory view showing a manufacturing process.

FIG. 4 is an explanatory view showing a manufacturing process.

FIG. 5 is an explanatory view showing a manufacturing process.

FIG. 6 is an explanatory diagram of an example of a conventional structure.

FIG. 7 is a sectional view of the second embodiment.

FIG. 8 is a sectional view of a third embodiment.

FIG. 9 is a sectional view of an example applied to a diode.

FIG. 10 is a sectional view of an example applied to a thyristor.

FIG. 11 is a diagram showing a manufacturing process of a semiconductor device to which the present invention is applied, in which one of the main surfaces is ground.

FIG. 12 is a diagram showing a manufacturing process of a semiconductor device to which the present invention is applied, in which one main surface is ground.

FIG. 13 is a diagram showing a manufacturing process of a semiconductor device, to which one of the main surfaces is ground, to which the present invention is applied.

FIG. 14 is a diagram showing a manufacturing process of a semiconductor device, to which one of the main surfaces is ground, to which the present invention is applied.

[Explanation of symbols]

1 ... p-type emitter, 2 ... n-type base, 3 ... p-type base,
4 ... N-type emitter, 7 ... Surface protective material, 10 ... Semiconductor substrate, 51 and 52 ... Protective film, 61, 62 and 63 ...
Electrodes, 101 and 102 ... Main surface.

Claims (5)

[Claims] 1. At least one pn junction is exposed on a side surface of a semiconductor substrate, an end portion of the semiconductor substrate is processed into a predetermined shape, and two main surfaces of the semiconductor substrate are used as anode and cathode electrodes. A semiconductor device having a structure in which a conductive region on one of the main surfaces is restricted by an insulating protective film in a semiconductor device in contact with each other on a surface. 2. At least one pn junction is exposed on a side surface of a semiconductor substrate, an end portion of the semiconductor substrate is processed into a predetermined shape, and two main surfaces of the semiconductor substrate serve as an anode and a cathode electrode. A semiconductor device having a surface-contacting structure, wherein one of the main surfaces is ground and the conductive region is restricted by an insulating protective film. 3. A semiconductor device according to claim 1, wherein the outer diameter of the electrode is equal to the inner diameter of the insulating protective film. 4. The semiconductor device according to claim 1 or 2, wherein the semiconductor substrate is pressure-contacted with a buffer material having a larger diameter than the outer diameter of the electrode. 5. The semiconductor device according to claim 1 or 2, wherein the outer diameter of the electrode is larger than the inner diameter of the insulating protective film and the electrode is on the insulating protective film.