JPH0936357A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the electrostatic breakdown voltage of an LSI using a transistor having a low resistance source and drain. The N-type diffusion region 10 is formed so as to be surrounded by the N well 5 and is connected to the input / output pad 13. The N-type diffusion region 11 is formed so as to protrude from the N well 5, and the silicon oxide film 8 is formed. In the vicinity, it is directly bonded to the P-type semiconductor substrate 100. The N-type diffusion region 12 is the GND pad 9
8 and N by the silicon oxide film 8
It is separated from the type diffusion region 11. When a surge is applied to this, the N well 5 becomes a resistance component, so that the junction 15 between the N type diffusion region 11 and the P type semiconductor substrate 100 is formed.
The electric field of 1 is relaxed, and it is possible to prevent the destruction at the joint portion 15 due to the discharge.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection transistor and an output transistor for preventing electrostatic breakdown in a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In recent years, efforts have been made to reduce the parasitic resistance of transistors for higher integration and higher speed of LSIs.
As a typical technique therefor, there is a technique of siliciding the source and drain of a transistor. This is to reduce the source / drain resistance by siliciding the surface of the source / drain diffusion region. Furthermore, this technique facilitates reduction of the source and drain areas, so that high integration and high speed of LSI can be realized. However, lowering the resistance of the source and drain brings about a significant decrease in the electrostatic breakdown voltage of the LSI. This is because, in the protection transistor for preventing electrostatic breakdown of the LSI, the electric field strength of the PN junction is remarkably increased due to the low resistance of the source and drain when a surge is applied, and the protection transistor itself is electrostatically destroyed. is there.

Therefore, in order to prevent the above-mentioned destruction, a protection transistor having the following structure has been conventionally proposed.

FIG. 9 is a structural sectional view of a conventional protection transistor. In FIG. 9, 100 is a P-type semiconductor substrate, 1 is a low concentration N well (for example, about 10 ¹⁷ / cm ³ ), 2 and 103 are silicon oxide films, and 3 and 4 are high concentration (for example, 10 ²⁰ / cm ^3). ), N-type diffusion regions, 101 and 102 are titanium silicide films formed on the surfaces of N-type diffusion regions 3 and 4, 13 is an input / output pad serving as an external electrode, and 98 is a GND pad. Here, the N type diffusion region 3 is formed on the P type semiconductor substrate 100 so as to be surrounded by the N well 1, and the N type diffusion region 4 is connected to the GND pad.

With the above structure, the NPN for electrostatic breakdown protection
A lateral bipolar transistor 95 is formed. That is, the N-type diffusion region 3 and the N well 1 are collectors, P
The type semiconductor substrate 100 serves as a base, and the N type diffusion region 4 serves as an emitter.

When a positive surge is applied from the input / output pad 13 to the protection transistor configured as described above, the protection transistor 95 is turned on and a discharge current flows from the N-type diffusion region 4 to the outside through the GND pad. But N
The well 1 serves as a resistance component, and the electric field between the N-type diffusion region 3 and the P-type semiconductor substrate 100 can be relaxed to prevent destruction.

[0007]

However, in the above structure, since the N well 1 and the N type diffusion region 4 are formed by using different masks, the distance between them, that is, the base width of the protection transistor is increased. Therefore, there is a problem in that the discharge rate is reduced, and as a result, the breakdown voltage of the internal circuit of the LSI is reduced. In addition, since the variation in the base width is large, the protection transistor 9
There was also a problem that the discharge characteristics of No. 5 could not be made uniform.

In view of the above problems, the present invention provides a protection transistor capable of maintaining a high electrostatic breakdown voltage even when the source and drain of the transistor have a low resistance.

[0009]

In order to solve the above-mentioned problems, a semiconductor device of the present invention is provided with a second road type first, second and third semiconductor devices formed on a first road type semiconductor substrate. 3 has a high-concentration diffusion region and a second road type low-concentration diffusion layer, the first diffusion region is formed in the diffusion layer and connected to an external electrode, and the second diffusion region is a power electrode. Alternatively, the third diffusion region is connected to the ground electrode, the third diffusion region is separated from the first diffusion region by the diffusion layer, is in contact with and electrically connected to the diffusion layer, and is further connected to the second diffusion region and the first conductive type semiconductor. It is separated by the substrate.

In the semiconductor device of the present invention, the second conductive type first, second, third, and fourth high-concentration diffusion regions and the second conductive type formed on the first conductive type semiconductor substrate are provided. A first and a second low-concentration diffusion layer of electric conductivity type, wherein the first diffusion region is formed in the first diffusion layer and connected to an external electrode;
The second diffusion region is formed in the second diffusion layer and connected to the power supply electrode or the ground electrode, the third diffusion region is separated from the first diffusion region by the first diffusion layer, and the first diffusion region is formed. The fourth diffusion region is in contact with and electrically connected to the layer, and the fourth diffusion region is the second diffusion region.
Is separated from the second diffusion region by the first diffusion layer and is in contact with and electrically connected to the second diffusion layer, and the third and fourth diffusion regions are separated from each other by the first conductive type semiconductor substrate. Has become.

[0011]

According to the present invention, the base width of the protection transistor is increased by forming the resistance component in the bipolar protection transistor formed between the high-concentration diffusion regions and the collector or the emitter thereof by the low-concentration diffusion layer. It can be formed finely and the variation in its discharge characteristics can be reduced.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a structural sectional view of an electrostatic discharge protection transistor of an integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is a plan view of the embodiment. In FIG. 1, 100 is a P-type semiconductor substrate, 5 is a low-concentration N well (for example, about 10 ¹⁷ / cm ³ ), 6, 7,
8 and 9 are silicon oxide films, 10, 11 and 12 are high concentration
N type diffusion region (for example, about 10 ²⁰ / cm ³ ), 80, 8
Reference numerals 1 and 82 are titanium silicide films formed on the surfaces of the N-type diffusion regions 10, 11 and 12, 13 is an input / output pad serving as an external electrode, and 98 is a GND pad. N-type diffusion region 1
0 is formed on the P-type semiconductor substrate 100 so as to be surrounded by the N well 5. The N type diffusion region 10 is connected to the input / output pad 13. The input / output pad 13 is connected to the internal circuit of the integrated circuit device.

The N-type diffusion region 11 is formed so as to protrude from the N-well 5 and is connected to the N-well 5 in the region 14, but in the region 15 near the silicon oxide film 8 the P-type semiconductor substrate. It is directly bonded to 100. The N-type diffusion region 10 is separated by the silicon oxide film 7. The N type diffusion region 12 is connected to the GND pad 98 and the N type diffusion region 11 is formed by the silicon oxide film 8.
Is separated from. With the above configuration, the NPN lateral bipolar transistor 16 for electrostatic breakdown protection is formed. That is, the N type diffusion region 10, the N well 5 and the N type
The type diffusion region 11 is a collector, the P-type semiconductor substrate 100 is a base, and the N-type diffusion region 12 is an emitter.

The protection transistor 16 having such a structure
Is applied with a + surge from the input / output pad 13,
When discharged to the pad 98, the discharge current flows into the N-type diffusion region 11 through the N-type diffusion region 10 and the N-well 5, and the protection transistor 16 is turned on to turn on the P-type semiconductor substrate 1.
Flow out from the N-type diffusion regions 12 through 00, but at this time, even if the surfaces of the N-type diffusion regions 10 and 11 are titanium silicide and have low resistance, the N between the N-type diffusion regions 10 and 11 is reduced.
Since the well 5 becomes a resistance component, the N-type diffusion region 11 and P
The electric field at the junction 15 with the type semiconductor substrate 100 is relaxed, and the destruction at the junction 15 due to discharge can be prevented. Moreover, since the N-type diffusion region 10 is surrounded by the N-well 5, no junction breakdown occurs with the P-type semiconductor substrate 100. Further, in the present embodiment, the separation width between the N-type diffusion regions 11 and 12 becomes the base width of the protection transistor 16, so that the base width can be miniaturized, and as a result, the discharge speed of the protection transistor 16 is improved and the internal circuit is improved. The electrostatic breakdown voltage can be improved. Further, since the size of the diffusion regions can be easily controlled, the discharge characteristic of the protection transistor 16 can be made uniform.

(Embodiment 2) FIG. 3 is a structural sectional view of an electrostatic breakdown protection transistor of an integrated circuit device according to a second embodiment of the present invention, and FIG. 4 is a plan view thereof. The N type diffusion regions 24 and 25 and the N well 20 have the same configurations as the N type diffusion regions 10 and 11 and the N well 5 of FIGS.

In FIG. 3, high-concentration N-type diffusion regions 25 and 26 are shown.
A MOS transistor is formed by the gate electrode 27 and the N-type diffusion region 25 is formed so as to protrude from the N-well 20. In the region near the gate electrode 27, the N-type diffusion region 25 is directly bonded to the P-type semiconductor substrate 100. There is. In such a configuration, when a + surge is applied to the input / output pad 13 and the GND pad 98 is discharged, the discharge current flows into the N-type diffusion region 25 via the N-type diffusion region 24 and the N-well 20, and further, The parasitic NPN lateral bipolar transistor 94 formed by the N-type diffusion regions 25 and 26 and the P-type semiconductor substrate 100 is turned on to turn on the P-type semiconductor substrate 10.
0 flows out from the N-type diffusion regions 26 through 0, but even if the surfaces of the N-type diffusion regions 25 and 26 are made into titanium silicide and have a low resistance as in the first embodiment, the N-type diffusion regions 24 and 25 are formed. Since the N well 20 between them serves as a resistance component, the electric field at the junction portion 32 between the N type diffusion region 25 and the P type semiconductor substrate 100 is relaxed, and this junction portion 3 due to discharge is formed.
The destruction at 2 can be prevented. By using the MOS transistor having the above structure as an output transistor for transmitting a signal from the inside of the integrated circuit device to the outside, an output transistor having a high electrostatic breakdown voltage can be realized.

The N-type diffusion regions 12 and 26 of the first and second embodiments are connected to the GND pad, respectively, but it goes without saying that they may be connected to the power supply pad. .

(Embodiment 3) FIG. 5 is a structural sectional view of an electrostatic breakdown protection transistor of an integrated circuit device according to a third embodiment of the present invention, and FIG. 6 is a plan view thereof. In FIG. 5, 100 is a P-type semiconductor substrate, 33 and 34 are low-concentration N wells (for example, about 10 ¹⁷ / cm ³ ), 35, 36, and 3.
7, 38, 39 are silicon oxide films, 39, 40, 41,
42 is a high concentration (for example, about 10 ²⁰ / cm ³ ) N-type diffusion region, and 86, 87, 88, 89 are N-type diffusion regions 39, 4
A titanium silicide film formed on the surfaces of 0, 41 and 42, 13 is an input / output pad serving as an external electrode, and 99 is a power supply pad. N type diffusion regions 39 and 40, N well 33
Has the same configuration as the N type diffusion regions 10 and 11 and the N well 5 in FIG. Further, in this embodiment, the N type diffusion region 42 is formed on the P type semiconductor substrate 100 so as to be surrounded by the N well 34. The N type diffusion region 42 is connected to the power supply pad 99. N type diffusion region 41
Is formed to protrude from the N well 34,
The region 46 is connected to the N well 34, but is directly joined to the P type semiconductor substrate 100 in the region near the silicon oxide film 37. The N type diffusion regions 40 and 41 are separated by the silicon oxide film 37.

With the above structure, the NPN for electrostatic breakdown protection
A lateral bipolar transistor 43 is formed. That is, the N type diffusion region 39, the N well 33 and the N type diffusion region 40 are collectors, the P type semiconductor substrate 100 is the base, and the N type diffusion region 41, the N well 34 and the N type diffusion region 42 are the emitters.

The protection transistor 43 having such a structure
When a + surge is applied from the input / output pad 13 to the power supply pad 99, the N well 33 between the N type diffusion regions 39 and 40 becomes a resistance component as in the first embodiment. The electric field at the junction portion 44 between the type diffusion region 40 and the P-type semiconductor substrate 100 is relaxed, and breakdown at the junction portion 44 due to discharge can be prevented. Further, in the present embodiment, when the + surge is applied from the power supply pad 99 and is discharged to the input / output pad 13, the N well 34 between the N type diffusion regions 41 and 42 also becomes a resistance component, so that the N type diffusion is performed. Area 41 and P
The electric field at the junction 45 with the type semiconductor substrate 100 is relaxed, and the destruction at the junction 45 due to discharge can be prevented. Further, since the separation width between the N-type diffusion regions 40 and 41 becomes the base width of the protection transistor 43, the base width can be miniaturized, and as a result, the discharge speed of the protection transistor 43 is improved and the electrostatic capacitance of the internal circuit is improved. The breakdown voltage can be improved.

(Embodiment 4) FIG. 7 is a structural sectional view of an electrostatic breakdown protection transistor of an integrated circuit device according to a fourth embodiment of the present invention, and FIG. 8 is a plan view thereof. The fourth embodiment has almost the same structure as the third embodiment,
In the third embodiment, the N-type diffusion regions 40 and 41 are separated by the silicon oxide film 37, whereas in the fourth embodiment, the N-type diffusion regions 59 and 60 and the gate electrode form the MOS.
The difference is that transistors are formed.

In such a structure, the input / output pad 1
When a + surge is applied to 3 and is discharged to the power supply pad 99, or when a + surge is applied from the power supply pad 99 and is discharged to the input / output pad 13, the N-type diffusion region is formed as in the third embodiment. Since the N well 52 between 58 and 59 has a resistance component, or the N well 53 between the N type diffusion regions 60 and 61 has a resistance component, the N type diffusion region 59.
And a P-type semiconductor substrate 100 are joined together 96 or an N-type diffusion region 60 and a P-type semiconductor substrate 100 are joined together 65.
The electric field of is relaxed, and destruction at these junctions can be prevented. An output transistor having a high electrostatic breakdown voltage can be realized by using the MOS transistor having the above structure as an output transistor for transmitting a signal from the inside of the integrated circuit device to the outside.

Although the N-type diffusion regions 42 and 61 of the third and fourth embodiments are connected to the power supply pads, they may be connected to the GND pad.

In each of the first, second, third and fourth embodiments, the NPN parasitic bipolar transistor is formed, but the PNP parasitic bipolar transistor may be formed.

Further, a titanium silicide film is formed on the surface of the N type diffusion region in the first, second, third and fourth embodiments, but another silicide film such as a cobalt silicide film is formed. Also, even if a metal film is deposited, the same effect can be obtained for improving the electrostatic breakdown voltage.

[0027]

As described above, according to the present invention, a surge component is formed by forming a resistance component in the bipolar protection transistor formed between the separated high-concentration diffusion regions and its collector or emitter by the low-concentration diffusion layer. At the time of application, the electric field at the junction between the high-concentration diffusion region and the semiconductor substrate is relaxed, destruction of this junction due to surge discharge can be prevented, and the base width of the protection transistor can be miniaturized. By improving the discharge speed of the protection transistor, the electrostatic breakdown voltage of the internal circuit can be improved. or,
The separation between the high-concentration diffusion regions is easy to control in size, so that the discharge characteristics of the protection transistor can be made uniform.

[Brief description of drawings]

FIG. 1 is a structural sectional view of an electrostatic breakdown protection transistor according to a first embodiment of the present invention.

FIG. 2 is a plan view of an electrostatic breakdown protection transistor according to the first embodiment of the present invention.

FIG. 3 is a structural sectional view of an electrostatic breakdown protection transistor according to a second embodiment of the present invention.

FIG. 4 is a plan view of an electrostatic breakdown protection transistor according to a second embodiment of the present invention.

FIG. 5 is a structural sectional view of an electrostatic breakdown protection transistor according to a third embodiment of the present invention.

FIG. 6 is a plan view of an electrostatic breakdown protection transistor according to a third embodiment of the present invention.

FIG. 7 is a structural sectional view of an electrostatic breakdown protection transistor according to a fourth embodiment of the present invention.

FIG. 8 is a plan view of an electrostatic breakdown protection transistor according to a fourth embodiment of the present invention.

FIG. 9 is a structural cross-sectional view of a conventional electrostatic breakdown protection transistor.

[Explanation of symbols]

1, 5, 20 N well 2, 6, 7, 8, 9 Silicon oxide film 3, 4, 10, 11, 12 N type diffusion region 13 Input / output pad 14 N type diffusion region and N well connection region 15 N type Junction portion between diffusion region and P-type semiconductor substrate 16 NPN parasitic lateral bipolar transistor 17, 18 Contact portion between N-type diffusion region and metal wiring 19, 20 Metal wiring 27 Gate electrodes 80, 81, 82 Titanium silicide film 98 GND pad 99 power supply pad 100 P-type semiconductor substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/73

Claims (4)

[Claims] 1. A low concentration diffusion layer having a second conductivity type formed on a semiconductor substrate having a first conductivity type, and a second concentration diffusion layer formed on the low concentration diffusion layer and connected to an external electrode. A high-concentration first diffusion region having a conductivity type, and a high-concentration second diffusion region having a second conductivity type formed so as to extend from the low-concentration diffusion layer onto the semiconductor substrate. A high-concentration third diffusion region of a second conductivity type formed on the semiconductor substrate and connected to a power supply electrode or a ground electrode, the semiconductor device comprising: the first diffusion region and the first diffusion region. The second diffusion region is separated by a first insulating layer, and the second diffusion region and the third diffusion region are separated by a second insulating layer. 2. A low concentration diffusion layer having a second conductivity type formed on a semiconductor substrate having a first conductivity type, and a second concentration diffusion layer formed on the low concentration diffusion layer and connected to an external electrode. A high-concentration first diffusion region having a conductivity type, and a high-concentration second diffusion region having a second conductivity type formed so as to extend from the low-concentration diffusion layer onto the semiconductor substrate. A high-concentration third diffusion region of a second conductivity type formed on the semiconductor substrate and connected to a power supply electrode or a ground electrode, the semiconductor device comprising: the first diffusion region and the first diffusion region. The second diffusion region is separated by a first insulating layer, the second diffusion region and the third diffusion region are separated by the semiconductor substrate, and the second diffusion region and the third diffusion region are separated. Formed on the semiconductor substrate via a gate insulating film Over gate electrode is formed, the gate insulating film, said gate electrode, a semiconductor device and forming a MOS transistor in said second diffusion region and said third diffusion region. 3. A first low concentration diffusion layer having a second conductivity type formed on a semiconductor substrate having a first conductivity type, and an external electrode formed on the first low concentration diffusion layer. A high concentration first diffusion region having a second conductivity type connected to
A high-concentration second diffusion region having a second conductivity type formed so as to extend from the first low-concentration diffusion layer onto the semiconductor substrate, and a semiconductor substrate having the first conductivity type on the second diffusion region. A second low-concentration diffusion layer having the second conductivity type formed, and a high-concentration second conductivity type formed on the second low-concentration diffusion layer and connected to a power supply electrode or a ground electrode. And a high-concentration fourth diffusion region having a second conductivity type and formed to extend from the second low-concentration diffusion layer onto the semiconductor substrate. Wherein the first diffusion region and the second diffusion region are separated by a first insulating layer, the second diffusion region and the fourth diffusion region are separated by a second insulating layer, and The fourth diffusion region and the third diffusion region are separated by a third insulating layer. Wherein a. 4. A first low-concentration diffusion layer having a second conductivity type formed on a semiconductor substrate having a first conductivity type, and an external electrode formed on the first low-concentration diffusion layer. A high concentration first diffusion region having a second conductivity type connected to
A high-concentration second diffusion region having a second conductivity type formed so as to extend from the first low-concentration diffusion layer onto the semiconductor substrate, and a semiconductor substrate having the first conductivity type on the second diffusion region. A second low-concentration diffusion layer having the second conductivity type formed, and a high-concentration second conductivity type formed on the second low-concentration diffusion layer and connected to a power supply electrode or a ground electrode. And a high-concentration fourth diffusion region having a second conductivity type and formed to extend from the second low-concentration diffusion layer onto the semiconductor substrate. Wherein the first diffusion region and the second diffusion region are separated by a first insulating layer, the second diffusion region and the fourth diffusion region are separated by a second insulating layer, and The fourth diffusion region and the third diffusion region are separated by a third insulating layer, A gate electrode formed via a gate insulating film on the semiconductor substrate separating the diffusion region from the fourth diffusion region, the gate insulating film, the gate electrode, and the second diffusion region. And the fourth
Forming a MOS transistor with the diffusion region of the semiconductor device.