JPH0936370A - Method for manufacturing coplanar thin film transistor - Google Patents

Abstract

(57) [Abstract] An object of the present invention is to provide a gate wire having good conductivity, which has a low process temperature of 600 ° C. or lower and does not have an increase in resistance due to oxidation as in the past, and has a sufficiently low resistance. The provided TFT is formed. SOLUTION: A polysilicon thin film to be an active layer 2 is formed on an insulating substrate 1 by an LP-CVD method, is etched by a CDE (chemical dry etching) method, and then an oxide film to be a gate insulating film 3 is formed. A film is formed by the atmospheric pressure thermal CVD method. Next, after a MoTa alloy or a MoW alloy is formed by a sputtering method, the gate electrode 4 is formed by the CDE method. Then, after injecting P (phosphorus), which is a donor, into the active layer, an oxide film to be the interlayer insulating layer 6 is formed by the atmospheric pressure thermal CVD method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a coplanar thin film transistor, and more particularly to a gate electrode material and a method of activation.

[0002]

2. Description of the Related Art An active matrix liquid crystal display device using a thin film transistor (hereinafter referred to as TFT) as a switching element is a device which is currently under active development because of its excellent display characteristics. Especially polysilicon TFT-L
The CD is expected as a future LCD because the mobility of the TFT is large and the same substrate for the driving circuit can be formed.

The problems of this polysilicon TFT are to lower the process temperature and increase the integration of pixels. An inexpensive glass substrate can be used by lowering the process temperature. That is, it is desired to suppress the process temperature to 600 ° C. or lower which is the strain point of the glass substrate.

In order to realize high integration, it is necessary to reduce the resistance of the gate electrode wiring.

Below, the maximum process temperature is 600 ° C. or less,
An example of a conventional method of manufacturing a coplanar type polysilicon TFT when a metal material single layer is used for a gate electrode is shown in FIG.
After explaining with reference to (a) to (d), problems of this manufacturing method will be described.

A polysilicon thin film to be the active layer 2 is formed on the insulating substrate 1 by the LP-CVD (low pressure chemical vapor deposition) method and etched, and then an oxide film to be the gate insulating film 3 is formed. Yes (Fig. 2
(A)).

Next, a gate electrode 4 is formed by forming a film of a metal material by sputtering and then etching it (FIG. 2 (b)).

Next, after implanting the impurities into the active layer, the impurities are activated by an annealing method to form the source and drain portions 5 (FIG. 2C).

Next, after forming the interlayer insulating layer 6, a contact hole 7 is opened and a signal line 8 is formed (FIG. 2).
(D)).

The above is the manufacturing method of the coplanar type polysilicon TFT when the metal material is used as the gate electrode.

[0011]

However, the manufacturing method of the coplanar type polysilicon TFT described in the conventional example is as follows.
I have some problems.

The first problem is that the metal material which will be the gate electrode is oxidized by activating it without forming the interlayer insulating layer. To prevent oxidation, a vacuum furnace must be used or hydrogen anneal must be performed. However, both methods have a problem that the structure is complicated and expensive.

A second problem is that the metal material for the gate electrode has a low resistance, serves as a mask for injecting disordered materials, has a heat resistance of 600 ° C., and is formed and processed. It needs to be easy. 600 ° C for Al alloy
It does not have heat resistance. Therefore, there is a problem that the metal material for the gate electrode is limited.

[0014]

In order to solve the above problems, the present invention provides an active layer formed of a semiconductor film, a gate insulating layer, a gate electrode, and an interlayer on an insulating substrate. A coplanar thin film transistor including an insulating layer, which includes a step of implanting impurity ions into a region corresponding to the source / drain regions of the semiconductor film, and a step of activating the impurity ions during a manufacturing process. The highest temperature
In the method for manufacturing a coplanar thin film transistor, which is 350 ° C. to 600 ° C., the gate electrode is at least M
After forming a layer formed of an oTa alloy or a MoW alloy as a material, the interlayer insulating layer or another insulating film in the interlayer insulating layer is formed to cover at least the gate electrode, A method of manufacturing a coplanar thin film transistor, comprising a step of activating a drain region.

According to the present invention, by adopting the above-mentioned means, the interlayer insulating layer is formed so as to cover the gate electrode,
TFT without oxidizing the metal that is the gate electrode material
Therefore, at a low process temperature of 600 ° C or less, which is significantly lower than the conventional process temperature, there is no increase in resistance due to oxidation as in the past, and the resistance is sufficiently low. It is possible to form a TFT including a gate wiring having good conductivity.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to FIGS.
FIG. 1 is a diagram showing a main part of the manufacturing method of the present invention.

After depositing a polysilicon thin film to be the active layer 2 on the insulating substrate 1 by the LP-CVD method and etching by the CDE (chemical dry etching) method,
An oxide film to be the gate insulating film 3 is formed by the atmospheric pressure thermal CVD method (FIG. 1A).

Next, a MoTa alloy or a MoW alloy is formed by a sputtering method, and then the gate electrode 4 is formed by the CDE method (FIG. 1B).

Next, after injecting P (phosphorus), which is a donor, into the active layer, the oxide film to be the interlayer insulating layer 6 is subjected to atmospheric pressure CV.
A film is formed by the D method (FIG. 1C).

Next, after activating P by annealing at 600 ° C. to form the source / drain regions 5, the contact holes 7 are opened and the signal lines 8 are formed (FIG. 1 (d)). Is the main part of the method for manufacturing a coplanar type polysilicon TFT having a metal gate electrode according to the present invention.

According to the manufacturing method of the present invention, one example of which is shown in the above-described embodiment, a TFT can be formed without oxidizing a metal which is a gate electrode material. In the above embodiment, the interlayer insulating layer 6
Was also used as an insulating film for covering the gate electrode 4, but it goes without saying that these insulating films may be separately provided.

Further, although the interlayer insulating layer 6 is an oxide film formed by the atmospheric pressure thermal CVD method in the present embodiment, it may be formed by an oxide film or a nitride film formed by the plasma CVD method. Is applicable.

Further, the gate electrode is not limited to the above-mentioned single layer of MoTa alloy or MoW alloy, and a laminated layer or Mo layer of these.
Lamination of Ta alloy and Si compound or MoW alloy and S
It may be laminated with an i compound. At this time, the Si compound layer may be formed so as to be a lower layer when viewed from the direction of implanting the impurity ions.

Further, in this example, the TFT is an n-type p-Si TFT having a coplanar structure, but it goes without saying that the present invention is also applicable to a p-type TFT.

[0025]

As is clear from the detailed description above, according to the present invention, the temperature is significantly lower than the conventional process temperature.
At a low process temperature of 00 ° C. or less, it is possible to form a TFT provided with a gate wiring having good conductivity and having no resistance increase due to oxidation as in the past and having sufficiently reduced resistance. .

[Brief description of drawings]

FIG. 1 is a diagram showing a main part of a manufacturing method of the present invention.

FIG. 2 is a diagram showing an example of a conventional manufacturing method of a coplanar type polysilicon TFT.

[Explanation of symbols]

1 ... Insulating substrate, 2 ... Active layer, 3 ... Gate insulating film, 4 ...
Gate electrode, 5 ... Source / drain region, 6 ... Interlayer insulating layer, 7 ... Contact hole, 8 ... Signal line

Claims (1)

[Claims] 1. A source / drain region of a semiconductor film of a coplanar type thin film transistor including an active layer formed of a semiconductor film, a gate insulating layer, a gate electrode, and an interlayer insulating layer on an insulating substrate. In the method for manufacturing a coplanar thin film transistor, which includes a step of implanting impurity ions into a region corresponding to the step 1, and a step of activating the impurity ions, the maximum temperature in the manufacturing process is 350 ° C. to 600 ° C. The gate electrode is made of at least MoTa alloy or Mo.
The source / drain region of the source / drain region is formed by including a layer formed of a W alloy as a material, and forming the interlayer insulating layer or another insulating film in the interlayer insulating layer so as to cover at least the gate electrode. A method of manufacturing a coplanar thin film transistor, comprising the step of activating.