JPH11284191A - Vertical thin film transistor and method of manufacturing the same - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To provide a TFT capable of improving on-current by forming a channel in consideration of a crystal structure of a polycrystalline semiconductor film formed from an amorphous semiconductor film and a method of manufacturing the same. . SOLUTION: In a TFT1, a channel forming region 3 is provided.
Is composed of a polycrystalline semiconductor film 301 having a columnar structure formed by a crystallization process on an amorphous semiconductor film and having a column axis A directed in an out-of-plane direction of the substrate 8. Gate electrode 7 is formed of polycrystalline semiconductor film 3 forming channel formation region 3.
01 faces the side surface 302 substantially parallel to the column axis A via the gate insulating film 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive
The present invention relates to a thin film transistor (hereinafter, referred to as a TFT) used for driving an element, driving a sensor, and the like, and a method for manufacturing the same. More specifically, the present invention relates to a vertical TFT.

[0002]

2. Description of the Related Art In an active matrix substrate of a liquid crystal display device, as shown in FIG. 6A, a data line 90 made of a conductive film such as aluminum or tantalum is formed on a transparent substrate.
In addition, a pixel area defined by the scanning lines 91 is formed, and a liquid crystal capacitor 94 (liquid crystal cell) to which an image signal is input via the pixel switching TFT 30 exists. For the data line 90, the shift register 8
4, a data side drive circuit 82 including a level shifter 85, a video line 87, and an analog switch 86 is configured. For the scanning line 91, a scanning side driving circuit 83 including a shift register 88 and a level shifter 89 is configured. Note that a storage capacitor 93 is formed between the pixel region and the preceding scanning line 91, and this storage capacitor 93
The liquid crystal capacitor 94 has a function of improving charge retention characteristics.

As shown in FIG. 6B, an N-type TFT 10 and a P-type TF
A complementary TFT circuit is constituted by T20.
Such a complementary TFT circuit constitutes a shift register or the like with one stage or two or more stages.

The TFTs 10 and 20 for such a driving circuit
7 is similar to the pixel switching TFT 30 shown in FIG.
As shown in (A) and (B), gate insulation is provided on the surface of the island-shaped silicon film 5A constituting the first source / drain region 2A, the channel formation region 3A, and the second source / drain region 4A. A film 6A is formed, and a gate electrode 7A formed on the surface of the gate insulating film 6A faces the channel forming region 3A via the gate insulating film 6A.

When manufacturing the TFT 1A having such a structure, a polycrystalline silicon film 5A (semiconductor film) formed on a substrate 8A is used. That is, in order to increase the operation speed of the drive circuit, it is necessary that the operation speed of the TFT be high. Therefore, a polycrystalline silicon film having high mobility is formed by using a high-temperature process,
Form FT. Therefore, conventionally, it is necessary to use expensive quartz glass that can withstand a high-temperature process as the substrate 8A, and there is a problem that an inexpensive glass substrate having a low strain point cannot be used.

Therefore, a polycrystalline silicon film having high mobility can be formed on an inexpensive glass substrate having a low strain point.
A low-temperature process of forming an amorphous silicon film on a substrate, subjecting the amorphous silicon film to crystallization treatment such as laser annealing, and melting and solidifying the amorphous silicon film to grow crystal grains has been studied.

[0007]

However, when the crystal grains of the silicon film are grown by such a crystallization process,
The silicon film is deposited in the film deposition direction during film formation,
The polycrystalline semiconductor film has a columnar structure in which the column axis is oriented in a direction perpendicular to A. In the channel length direction (the direction indicated by the arrow CH), the channel is a grain boundary (shown by a vertical line B in the channel forming region 3A). .). As a result, even if the crystallinity of the silicon film is increased, TF
There is a problem that the ON current of T1A is not sufficiently improved.

[0008] In view of the above problems, an object of the present invention is to provide:
An object of the present invention is to provide a TFT capable of improving on-state current by forming a channel in consideration of a crystal structure of a polycrystalline semiconductor film formed from an amorphous semiconductor film, and a method for manufacturing the same.

[0009]

According to the present invention, a channel is formed on a substrate between a first region serving as one of source / drain regions and a second region serving as the other. A thin film transistor including a channel formation region and a gate electrode opposed to the channel formation region with a gate insulating film interposed therebetween has a vertical structure. That is, the channel formation region is formed of a polycrystalline semiconductor film having a columnar structure formed by a crystallization process on an amorphous semiconductor film and directing a column axis in an out-of-plane direction of the substrate, and the gate electrode is formed in the channel formation region. A side end surface of the polycrystalline semiconductor film constituting the semiconductor device, which is substantially parallel to the column axis, is opposed via the gate insulating film.

According to the present invention, a channel forming region is formed by a polycrystalline semiconductor film in which an amorphous semiconductor film is melt-solidified and crystal grains are grown by crystallization treatment such as laser annealing, electron beam annealing, lamp annealing, and solid phase growth. To form Therefore, in the channel formation region, a polycrystalline semiconductor film having a columnar structure in which the column axis is oriented in the film deposition direction at the time of forming the semiconductor film, that is, in the out-of-plane direction of the substrate. Nevertheless, in the present invention, the direction parallel to the column axis is the channel length direction because the gate electrode faces the side end surface of the polycrystalline semiconductor film parallel to the column axis. Therefore, the mobility of the carrier is high because the channel does not cross the grain boundary in the direction of the channel length. Therefore, in a TFT manufactured by a low-temperature process, on-current can be improved.

In the method of manufacturing a vertical thin film transistor having such a configuration, for example, a columnar structure in which an amorphous semiconductor film for forming the channel formation region is subjected to crystallization treatment so that a column axis is oriented in an out-of-plane direction of the substrate. After the polycrystalline semiconductor film is formed, the polycrystalline semiconductor film is patterned to expose a side end surface substantially parallel to a column axis, and thereafter, the gate insulating film and the gate electrode are sequentially formed (claim 5). ).

In the present invention, the first region and the second region may be, for example, a lower semiconductor film and an upper semiconductor formed respectively on a lower layer and an upper layer of a polycrystalline semiconductor film constituting the channel forming region. It is composed of a film (claim 2). In this case, it is preferable that the polycrystalline semiconductor film constituting the channel forming region and the upper semiconductor film have the same patterning shape (claim 3). When manufacturing a vertical thin film transistor having such a configuration, after forming the semiconductor film for forming the channel formation region and the upper semiconductor film in this order, the two semiconductor films are collectively patterned. Thus, it is preferable to reduce the number of manufacturing steps (claim 6).

In the present invention, when the polycrystalline semiconductor film forming the channel forming region has a channel forming side end surface located on the lower layer side semiconductor film forming region, the polycrystalline semiconductor film is formed. It is preferable to have an insulating film slightly interrupted between these films between the side end surface of the semiconductor device and the lower semiconductor film (claim 4). That is,
After forming the lower semiconductor film and the insulating film in this order, the polycrystalline semiconductor film for forming the channel forming region is formed on the entire surface of the substrate, and thereafter, the polycrystalline semiconductor film is formed using the insulating film as an etching stopper. It is preferable to pattern the semiconductor film (claim 7).

[0014]

Embodiments of the present invention will be described with reference to the drawings. In each embodiment, FIG.
TFT for driving liquid crystal display device described with reference to FIG.
As an example, the TFT according to the present invention can be used in various fields such as EL element driving and sensor driving.

Embodiment 1 FIGS. 1A and 1B are a sectional view and a plan view of a TFT to which the present invention is applied, respectively.

1A and 1B, a TFT 1 according to the present embodiment is a TFT for a driving circuit formed by a low-temperature process on a substrate 8 made of a glass plate as a base of a liquid crystal panel. The TFT 1 has a channel forming region 3 forming a channel between the first source / drain region 2 and the second source / drain region 4, and a gate insulating film 6 with respect to the channel forming region 3. The point that it has the gate electrode 7 facing the conventional TFT 1
Is the same as

However, in this embodiment, the first source / drain region 2, the channel formation region 3, and the second source / drain region 2
The drain region 4 includes a lower semiconductor film 201 such as a doped silicon film formed on the surface of the substrate 8, a polycrystalline semiconductor film 301 such as a polycrystalline silicon film laminated on the surface of the lower semiconductor film 201, And an upper semiconductor film 401 such as a doped silicon film laminated on the surface of the polycrystalline semiconductor film 301. In the polycrystalline semiconductor film 301 constituting the channel formation region 3, the side end surfaces 302 and 402 are located on the lower semiconductor film 201, similarly to the upper semiconductor film 401. Here, the polycrystalline semiconductor film 30 forming the channel formation region 3
1 between the side end surface 302 and the lower semiconductor film 201.
An insulating film 9 for an etching stopper which is slightly interrupted between these films is formed.

A gate insulating film 6 made of a silicon oxide film or the like is formed on the surface of the upper semiconductor 401 serving as the second source / drain region 4, and this gate insulating film 6
The side end surface 302 of the polycrystalline semiconductor film 301 constituting the channel formation region 3 is covered. In this embodiment, the gate electrode 7 formed on the surface of the gate insulating film 6 faces the side end surface 302 of the polycrystalline semiconductor film 301 forming the channel formation region 3 via the gate insulating film 6.

An interlayer insulating film 11 made of a silicon oxide film or the like is formed on the surface side of the gate electrode 7, and the first insulating film 11 is formed through contact holes 111 and 112 of the interlayer insulating film 11.
The first source / drain electrode 12 and the second source / drain electrode 13 are electrically connected to the source / drain region 2 and the second source / drain region 4, respectively.

When a high-temperature process is used to manufacture the vertical TFT 1 configured as described above, it is necessary to use expensive quartz glass that can withstand the high-temperature process as the substrate 8. A low temperature process is employed so that a glass substrate can be used. Therefore, in the TFT 1 of the present embodiment, the channel forming region 3 is formed by forming an amorphous semiconductor film on the substrate 8 and then performing laser annealing, electron beam annealing, lamp annealing, and solid phase growth on the amorphous semiconductor film as described later. It is formed of a polycrystalline semiconductor film 301 obtained by performing a crystallization process such as the above. This polycrystalline semiconductor film 301
Has a columnar structure in which a column axis (indicated by an arrow A) is oriented in a film deposition direction during film formation, that is, in an out-of-plane direction of the substrate 8 in a process of melting and solidifying an amorphous semiconductor film to grow crystal grains. Will be. In this columnar structure, in order to indicate that the column axis A is perpendicular to the substrate 8, in FIG. 1A, a grain boundary is formed in the channel forming region 3 (polycrystalline semiconductor film 301) by a vertical line B. It is represented by

In this embodiment, in accordance with such a crystal structure, the polycrystalline semiconductor film 30 forming the channel formation region 3 is formed.
1 is perpendicular to the substrate 8,
The gate electrode 7 faces the gate electrode 02 via the gate insulating film 6. Therefore, when a gate potential is applied to the gate electrode 7, a channel is formed on the side end surface 302 of the polycrystalline semiconductor film 301 constituting the channel formation region 3, and the direction of the channel length at this time (indicated by an arrow CH) Direction) is parallel to the column axis A of the polycrystalline semiconductor film 301.
Therefore, in the direction of the channel length CH, the channel does not cross the grain boundary B, so that the carrier mobility is high. Therefore, TF manufactured by low temperature process
At T1, the on-current can be improved.

The method of manufacturing the TFT 1 having such a structure is described below.
This will be described with reference to FIGS. 2 and 3
Is a process sectional view illustrating the method for manufacturing the TFT 1 of this embodiment.

First, as shown in FIG. 2A, an impurity such as phosphorus or boron is doped on the entire surface of the substrate 8 for about 10 ¹⁸ c.
m ^-3 ~ about 10 ²⁰ cm ^-3 approximately containing doped silicon film of several to a thickness of several 100 Å semiconductor film such that μ
After the formation of m, it is patterned into an island shape to form the first source / drain region 2 (the lower semiconductor film 201). The doped semiconductor film may be formed as a polycrystalline semiconductor film or may be obtained by crystallizing an amorphous semiconductor film.

Next, as shown in FIG. 2B, an insulating film such as a silicon oxide film or a silicon nitride film is formed on the entire surface of the substrate 8 by a sputtering method, a CVD method, a vapor deposition method or the like.
The insulating film is patterned to leave an insulating film 9 for an etching stopper that partially overlaps the first source / drain region 2 (lower semiconductor film 201).

Next, as shown in FIG. 2C, an amorphous semiconductor film 300 such as an amorphous silicon film having a thickness of about 500 Å to several μm is formed. If an amorphous silicon film is used as the amorphous semiconductor film 300, a plasma CVD method, an LPCVD method,
There are methods such as a vapor deposition method and a sputtering method. Plasma CVD
In the case of the method, a film can be formed at a temperature of 350 ° C. or less. LPC
In the case of the VD method, the deposition temperature differs depending on the source gas, and a film can be formed at a temperature of about 450 ° C. or less when disilane (Si ₂ H ₆ ) gas is used and at a temperature of about 560 ° C. or less when silane (SiH ₄ ) gas is used. It is. In the case of a vapor deposition method or a sputtering method, a film can be formed at a temperature of about 250 ° C. or less. Here, by adding phosphorus or boron at a low concentration as the amorphous semiconductor film 300, channel doping may be performed to adjust the threshold voltage of the TFT1.

Next, the amorphous semiconductor film 300 is subjected to crystallization treatment such as laser annealing, electron beam annealing, lamp annealing, or solid-phase growth, so that the amorphous semiconductor film 300 becomes a polycrystalline semiconductor film. In the laser annealing method, for example, a line beam having an excimer laser beam length of 400 mm is used, and its output intensity is, for example, 200 mJ / cm ² . For the line beam, the peak value of the laser intensity in the width direction is 90%.
The line beam is scanned so that a portion corresponding to% overlaps each region. In this crystallization process, the amorphous semiconductor film 300 is melted and solidified, and crystal grains grow to form a polycrystalline semiconductor film. This polycrystalline semiconductor film has a columnar crystal structure (columnar structure) in which the column axis A is oriented in a direction perpendicular to the substrate 8.

Next, as shown in FIG. 2D, the polycrystalline semiconductor film is patterned to form a polycrystalline semiconductor film 301 constituting the channel formation region 3. Here, patterning is performed so that the side end face 302 of the polycrystalline semiconductor film 301 is located on the etching stopper insulating film 9 formed on the surface of the first source / drain region 2 (the lower semiconductor film 201). I do. The insulating film 9 for an etching stopper prevents the lower semiconductor film 201 constituting the first source / drain region 2 from being over-etched when the polycrystalline semiconductor film 301 is formed by patterning. When the polycrystalline semiconductor film 301 is formed by patterning in this manner, the end of the insulating film 9 for the etching stopper is slightly interrupted between the side end surface 302 of the polycrystalline semiconductor film 301 and the lower semiconductor film 201. Becomes

Next, a doped semiconductor film containing about 10 ¹⁸ cm ^{-3 of} an impurity such as phosphorus or boron is formed on the entire surface of the substrate 8, and is patterned into an island shape. As shown in (2), a second source / drain region 4 (upper semiconductor film 401) is formed. The doped semiconductor film may be formed as a polycrystalline semiconductor film or may be obtained by crystallizing an amorphous semiconductor film.

Next, as shown in FIG. 3A, the entire surface of the substrate 8 is formed by a plasma CVD method, a CVD method, or a sputtering method using TEOS (tetraethoxysilane), oxygen gas or the like as a source gas. Is about 600-1500
A gate insulating film 6 made of an Angstrom silicon oxide film or the like is formed.

Next, a doped semiconductor film, a metal film (tantalum, chromium, aluminum, etc.),
After forming a conductive film such as a silicide film (such as tungsten silicide or molybdenum silicide), FIG.
Is patterned as shown in FIG.
A gate electrode 7 is formed on the side end surface 302 of the semiconductor device via the gate insulating film 6.

Next, after an interlayer insulating film 11 is formed on the entire surface of the substrate 8, as shown in FIG. 1A, it corresponds to the first source / drain region 2 and the second source / drain region 3. Contact holes 111 and 112 are formed at positions.

Then, a doped semiconductor film, a metal film (tantalum, chromium, aluminum, etc.)
After a conductive film such as a silicide film (such as tungsten silicide or molybdenum silicide) is formed, the first source / drain electrode 12 and the second source / drain electrode 13 are formed by patterning.

According to such a manufacturing method of the TFT 1,
Since the TFT 1 can be manufactured by a low-temperature process, an inexpensive glass substrate can be used as the substrate 8.
Further, the polycrystalline semiconductor film 3 forming the channel formation region 3
01 is patterned into an island shape,
Since the insulating film 9 for an etching stopper is formed in advance in a layer below the position corresponding to the above, the lower semiconductor film 201 constituting the first source / drain region 2 is not over-etched.

Embodiment 2 FIGS. 4A and 4B are a sectional view and a plan view of a TFT to which the present invention is applied, respectively. Note that the TFT of this embodiment and a method of manufacturing the same are
Since the basic configuration is the same as that of the first embodiment, common portions are denoted by the same reference numerals and are shown in the drawings, and description thereof is omitted.

4A and 4B, the TFT 1 according to the present embodiment also has a first source / drain region 2, a channel formation region 3, and a second source / drain region similarly to the first embodiment. 4 is a lower semiconductor film 201 such as a doped silicon film formed on the surface of the substrate 8;
A polycrystalline semiconductor film 301 such as a polycrystalline silicon film laminated on the surface of the lower semiconductor film 201 and an upper semiconductor film 401 such as a doped silicon film laminated on the surface of the polycrystalline semiconductor film 301 Have been.

In manufacturing the vertical TFT 1 configured as described above, the channel forming region 3 is formed by subjecting the amorphous semiconductor film to crystallization treatment such as laser annealing, electron beam annealing, lamp annealing, and solid phase growth. It is formed of the obtained polycrystalline semiconductor film 301. The column axis (indicated by an arrow A) of the polycrystalline semiconductor film 301 in the film deposition direction at the time of film formation, that is, in the out-of-plane direction of the substrate 8 during the process of melting and solidifying the amorphous semiconductor film to grow crystal grains. Will have a columnar structure that faces. In this columnar structure, in order to indicate that the column axis A is perpendicular to the substrate 8, in FIG. 1A, a grain boundary is formed in the channel forming region 3 (polycrystalline semiconductor film 301) by a vertical line B. It is represented by

In this embodiment, in accordance with such a crystal structure, the polycrystalline semiconductor film 30 forming the channel formation region 3 is formed.
1 is perpendicular to the substrate 8,
The gate electrode 7 faces the gate electrode 02 via the gate insulating film 6. Therefore, the direction of the channel length (the direction indicated by the arrow CH) is parallel to the column axis A of the polycrystalline semiconductor film 301. Therefore, in the direction of the channel length CH, the channel does not cross the grain boundary B, so that the carrier mobility is high. Therefore, in the TFT 1 manufactured by the low-temperature process, the on-current can be improved.

In the method of manufacturing the TFT 1 having such a configuration, as described below, the polycrystalline semiconductor film 301 forming the channel formation region 3 and the upper semiconductor film forming the second source / drain region 4 Since the substrate 401 and the substrate 401 are collectively patterned, they have the same patterning shape.

A method of manufacturing the TFT 1 according to this embodiment will be described with reference to FIG. FIG. 5 is a process sectional view illustrating the method for manufacturing the TFT 1 of the present embodiment.

First, as shown in FIG. 5A, an impurity such as phosphorus or boron is doped on the entire surface of the substrate 8 for about 10 ¹⁸ c.
After a semiconductor film such as a doped silicon film containing about m ⁻³ is formed, the semiconductor film is patterned into an island shape to form a first source / drain region 2 (lower semiconductor film 201).

Next, as shown in FIG. 5B, an insulating film such as a silicon oxide film or a silicon nitride film is formed on the entire surface of the substrate 8 by a sputtering method, a CVD method, a vapor deposition method, etc.
The insulating film is patterned to leave an insulating film 9 for an etching stopper.

Next, as shown in FIG. 5C, the temperature of the substrate 8 is set to, for example, 350 ° C., and the entire surface of the substrate 8 is formed by plasma CVD, LPCVD, vapor deposition, sputtering, or the like. Semiconductor film 30 such as an amorphous silicon film having a thickness of about 500 Å to several μm.
0 is formed.

Next, the amorphous semiconductor film 300 is subjected to a crystallization process such as laser annealing, electron beam annealing, lamp annealing, or solid-phase growth, so that the amorphous semiconductor film 300 becomes a polycrystalline semiconductor film 300B. In the laser annealing method, for example, a line beam having an excimer laser beam length of 400 mm is used, and its output intensity is, for example, 200 mJ / cm ² . The line beam is scanned such that a portion corresponding to 90% of the peak value of the laser intensity in the width direction overlaps in each region. In this crystallization process, the amorphous semiconductor film 300 is melted and solidified, and crystal grains grow to form the polycrystalline semiconductor film 300B. The polycrystalline semiconductor film 300B has a columnar crystal structure (columnar structure) in which the column axis A is oriented in a direction perpendicular to the substrate 8.

Next, as shown in FIG. 5D, an impurity such as phosphorus or boron is doped on the entire surface of the substrate 8 for about 10 ¹⁸ c.
A doped semiconductor film 400 containing about m ⁻³ is formed.
As a result, the doped semiconductor film 400 becomes the polycrystalline semiconductor film 300B after the crystallization of the amorphous semiconductor film 300.
In a state of being stacked.

Next, a resist mask RM is formed on the surface of the doped semiconductor film 400.

Then, the doped semiconductor film 400 and the polycrystalline semiconductor film 300B are collectively patterned using the resist mask RM, and the polycrystalline semiconductor film forming the channel formation region 3 is formed as shown in FIG. 301 and the second source / drain region 4 (the upper semiconductor film 40
Leave 1). Also in this case, the side end surface 302 of the polycrystalline semiconductor film 301 is positioned above the etching stopper insulating film 9 formed on the surface of the first source / drain region 2 (the lower semiconductor film 201). Perform patterning. The insulating film 9 for the etching stopper is used for forming the first source / drain region 2 when forming the second source / drain region 4 (upper semiconductor film 401) and the polycrystalline semiconductor film 301 by patterning. The semiconductor film 201 is prevented from being over-etched.

Since the subsequent steps are the same as in the first embodiment,
Although the description is omitted, according to the present embodiment, the TFT 1 can be manufactured by a low-temperature process, so that an inexpensive glass substrate can be used as the substrate 8. Since the polycrystalline semiconductor film 301 that forms the formation region 3 and the upper semiconductor film 401 that forms the second source / drain region 4 are collectively patterned, the patterning process is one process longer than in the first embodiment. It has the advantage of requiring less.

[Other Embodiments] In the above embodiment, the silicon film is used as the semiconductor film.
The present invention may be applied to a TFT using a semiconductor film such as germanium or silicon-germanium.

[0049]

As described above, according to the present invention, since the gate electrode faces the side end surface parallel to the column axis of the polycrystalline semiconductor film obtained from the amorphous semiconductor film by the crystallization treatment, The direction parallel to the axis is the direction of the channel length. Therefore, the mobility of the carrier is high because the channel does not cross the grain boundary in the direction of the channel length. Therefore, TF manufactured by low temperature process
At T, the ON current can be improved.

[Brief description of the drawings]

FIGS. 1A and 1B are a cross-sectional view and a plan view, respectively, of a TFT according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing a method for manufacturing the TFT shown in FIG.

3 is a process cross-sectional view showing each process performed after the process shown in FIG. 2 in the method of manufacturing the TFT shown in FIG. 1;

FIGS. 4A and 4B are a cross-sectional view and a plan view, respectively, of a TFT according to a second embodiment of the present invention.

5 is a process sectional view illustrating the method of manufacturing the TFT shown in FIG.

FIGS. 6A and 6B are a block diagram of an active matrix substrate of a liquid crystal display device and a circuit diagram showing a part of a driving circuit configured therein, respectively;

FIGS. 7A and 7B are a cross-sectional view and a plan view of a conventional TFT, respectively.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 TFT 2 first source / drain region 3 channel formation region 4 second source / drain region 6 gate insulating film 7 gate electrode 8 substrate 9 insulating film for etching stopper 11 interlayer insulating film 12 first source / drain electrode 13 Second Source / Drain Electrode 201 Lower Semiconductor Film 301 Polycrystalline Semiconductor Film 302 Side End Surface of Polycrystalline Semiconductor Film 401 Upper Semiconductor Film A Column Axis of Polycrystalline Semiconductor Film B Grain Boundary CH Channel Length Direction

Claims (7)

[Claims] 1. A channel forming region for forming a channel between a first region serving as one of source / drain regions and a second region serving as the other on a substrate, and a gate insulating film for the channel forming region. A thin film transistor having a gate electrode facing each other, wherein the channel forming region is formed by a polycrystalline semiconductor film having a columnar structure formed by a crystallization process on an amorphous semiconductor film and directing a column axis in an out-of-plane direction of the substrate. A vertical thin film transistor, wherein the gate electrode is opposed to a side end surface of the polycrystalline semiconductor film constituting the channel formation region, which is substantially parallel to a column axis, via the gate insulating film. 2. The semiconductor device according to claim 1, wherein the first region and the second region are a lower semiconductor film and an upper layer formed on a lower layer side and an upper layer side of a polycrystalline semiconductor film forming the channel formation region, respectively. A vertical thin film transistor comprising a semiconductor film. 3. The vertical thin film transistor according to claim 2, wherein the polycrystalline semiconductor film forming the channel forming region and the upper semiconductor film have the same patterning shape. 4. The method according to claim 1, wherein
In the polycrystalline semiconductor film forming the channel formation region, a side end surface forming a channel is located on a formation region of the lower semiconductor film, and between a side end surface of the polycrystalline semiconductor film and the lower semiconductor film. A thin film transistor having an insulating film slightly interrupted between these films. 5. The method for manufacturing a vertical thin film transistor according to claim 1, wherein the amorphous semiconductor film for forming the channel formation region is crystallized to form a column in an out-of-plane direction of the substrate. After forming a columnar-structured polycrystalline semiconductor film oriented toward an axis, the polycrystalline semiconductor film is patterned to expose a side end surface substantially parallel to the column axis, and thereafter, the gate insulating film and the gate electrode are sequentially formed. A method for manufacturing a vertical thin film transistor. 6. The method for manufacturing a vertical thin film transistor according to claim 3, wherein the semiconductor films for forming the channel forming region and the upper semiconductor film are formed in this order, and then the two semiconductors are formed. A method for manufacturing a vertical thin film transistor, wherein a film is patterned at once. 7. The method of manufacturing a vertical thin film transistor according to claim 4, wherein the channel forming region is formed on the entire surface of the substrate after the lower semiconductor film and the insulating film are formed in this order. A method for manufacturing a vertical thin film transistor, comprising: forming a polycrystalline semiconductor film; and thereafter, patterning the polycrystalline semiconductor film using the insulating film as an etching stopper.