JPH0936718A - Differentiation circuit and timing extract circuit using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differentiation circuit and a timing extract circuit offering ease of manufacture with high accuracy which is operated by a single power supply and the connection of a delay circuit to ground is not required. SOLUTION: Upon receipt of input signals IN1, IN2, they are differentially amplified by an input buffer 12. A 1st signal S12 in 1st and 2nd complementary signals S1, S2 outputted from the input buffer 12 is delayed by a fixed delay circuit 13, from which a 1st delay signal S12a is generated. The 2nd signal S12B is delayed by a fixed delay circuit 13, from which a 2nd delay signal S12Ba is generated. The 1st signal S12 and the 2nd delay signals S12Ba are added and a 1st differentiation wave S13 is generated, The 2nd signal S12B and the 1st delay signal S12a are added to generate the 2nd differentiation waveform S13B. The differentiation waves S13, S13B are given to an output buffer 14, from which output signals OUT1, OUT2 are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differentiating circuit used in an optical transmitter, an optical receiver, etc., and a timing extracting circuit for extracting a clock component from input data by using the differentiating circuit. , And a multiplier for multiplying the reference clock signal is included).

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, some documents were described in the following documents. Reference: Proceedings of the 1991 IEICE Autumn Meeting C-
418, Kikuchi et al. "10 Gb / s GaAs-MESFET Timing Extraction IC" P. 5-132 Generally, in an optical transmission system, an optical transmission terminal device is provided at one end of an optical transmission line, a plurality of lines having a low transmission speed are multiplexed, and an optical signal having a higher transmission speed is transmitted to the optical transmission line. . The multiplexing is usually performed with reference to a clock signal obtained by multiplying a reference clock signal supplied to the optical transmission terminal device by a clock signal at the transmission speed of the optical signal sent to the optical transmission line. In order to multiply the clock signal, it is necessary to generate and rectify the differential waveform of the reference clock signal. When an input data signal is identified and reproduced in an optical receiver, it is usually performed by latching an equalized data signal with a predetermined clock signal.
The input signal is an RZ (Return to Zero) code,
If the signal has a clock component, the clock component can be easily extracted by passing it through a filter.
However, recently, the code format of the input data signal is NR.
It is in the direction of being standardized to Z (Non Return to Zero) code, and in order to extract the clock component, a non-linear circuit that differentiates the input data signal and returns it is necessary. For example,
A conventional optical receiver, particularly an optical receiver operating at a high speed of about Gb / s, employs a differentiating circuit as described in the above-mentioned document.

FIG. 2 is a block diagram showing the configuration of a conventional differentiating circuit described in the above document. This differentiating circuit is composed of an input buffer 1, fixed delay circuits 2 and 3, and an output buffer 4. The input buffer 1 is a circuit that inputs a complementary input signal IN and an inverted input signal INB. Of the two output signals of the input buffer 1, one output signal S1 is delayed by one fixed delay circuit 2 for a predetermined time to become a signal S2a, and the signal S2a is inverted at the ground to become a signal S2b. This signal S2b is again delayed by the fixed delay circuit 2 to become the signal S2c, and the input buffer 1
Of the output signal S1 of FIG. The differential waveform S2 is input to the output buffer 4, and the output signal OUT is output from the output buffer 4. The other output signal of the input buffer 1 is the fixed delay circuit 3 as described above.
Is connected to the ground via the output buffer 4
Is connected to the other input side, and the inverted output signal OUTB is output from the other output side of the output buffer 4.

FIG. 3 is a signal waveform diagram for explaining the operation of the differentiating circuit shown in FIG. The operation of FIG. 2 will be described with reference to this signal waveform diagram. When the input signal IN is input to the input buffer 1, the signal S1 is input from the input buffer 1.
Is output. The fixed delay circuit 2 has one end connected to the output side of the output buffer 1 and the other end terminated with a ground, and is formed of a transmission line having a delay time τ / 2. Therefore, the signal S1 propagates through the fixed delay circuit 2 to become the signal S2a delayed by the delay time τ / 2, and the signal S2a is logically inverted on the ground side to become the signal S2b. Signal S2
The signal b is propagated through the fixed delay circuit 2 again and becomes the signal S2c delayed by the delay time τ / 2. This signal S2c is the signal S
1 is delayed by a delay time τ, and this signal S2c
And the signal S1 are added, and the signal S1 having the pulse width τ
The differential waveform S2 of is obtained. The differential waveform S2 is input to the output buffer 4, and the output signal OU is output from the output buffer 4.
T is output. Similarly, when the inverted input signal INB is input to the input buffer 1, the output buffer 4 outputs the inverted output signal OUTB having the inverted logical waveform of the differential waveform S2. These output signals OUT and OUTB are necessary when a rectifying circuit such as a mixer circuit is connected in the subsequent stage.

A timing extraction circuit can be constructed by connecting a rectifying circuit such as a mixer circuit to the output side of the output buffer 4 after the differentiating circuit shown in FIG. Output buffer 4
If you rectify the output signals OUT and OUTB of
A rectified signal S5 having a waveform as shown in FIG. 3 is obtained, and a clock component is generated. The clock component A generated by Fourier transforming the waveform of the rectified signal S5 is
With pulse width τ and pulse width T0 corresponding to 1 bit period,
It is expressed by the following equation (1).

[Equation 1] Therefore, if the pulse width τ is designed under the condition of the equation (2), the maximum clock component can be obtained.

[Equation 2]

[0006]

However, the conventional differentiating circuit and the timing extracting circuit using the same have the following problems (a) to (c), and it is difficult to solve them. It was (A) In the conventional circuit, 2 is provided on the output side of the input buffer 1.
One ends of the two fixed delay circuits 2 and 3 are connected, and the other ends of the fixed delay circuits 2 and 3 are terminated to the ground.
Therefore, it is necessary to design the bias potential of the input buffer output to be equal to the ground. That is, in order to operate the input buffer 1, two power sources, plus and minus, are required. (B) The fixed delay circuits 2 and 3 are composed of, for example, a coplanar line or a microstrip line, but since these lines cannot be directly terminated to the ground, they are terminated to the ground via a wire or the like. Become. However, when the line is connected to the ground through such a wire or the like, reactance or the like occurs when a high frequency signal flows through the wire or the like. Therefore, it is difficult to ground the other ends of the fixed delay circuits 2 and 3 to the ground with high frequency. (C) As can be seen from the equation (1), the fixed delay circuit 2,
When the propagation delay time τ / 2 of 3 does not meet the condition of the expression (2), the clock component decreases. Therefore, one cycle of the reference clock signal or one-bit cycle T0, that is, the propagation delay time τ / 2 of the fixed delay circuits 2 and 3 each time the transmission speed changes.
Must be designed. Moreover, high precision is required for manufacturing precision of the fixed delay circuits 2 and 3. The present invention provides a differentiating circuit and a timing extracting circuit using the differentiating circuit, which solves the problems of the prior art.

[0007]

In order to solve the above-mentioned problems, a first aspect of the present invention is a differential circuit which differentially amplifies first and second input signals to provide complementary first and second signals. A differential input buffer for input impedance matching (input impedance matching) that outputs a signal, a fixed delay circuit that generates first and second differential waveforms, and the first and second differential waveforms are input. And an output buffer for output impedance matching that outputs first and second output signals. Here, the fixed delay circuit delays the first signal by propagation for a predetermined time to generate a first delayed signal, and propagates the second signal in a direction opposite to the first signal by the predetermined time. Delaying to generate a second delayed signal, adding the first signal and the second delayed signal to generate a first differentiated waveform, and simultaneously generating the second signal and the first delay It is a circuit for adding a signal and generating a second differential waveform.

A second aspect of the present invention is a differential input buffer for input impedance matching, which differentially amplifies first and second input signals and outputs complementary first and second signals in a differentiating circuit. A variable delay circuit capable of adjusting a propagation delay time for generating first and second differential waveforms, and the first and second
And an output buffer for output impedance matching which inputs the differential waveform of and outputs the first and second output signals,
Have. Here, the variable delay circuit delays the first signal by a predetermined propagation delay time to generate a first delay signal, and at the same time, causes the second signal to move in the opposite direction to the first signal by the predetermined signal. A second delay signal is generated by delaying the second delay signal by adding the first delay waveform to the second delay signal, and a second differential signal is generated by adding the first delay signal to the second delay signal. It is a circuit for adding the first delay signal to generate a second differential waveform.

A third aspect of the present invention is the differential circuit of the second aspect, wherein the variable delay circuit has the propagation delay such that a duty of the rectified signal obtained by rectifying the first and second output signals is 50%. The time is adjustable. A fourth invention comprises, in a timing extraction circuit, a differentiating circuit of the first, second or third invention, and a rectifying circuit for rectifying the first and second output signals to output a rectified signal. ing. A fifth invention is a timing extraction circuit, wherein the differentiation circuit of the second invention and the differentiation circuit according to the first invention are provided.
And a rectifier circuit that rectifies the second output signal to output a rectified signal, and a low-voltage circuit that integrates the rectified signal and detects and outputs a voltage value corresponding to the pulse width of the first and second output signals. A band pass filter (hereinafter referred to as "LPF") and a comparison circuit are provided. The comparison circuit is a circuit that compares the output voltage value of the LPF and the voltage value of the variable reference voltage source and controls the propagation delay time of the variable delay circuit so that the duty of the rectified signal becomes 50%.

[0010]

According to the first and fourth aspects of the invention, since the differentiating circuit or the timing extracting circuit is configured as described above, when the first and second input signals are input, those input signals are input buffers. Differentially amplified by the complementary first
And a second signal is output. The first signal propagates from one end of the fixed delay circuit to the other end, and a first delay signal delayed by a predetermined delay time is generated. The second signal propagates from the other end of the fixed delay circuit toward the one end, and a second delay signal delayed by a predetermined delay time is generated. First
Signal and the second delay signal are added to generate a first differential waveform. The second signal and the first delay signal are added to generate the second differential waveform. These first and second differential waveforms are input to the output buffer, and the output buffer outputs the first and second output signals. When a rectifier circuit is provided on the output side of the output buffer, the output signal of the output buffer is rectified by the rectifier circuit. According to the differentiating circuit of the second and third inventions or the timing extracting circuit of the fourth invention, the propagation delay time can be adjusted by the variable delay circuit. According to the timing extraction circuit of the fifth invention, the output signal of the differentiating circuit is rectified by the rectifying circuit, the rectified signal is integrated by the LPF, and the voltage value corresponding to the pulse width of the first and second output signals is obtained. Is detected and sent to the comparison circuit. In the comparison circuit, LP
Comparing the output voltage value of F and the voltage value of the variable reference voltage source,
The propagation delay time of the variable delay circuit is controlled so that the duty ratio of the rectified signal output from the rectifier circuit becomes 50%.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram showing the configuration of a differentiating circuit showing a first embodiment of the present invention. This differentiating circuit has a first input signal IN
Input terminal 11-1 for inputting 1 and second input signal IN
2 is input, and those input terminals 11-1 and 11-2 are connected to the input side of the differential input buffer 12 for input impedance matching. The input buffer 12 has a first input signal IN1 and a second input signal IN1.
Differentially amplifying the input signal IN2 of the first input signal IN2 to obtain a complementary first signal S12 and a second signal S12B which is an inverted signal of the first signal S12,
It is a circuit that outputs from the non-inverting output side and the inverting output side, respectively. A fixed delay circuit 13 is connected between the non-inverting output side and the inverting output side of the input buffer 12, and one end and the other end of the fixed delay circuit 13 are connected to the non-inverting side of the output buffer 14 for output impedance matching. They are connected to the input side and the inverting input side, respectively.

The fixed delay circuit 13 is formed of a transmission line having a delay time τ, for example, and propagates and delays the first signal S12 of the first and second signals S12 and S12B output from the input buffer 12. The first delay signal S12a delayed by the time τ is generated, and the second signal S12B is propagated in the opposite direction to the first signal S12 to generate the second delay signal S12Ba delayed by the delay time τ. ,further,
The first signal S12 and the second delay signal S12Ba are added to generate the first differential waveform S13, and the second signal S12B and the first delay signal S12a are added and inverted to the second signal. It is a circuit for generating the differential waveform S13B.
The output buffer 14 inputs the first and second differential waveforms S13 and 13B from the non-inverting input side and the inverting input side, and outputs the first and second differential waveforms S13 and 13B.
The output signal OUT1 and the second output signal OUT2 are output to the output terminals 15-1 and 15-2. A timing extraction circuit can be configured by connecting a rectifier circuit to the output terminals 15-1 and 15-2. The rectifier circuit includes complementary first and second output signals OUT1, OUT.
2 is a circuit that rectifies 2 and outputs a complementary first rectified signal S16 and an inverted second rectified signal S16B.

FIG. 4 is a signal waveform diagram for explaining the operation of the differentiating circuit of FIG. 1 and the timing extracting circuit using it. The operation of FIG. 1 will be described below with reference to FIG. Input signals IN1 and IN2 are input terminals 11-1,
When input to 11-2, its input signals IN1 and IN2
Is differentially amplified by the input buffer 12, and the input buffer 1
2 outputs complementary first and second signals S12 and S12B. The first signal S12 propagates from one end of the fixed delay circuit 13 to the other end, and the first delay signal S12a delayed by the delay time τ is output from the other end of the fixed delay circuit 13. The second signal S12B propagates from the other end of the fixed delay circuit 13 toward the one end, and the delay time τ
The second delay signal S12Ba delayed by the above is output from one end of the fixed delay circuit 13. Then, the first signal S1
2 and the second delay signal S12Ba are added, and the first differential waveform S13 is generated and sent to the non-inverting input side of the output buffer 14. Further, the second signal S12B and the first delay signal S12a are added, and the second differential waveform S13 is obtained.
B is generated and sent to the inverting input side of the output buffer 14. The output buffer 14 receives the complementary first and second differential waveforms S13 and S13B, and outputs the complementary first and second output signals OUT1 and OUT2 to the output terminals 15-1 and 15.
Output to 15-2. These output signals OUT1 and OUT2
Is rectified by a rectifier circuit (not shown), so that the first and second rectified signals S16 and S16 as shown in FIG.
B is obtained and a clock component is generated.

As described above, the first embodiment has the following effects (a) to (c). (A) In the conventional differentiation circuit, two fixed delay circuits 2,
One end of 3 is connected to the ground. On the other hand, in the first embodiment, two conventional fixed delay circuits 2 and 3 are used.
Since one fixed delay circuit 13 in which the ground connection sides are integrated is provided and the circuit is virtually grounded in the middle of the fixed delay circuit 13 due to the left-right symmetry peculiar to the differential circuit. It becomes unnecessary to design the bias potentials on the output side of the input buffer 12 and the input side of the output buffer 14 to be equal to the ground. Therefore, a single power supply circuit can be configured, and the circuit configuration is simplified. Further, in the conventional fixed delay circuits 2 and 3, when it is formed of, for example, a coplanar line or a microstrip line, it is difficult to ground one end of them to the ground at high frequency. However, since the fixed delay circuit 13 of the first embodiment does not need to be grounded as in the conventional case, a highly accurate differentiating circuit can be easily manufactured. (B) Since the intermediate point of the fixed delay circuit 13 is electrically determined, the physical lengths of the two fixed delay circuits 2 and 3 formed of, for example, transmission lines are adjusted to be the same as in the conventional case. There is no need. Therefore, there is little variation,
An accurate differentiating circuit can be easily manufactured. (C) Since the bias points of the output of the fixed delay circuit 13 can be made equal, adverse effects such as deterioration of the suppression ratio due to the input offset of the rectifier circuit such as the mixer circuit connected to the output terminals 15-1 and 15-2 are reduced. be able to.

Second Embodiment FIG. 5 is a block diagram showing the configuration of a differentiating circuit according to the second embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are common to those elements. Is attached. This differentiating circuit has a configuration in which the fixed delay circuit 13 in the differentiating circuit of the first embodiment is replaced with a variable delay circuit 23, and the other parts have the same circuit configuration as the first embodiment. The variable delay circuit 23 has a configuration in which the propagation delay time τ can be adjusted using a variable reactance, a variable capacitor, or the like. Further, the variable delay circuit 23 outputs the output signals OUT1 and OU.
Propagation delay time τ so that the duty is 50% in the rectified signals S16 and S16B obtained by rectifying T2 by the rectifier circuit.
It has a circuit configuration that can be adjusted.

Next, the operation will be described. This differentiator circuit
Similar to the differentiation circuit of FIG. 1, the first signal S12 output from the input buffer 12 is propagated through the variable delay circuit 23 to generate the first delay signal S12a delayed by the delay time τ, and further, The second signal S12B is replaced with the first signal S1.
It propagates through the variable delay circuit 23 in the direction opposite to 2, and generates the second delay signal S12Ba delayed by the delay time τ.
Then, the first signal S12 and the second delay signal S12Ba
Are added to generate the first differential waveform S13, and the second signal S12B and the first delay signal S12a are added to generate the second differential waveform S13B. The first and second differential waveforms S13 and S13B are input to the output buffer 14, and the output buffer 14 outputs the output signals OUT1 and OUT2. At this time, the maximum clock component can be extracted by adjusting the delay time τ of the variable delay circuit 23 so as to satisfy the condition of the expression (2) and rectifying the output signals OUT1 and OUT2 by a rectifier circuit (not shown). .

As described above, the second embodiment has substantially the same effects as the effects (a) to (c) of the first embodiment, and the following (d) and (e) There is also such an effect. (D) If a rectifier circuit is connected to the output terminals 15-1 and 15-2 and input data signals are input as the input signals IN1 and IN2, if the transmission speed is different or the propagation delay time τ of the delay circuit is Even if the accuracy is insufficient, the maximum clock component can be extracted from the input data signal by adjusting the delay time τ of the variable delay circuit 23. (E) If the input data signal in (d) is replaced with a clock signal, a clock signal corresponding to twice the frequency of the input clock signal can be extracted in the same manner as described above, and can be used as a multiplier. Is.

Third Embodiment FIG. 6 is a block diagram of a timing extraction circuit showing a third embodiment of the present invention. Elements common to those in FIG. 5 showing the second embodiment are common to those elements. Is attached. This timing extraction circuit has the differentiating circuit shown in FIG. 5, the rectifying circuit 24 is connected to the output side thereof, and the output terminal 25 is further connected to the output side of the rectifying circuit 24. Further, the output terminal 25 is connected to the LPF 26, and the output side thereof is connected to the comparison circuit 30, and the output side of the comparison circuit 30 is connected to the delay control terminal of the variable delay circuit 23. The rectifier circuit 24 rectifies the complementary first and second output signals OUT1 and OUT2 of the output buffer 14 to obtain a rectified signal S24.
Is output to the output terminal 25, and includes, for example, an input buffer, a signal distribution circuit, a multiplier, and an output buffer. The LPF 26 is a filter that integrates the rectified signal S24 and detects and outputs a voltage value corresponding to the pulse width of the first and second output signals OUT1 and OUT2. The comparison circuit 30 is a circuit that compares the output voltage value of the LPF 26 with the voltage value of the variable reference voltage source 34 and controls the propagation delay time τ of the variable delay circuit 23 so that the duty of the rectified signal S24 becomes 50%. . This comparison circuit 3
Reference numeral 0 is composed of resistors 31 and 32, a variable reference voltage source 34, and an operational amplifier (hereinafter, referred to as “op amp”) 33. The inverting input side of the operational amplifier 33 is connected to the output side of the LPF 26 via the resistor 31, and the resistor 3
It is connected to the output side of the operational amplifier 33 via 2. The non-inverting input side of the operational amplifier 33 is connected to the ground via the variable reference voltage source 34. The output side of the operational amplifier 33 is connected to the delay control terminal of the variable delay circuit 23.

Next, the operation will be described. Similar to the differentiating circuit of FIG. 5, input signals IN1 and IN2 are input terminals 11-1 and
When input to 11-2, its input signals IN1 and IN2
Is differentially amplified by the input buffer 12, and complementary first and second signals S12 and S12B are output. The first and second signals S12 and S12B are delayed by the delay time τ in the variable delay circuit 23, and the first and second differential waveforms S1.
3, S13B is generated. The first and second differential waveforms S13 and S13B are input to the output buffer 14, and the first and second output signals OUT are output from the output buffer 14.
1, OUT2 are output. First and second output signal O
The UT1 and OUT2 are rectified by the rectification circuit 24, and the rectification signal S24 is output from the rectification circuit 24. Rectified signal S
24 is integrated by the LPF 26 and its rectified signal S
A DC signal S26 proportional to the duty of 24 is generated and sent to the comparison circuit 30. The comparison circuit 30 controls the delay amount of the variable delay circuit 23 so that the DC signal S26 becomes equal to the voltage value of the variable reference voltage source 34. Therefore, the maximum clock component can be extracted from the output terminal 25 by adjusting the voltage value of the variable reference voltage source 34. In addition, the rectification signal S24 may be changed depending on the temperature characteristics and the like.
Even when the duty of fluctuates, the optimum state is always controlled.

As described above, the third embodiment has substantially the same effects as the effects (a) to (c) of the first embodiment and the effect (d) of the second embodiment. , Next (f),
There is also an effect like (g). (F) Even when the duty of the rectified signal S24 changes due to temperature characteristics or the like, the input signals IN1 and IN2
For example, input data signals are input terminals 11-1, 11
If it is input to -2, it is possible to control to the optimum state in which the maximum clock component can be extracted from the input data signal. (G) Similar to the second embodiment, if the input data signal is replaced with the clock signal in (f), a clock signal corresponding to twice the frequency of the input clock signal is extracted and also used as a multiplier. It is possible. The present invention is not limited to the above-described embodiment, and for example, the comparison circuit 30 of FIG. 6 may be changed to another circuit configuration, or the above-mentioned 2 × multiplier may be an even number such as 2 stages or 4 stages. By connecting them in cascade, it is possible to construct a multiplier having a multiplication number of 4, 8, or the like.

[0021]

As described in detail above, according to the first and fourth inventions, there are the following effects (a) to (c). (A) Due to the left-right symmetry peculiar to the differential type circuit, since it is virtually grounded in the middle of the fixed delay circuit, the bias potential on the output side of the input buffer and the input side of the output buffer is designed to be equal to the ground. There is no need. Therefore, it is possible to configure a circuit with a single power source, and the circuit configuration can be simplified. Further, since it is not necessary to ground the fixed delay circuit to the ground as in the conventional case, it is possible to easily manufacture a circuit having no variations and high accuracy. (B) Since the midpoint of the fixed delay circuit is electrically determined, it is not necessary to match the physical lengths of two fixed delay circuits formed of, for example, transmission lines so that they are the same as in the conventional case. Therefore, it is possible to easily manufacture a circuit with high accuracy and no variation. (C) Since the bias points of the delay circuit outputs can be made equal, it is possible to reduce adverse effects such as deterioration of the suppression ratio due to the input offset of the rectifying circuit such as a mixer circuit provided in the subsequent stage.

According to the second, third and fourth inventions, the first
In addition to having almost the same effect as the invention of (1), the following (d),
There is also an effect like (e). (D) When the input data signal is input to the input buffer as the input signal by adjusting the delay time of the variable delay circuit even if the transmission speed is different or the accuracy of the propagation delay time of the delay circuit is insufficient. , The maximum clock component can be extracted from the input data signal. (E) In (d) above, if the input data signal is replaced with a clock signal, a clock signal corresponding to a frequency that is an even multiple of the input clock signal is extracted and can be used as a multiplier. According to the fifth invention, in addition to the effects (a) to (c) of the first invention and the effect (d) of the second invention, the following (f) and (g) are provided. There is also an effect like. (F) Even when the duty of the rectified signal changes due to temperature characteristics or the like, it is possible to control to the optimum state in which the maximum clock component can be extracted from the input data signal. (G) If the input clock signal is input to the input buffer as the first and second input signals as in the second invention,
It can also be used as a multiplier capable of extracting a clock signal corresponding to an even frequency of the input clock signal.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a differentiating circuit showing a first embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional differentiating circuit.

FIG. 3 is a signal waveform diagram of FIG.

FIG. 4 is a signal waveform diagram of FIG.

FIG. 5 is a configuration block diagram of a differentiating circuit showing a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a timing extraction circuit showing a third embodiment of the present invention.

[Explanation of symbols]

 12 Input Buffer 13 Fixed Delay Circuit 14 Output Buffer 23 Variable Delay Circuit 24 Rectifier Circuit 26 LPF 30 Comparison Circuit

Claims (5)

[Claims] 1. A differential input buffer for input impedance matching, which differentially amplifies first and second input signals to output complementary first and second signals, and the first signal. The first delay signal is generated by delaying the propagation for a predetermined time, and the second signal is delayed in the opposite direction to the first signal by the predetermined time to generate a second delay signal. 1 signal and the second delay signal are added to generate a first differential waveform, and the second signal and the first delay signal are added to generate a second differential waveform. A differential circuit, comprising: a fixed delay circuit; and an output buffer for output impedance matching, which receives the first and second differential waveforms and outputs first and second output signals. 2. A differential input buffer for input impedance matching, which differentially amplifies first and second input signals and outputs complementary first and second signals, and the first signal A second delay signal is generated by delaying the second signal by a predetermined propagation delay time in a direction opposite to the first signal while delaying the second signal by a predetermined propagation delay time. To generate the first differential waveform by adding the first signal and the second delayed signal, and add the second signal and the first delayed signal to generate the second differential signal. A variable delay circuit capable of adjusting a propagation delay time for generating a differential waveform of the input signal, and an output buffer for output impedance matching which inputs the first and second differential waveforms and outputs first and second output signals. A differentiating circuit characterized in that 3. The differential circuit according to claim 2, wherein the variable delay circuit can adjust the propagation delay time so that a duty of the rectified signal obtained by rectifying the first and second output signals is 50%. Differentiating circuit characterized by having a simple structure. 4. A timing extraction circuit comprising: the differentiating circuit according to claim 1, 2 or 3, and a rectifying circuit that rectifies the first and second output signals and outputs a rectified signal. . 5. The differentiating circuit according to claim 2, a rectifying circuit that rectifies the first and second output signals of the differentiating circuit and outputs a rectified signal, and the first and second rectifying signals are integrated. The low-pass filter that detects and outputs the voltage value corresponding to the pulse width of the output signal of 2 and the output voltage value of the low-pass filter and the voltage value of the variable reference voltage source are compared, and in the rectified signal, A timing extraction circuit comprising: a comparison circuit that controls the propagation delay time of the variable delay circuit so that the duty becomes 50%.