JPH0936772A - PLL control circuit and transmission / reception circuit - Google Patents

Abstract

(57) Abstract: To improve the characteristics of a PLL. A register 361 to which data for specifying a group and a channel is supplied, and frequency dividing circuits 351 to 355 for dividing an oscillation signal S30 having a predetermined frequency into a plurality of frequencies different from each other. Data b specifying a group of the data supplied to the register 361
A selector circuit 35 for selectively extracting the divided signal Sx of a predetermined frequency among a plurality of frequencies in accordance with 1 and b0.
6 and a conversion circuit 362 for converting the data b6 to b2 designating the channel out of the data supplied to the register 361 into the data of the frequency division ratio N of the variable frequency division circuit 311 of the PLL 31. The divided signal Sx is supplied to the phase comparison circuit 313 of the PLL 31 as a signal of the reference frequency, and the data of the conversion result of the conversion circuit 362 is set in the variable frequency division circuit 311 as the data of the division ratio.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL control circuit and a transmission / reception circuit using the same.

[0002]

2. Description of the Related Art For example, a cordless telephone in the United States is assigned a frequency band for 25 channels, and its channel number CHNO and the transmission frequencies (carrier frequencies) fBU and fHS of the master unit and the slave unit. The relationship is as shown in FIG.

That is, the transmission frequency fBU of all channels of the base unit and the transmission frequency fHS of channels other than the second and fifth channels of the base unit are integer multiples of 10 kHz. However, as indicated by the asterisk, the transmission frequency f of the second and fifth channels of the slave unit
HS is an integer multiple of 15 kHz.

[0004]

A transmission signal of such a frequency is generally formed by a PLL, but in the case of directly forming a carrier signal of a frequency equal to the above transmission frequencies fBS and fHS in the PLL, , The reference frequency required for the PLL is 5 kHz, which is the highest common divisor of 10 kHz and 15 kHz.

However, when the reference frequency of the PLL becomes low, the lockup characteristic of the PLL and the C / N of the oscillation signal output from the VCO become poor.

A frequency band for 15 channels is assigned to a cordless telephone in France, but the transmission frequency fBU of the master unit and the transmission frequency f of the slave unit are assigned.
HS is as shown in FIG. Therefore, P
The reference frequency required for LL is 12.5 kHz.

Further, although a frequency band for 12 channels is assigned to the cordless telephone in Spain, the transmission frequency fBU of the master unit and the transmission frequency fHS of the slave unit are as shown in FIG. Therefore,
The reference frequency required for the PLL is 25 kHz.

Therefore, when the main part of the cordless telephone is made into a one-chip IC so that the IC can be commonly used for cordless telephones for the United States, France, and Spain, the reference frequency of the PLL is the maximum of the above-mentioned reference frequencies. The frequency is 2.5 kHz, which is the common divisor, and the characteristics become even worse.

Further, when the transmission frequencies fBU and fHS are set, the microcomputer forms data of a frequency division ratio corresponding to the channel number, converts the frequency division ratio into a binary value, and outputs the binary value. Each bit of the value is set in each stage of the variable frequency dividing circuit of the PLL by serial communication or parallel communication.

Therefore, as an example, considering the transmission frequency of the first channel of the base unit in the United States of 46.610 MHz, even if the reference frequency is 5 kHz, the division ratio N becomes N = 46.610 MHz / 5 kHz = 9332, The binary value is 14 bits long.

That is, when setting a channel, 14-bit length data is set in the variable frequency divider circuit of the PLL of the transmitting circuit, and 14-bit length is set in the variable frequency divider circuit of the PLL of the local oscillator circuit of the receiving circuit. The data of must be set. Moreover, in the case of an IC for multiple countries, it is necessary to set data for the reference frequency. For this reason, the load on the microcomputer for system control has increased.

The present invention is intended to solve the above problems.

[0013]

Therefore, in the present invention, the VCO and the oscillation signal of the VCO are 1 / N (N
Is a integer of 2 or more), a variable frequency dividing circuit for frequency-dividing into a signal of frequency, a phase comparison circuit for phase-comparing the frequency-divided signal from the variable frequency dividing circuit with a signal of the reference frequency, A low-pass filter for extracting a direct current component from the comparison output, the direct current component from the low pass filter is supplied to the VCO as its control voltage to form a PLL, and a register to which data designating a group and a channel is supplied A frequency dividing circuit for dividing an oscillation signal having a predetermined frequency into a plurality of frequencies different from each other, and data specifying the group of the data supplied to the register. A frequency-divided signal of a predetermined frequency is selectively taken out, and the frequency-divided signal thus taken out is supplied to the phase comparison circuit as a signal of the reference frequency. A conversion circuit for converting the data designating the channel out of the data supplied to the register into the data of the division ratio N, and the conversion result data of the conversion circuit is This is a PLL control circuit which is set in the variable frequency dividing circuit as the data of the frequency dividing ratio N.

Therefore, when the data designating the group and the channel is loaded into the register, the output frequency of the PLL automatically becomes the target frequency.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION [One Mode of Cordless Telephone] First, one mode of a receiving circuit and a transmitting circuit of a cordless telephone to which the present invention is applied will be described with reference to FIGS. 1 and 2.

In the case where the receiving circuit and the transmitting circuit shown in FIGS. 1 and 2 are constructed so that they can be integrated into a one-chip IC, and the IC can be used in both the master unit and the slave unit. And shows the case where the IC is used in a slave unit.

Further, * 1 and * 2 in FIG. 1 are connected to * 1 and * 2 in FIG. 2, and the portion 1 surrounded by a chain line is integrated into one chip IC.

This IC 1 has a receiving circuit 10 and a transmitting circuit 40. The receiving circuit 10 is of the double superheterodyne type and is of direct conversion type. That is, the FM signal Sr of the downlink channel from the base unit is received by the antenna 2, and is orthogonal through the signal line of the terminal T11 → high frequency amplifier 11 → terminal T12 → bandpass filter 3 having all the downlink channels as pass bands → terminal T13. It is supplied to the first mixer circuits 12 and 22 for the I axis and the Q axis for conversion.

An oscillator circuit 30 is also provided. This oscillator circuit 30 has a stable reference frequency, for example, 14.4M.
It is for forming the oscillation signal S30 of Hz. Therefore, the oscillation circuit 30 has the crystal oscillator 6 through the terminal T16.
Are connected to form a crystal oscillation circuit.

Further, a frequency dividing circuit 35 and a setting circuit 36 are provided. Although the details of these circuits 35 and 36 will be described later, when the oscillation signal S30 is supplied to the frequency dividing circuit 35, for example, a frequency of 1/1440, 1/1152, 1/960 or 1/576, that is, a frequency of 10 kHz or 12.5. It is divided into a signal Sx of a predetermined frequency of kHz, 15 kHz or 25 kHz,
This signal Sx is supplied to the PLL 31 as a signal of its reference frequency.

Further, when the data of the channel number CHNO is supplied from the system controlling microcomputer (not shown) to the setting circuit 36 through the terminal T17, the data of the division ratio corresponding to the channel number CHNO is obtained from the data. The data of the frequency division ratio that is formed is supplied to the variable frequency division circuit 311 of the PLL 31 and set.

In this way, the oscillation signal S31 having a frequency equal to the carrier frequency of the FM signal Sr is taken out from the VCO 312 of the PLL 31. In this case, the received F
The carrier frequency of the M signal Sr is the transmission frequency fBU of the master unit.
Therefore, the frequency of the oscillation signal S31 also becomes the value fBU.

The signal S31 is supplied to the mixer circuit 12 as the first local oscillation signal and is also supplied to the phase shift circuit 32 to be phase-shifted by π / 2.
32 is supplied to the mixer circuit 22 as the first local oscillation signal.

Therefore, for simplification, as shown in FIG. 3A, the received signal Sr has a signal component Sa in its lower sideband and a signal component Sb in its upper sideband. , Ωo: carrier frequency (angular frequency) of the received signal Sr ωo = 2πfBU ωa: angular frequency of the signal component Sa. ωa <ωo Ea: Amplitude of signal component Sa ωb: Angular frequency of signal component Sb ωb> ωo Eb: If the amplitude of the signal component Sb is Δωa = ωo−ωa Δωb = ωb−ωo, then Sr = Sa + Sb Sa = Ea · sinωat Sb = Eb · sinωbt.

Further, if E1 is the amplitude of the first local oscillation signals S31 and S32, then S31 = E1.sin.omega.ot S32 = E1.cos.omega.ot.

Therefore, S12, S22: S12 = Sr.S31 = (Ea.sin.omega.at + Eb.sin.omega.bt) .times.E1.sin.omega.ot = αa {-cos (ωa + ωo) t + cos (ωo- ωa) t} +
αb {−cos (ωb + ωo) t + cos (ωb−ωo) t} = αa {−cos (ωa + ωo) t + cosΔωat} + αb {−c
os (ωb + ωo) t + cosΔωbt} S22 = Sr · S32 = (Ea · sinωat + Eb · sinωbt) × E1 · cosωot = αa {sin (ωa + ωo) t−sin (ωo−ωa) t} + αb
{Sin (ωb + ωo) t + sin (ωb−ωo) t} = αa {sin (ωa + ωo) t−sin Δωat} + αb {sin
(Ωb + ωo) t + sinΔωbt} αa = Ea · E1 / 2/2 αb = Eb · E1 / 2

Then, in the above equation, the angular frequencies Δωa, Δ
Since the signal component of ωb is the required intermediate frequency signal, these signals S12 and S22 are supplied to the low pass filters 13 and 23, and the signal components of the angular frequencies Δωa and Δωb are extracted as the first intermediate frequency signals S13 and S23, and S13 = Αa · cos Δωat + αb · cos Δωbt S23 = −αa · sin Δωat + αb · sin Δωbt In this case, as is clear from the above equation and FIG. 3A, the signals S13 and S23 are baseband signals.

Further, these signals S13 and S23 are supplied to the second mixer circuits 14 and 24 for the I axis and the Q axis of the orthogonal transformation.

Further, the oscillation signal S30 of the oscillation circuit 30 is supplied to the frequency dividing circuit 33 and is a signal S33 having a frequency of several times the highest audible frequency, for example, 262 frequency-divided to have a frequency of about 55 kHz.
It is divided into the signal S33 of z. Then, the signal S33 is supplied to the mixer circuit 14 as the second local oscillation signal and is also supplied to the phase shift circuit 34 to be phase shifted by π / 2.
The phase shift signal S34 is supplied to the mixer circuit 24 as the second local oscillation signal.

Therefore, S33 = E2sinωst S34 = E2cosωst E2: The amplitude of the second local oscillation signals S33 and S34 is set to ωs = 2πfs (fs = about 55 kHz), and S14 and S24: of the mixer circuits 14 and 24. As an output signal, S14 = S13 · S33 = (αa · cosΔωat + αb · cosΔωbt) × E2 · sinωst = βa {sin (Δωa + ωs) t−sin (Δωa−ωs) t} + βb {sin (Δωb + ωs) t-sin ( Δωb−ωs) t} S24 = S23 · S34 = (− αa · sin Δωat + αb · sin Δωbt) × E2 · cosωst = −βa {sin (Δωa + ωs) t + sin (Δωa−ωs) t} + βb {sin (Δωb + ωs) t + sin (Δωb) ωs) t} βa = αa · E2 / 2 βb = αb · E2 / 2.

Then, in these signals S14 and S24, signals S14 and S24 are set so that the frequency difference does not become a negative value.
When transforming 24, S14 = βa {sin (Δωa + ωs) t + sin (ωs−Δωa) t} + βb {sin (Δωb + ωs) t + sin (ωs−Δωb) t} = βa · sin (ωs + Δωa) t + βa · sin (ωs−Δωa) t + βb · sin (ωs + Δωb) t + βb · sin (ωs−Δωb) t S24 = −βa {sin (Δωa + ωs) t−sin (ωs−Δωa) t} + βb {sin (Δωb + ωs) t−sin (ωs−Δωb) t } = − Βa · sin (ωs + Δωa) t + βa · sin (ωs−Δωa) t + βb · sin (ωs + Δωb) t−βb · sin (ωs−Δωb) t.

Then, these signals S14 and S24 are supplied to the addition circuit 15 and added, and from the addition circuit 15, the addition represented by S15 = S14 + S24 = 2βa · sin (ωs−Δωa) t + 2βb · sin (ωs + Δωb) t The signal S15 is taken out.

The addition signal S15 is illustrated as follows.
As shown in FIG. 3B, this signal S15 is nothing but a signal obtained by frequency-converting the original received signal Sr into a signal having a carrier frequency (angular frequency) ωs. That is, the signal S15 is the second intermediate frequency signal having the intermediate frequency fs.

Then, the second intermediate frequency signal S15 is supplied to the FM demodulation circuit 18 through the band pass filter 16 for the intermediate frequency filter and the limiter amplifier 17, and the original audio signal is demodulated, and this audio signal is Amplifier 1
It is supplied to the speaker 4 for the receiver through 9 and the terminal T14. The above is the configuration and operation of the receiving circuit 10.

On the other hand, the transmitting circuit 40 directly converts the voice signal into the FM signal of the upstream channel, and the PLL circuit
43 is provided and the frequency from the frequency dividing circuit 35 is 10
A signal Sy having a predetermined frequency of kHz, 12.5 kHz, 15 kHz or 25 kHz is taken out, and this signal Sy is supplied to PLL3.
1 is supplied as a signal of the reference frequency. Further, the data of the frequency division ratio corresponding to the channel number CHNO is taken out from the setting circuit 36, and this data is supplied to the variable frequency dividing circuit 431 of the PLL 43 to be set.

In this way, from the VCO 432 of the PLL 43, the signal St of the carrier frequency fHS of the upstream channel paired with the downstream channel received by the receiving circuit 10 is taken out.

The voice signal from the microphone 5 for the transmitter is supplied to the low-pass filter 42 through the terminal T15 and the amplifier 41 to remove the unnecessary band component, and then the VCO 432 of the PLL 43 receives the oscillation frequency as a control signal. Supplied.

Thus, the VCO 432 extracts the FM signal St which is the upstream channel paired with the downstream channel received by the receiving circuit 10 and which is FM-modulated by the audio signal from the low pass filter 42.

The FM signal St is taken out to the terminal T18 through the drive amplifier 44 and the output amplifier 45, supplied to the antenna 2 and transmitted. The above is the configuration and operation of the transmission circuit 40.

In the case of a general FM receiver, the intermediate frequency thereof is set to 10.7 MHz, so that the intermediate frequency filter is composed of a ceramic filter and cannot be integrated into an IC.

However, in the receiving circuit 10 described above,
Since the first intermediate frequency signals S12 and S22 are in the base band and the second intermediate frequency fs is as low as 55 kHz, the filters 13, 23 and 16 can be configured by active filters having resistors, capacitors and amplifiers. . Therefore, the receiving circuit 10 includes the filter 3 and the V
It can be integrated into an IC except for the oscillation coil (not shown) of CO312. The same applies to the transmission circuit 40, which can be integrated into an IC.

Therefore, the entire receiving circuit 10 and transmitting circuit 40 shown in FIGS. 1 and 2 can be integrated into a single monolithic IC.

In the above description, the case where the IC1 is used for the slave unit is used, but the terminals T14 and T15 are 4 lines / 2 of the master unit.
The frequency dividing circuits 311 and 43 are connected to the line conversion circuit.
If the frequency division ratio of 1 is replaced, the above operation is performed in the parent device. Then, at this time, the receiving circuit 10 receives the upstream channel, and the transmitting circuit 20 transmits the downstream channel.

Therefore, this IC1 can also be used in the master unit. That is, this IC1 can be commonly used by the child device and the parent device.

[One Mode of Dividing Circuit 35 and Setting Circuit 36] In the circuits shown in FIGS. 1 and 2, the first local oscillation signal S31 of the receiving circuit 10 is used when the IC1 is used as a slave unit. , S32 (the angular frequency) is equal to the reception frequency ωo of the reception signal Sr. The reception frequency ωo is also the transmission frequency of the base unit.

Therefore, when IC1 is used as a slave unit, the oscillation frequency of VCO 312 of PLL31 = transmission frequency fBU of the master unit becomes the oscillation frequency of VCO432 of PLL43 = transmission frequency fHS of the slave unit, and when IC1 is used as the master unit The oscillation frequency of the VCO 312 of the PLL 31 = transmission frequency fHS of the slave unit The oscillation frequency of the VCO 432 of the PLL 43 = transmission frequency fBS of the master unit.

Therefore, when the IC 1 is used in the slave unit 1, it is assumed that the frequency dividing ratio of the variable frequency dividing circuit 311 of the PLL 31 = Nx and the frequency dividing ratio of the variable frequency dividing circuit 431 of the PLL 43 = Ny for a certain channel. For example, when the IC1 is used in the master unit, the frequency division ratio of the variable frequency divider circuit 311 of the PLL 31 is Ny in the same channel, and the frequency division ratio of the variable frequency divider circuit 431 of the PLL 43 is Nx.

That is, the frequency division ratios Nx and Ny are set for each channel.
In advance, the IC 1 may be set in the variable frequency dividing circuits 311 and 431 in opposite directions depending on whether the IC 1 is used as a slave or a master.

The setting circuit 36 shown in FIG. 4 sets the frequency division ratios of the variable frequency dividing circuits 311 and 431 on the basis of such an idea.

That is, first, the PLLs 31 and 43, but in the PLL 31, the oscillation signal S of the VCO 312 is generated.
31 is supplied to the variable frequency dividing circuit 311 and is frequency-divided to a frequency of 1 / N31. This frequency-divided signal is supplied to the phase comparison circuit 313, and the signal Sx of the reference frequency is taken out from the frequency dividing circuit 35. , The signal Sx is supplied to the comparison circuit 313. Then, the comparison output of the comparison circuit 313 is supplied to the low-pass filter 314 to extract the DC component, and this DC component is supplied to the VCO 312 as its control voltage. Therefore, the oscillation frequency of the VCO 312 is
The frequency is N31 times the frequency of the reference signal Sx.

Similarly, in the PLL 43, V
The oscillation signal St of the CO 432 is supplied to the variable frequency dividing circuit 431 and divided into a frequency of 1 / N43. This frequency dividing signal is supplied to the phase comparison circuit 433 and the frequency dividing circuit 3
The signal Sy of the reference frequency is taken out from 5, and this signal Sy
Are supplied to the comparison circuit 433. Then, the comparison output of the comparison circuit 433 is supplied to the low-pass filter 434 to extract the DC component, and this DC component is supplied to the VCO 432 as its control voltage. Therefore, VCO4
The oscillation frequency of 32 is N43 times the frequency of the reference signal Sy.

The setting circuit 36 is provided with an 8-bit serial input / parallel output shift register 361. When setting a channel, the channel data CHDT is supplied to the register 361 through a terminal T17. Is supplied. This channel data CHDT
5 is 8-bit serial data, for example, the first bit b7 (MSB) is always "1", and the subsequent 5 bits b6 to b2 indicate the channel number CHNO of the channel to be 2 It is indicated by a decimal value.
And the last 2 bits b1 and b0 are the country code,
For example, as shown in FIG. 6, the countries of the United States, France and Spain are assigned.

Then, the channel data CHDT supplied to the register 361 is supplied to the conversion circuit 362,
The channel number CHNO indicated by the bits b6 to b2 is the bit b
The data is converted into the data of the frequency division ratio NBU corresponding to the transmission frequency fBU of the parent device in the country indicated by 1 and b0, and the data of the frequency division ratio NBU is supplied to the switch circuit 364.

Further, the channel data CHDT supplied to the register 361 is supplied to the conversion circuit 363, and the channel number CHNO indicated by the bits b6 to b2 is changed to the bits b1 and b0.
Is converted into data of the frequency division ratio NHS corresponding to the transmission frequency fHS of the slave unit in the country indicated by, and the data of the frequency division ratio NHS is supplied to the switch circuit 364.

Further, for example, when the IC1 is used in the slave unit, the terminal T19 is pulled down to the "0" level, and when used in the master unit, the terminal T19 is pulled up. As a result, the level becomes "1". Then, the voltage of the terminal T19 is supplied to the switch circuit 364 as its control voltage.

Thus, when the terminal T19 is at the "0" level (when the IC1 is used in the slave unit), the data of the frequency division ratio NBU supplied from the conversion circuit 362 to the switch circuit 364 is the variable frequency division circuit. 311 is supplied to and set by the conversion circuit 362 and the switch circuit 3
The data of the frequency division ratio NHS supplied to 64 is supplied to the variable frequency dividing circuit 431 and set.

Further, when the terminal T19 is at "1" level (when IC1 is used in the master unit), the division ratio NBU supplied from the conversion circuit 362 to the switch circuit 364.
Data is supplied to and set by the variable frequency dividing circuit 431, and the conversion circuit 362 switches the switch circuit 364.
The data of the division ratio NHS supplied to the variable division circuit 31
1 is set and set.

Therefore, the variable frequency dividing circuits 311 and 431 are provided.
Is set to the division ratio corresponding to the channel number in the country indicated by the channel data CHDT. Further, the frequency division ratios of the variable frequency dividing circuits 311 and 431 are set to be opposite to each other depending on whether the IC1 is used for the child device or the parent device.

Further, in the frequency dividing circuit 35, the oscillation signal S30 from the oscillation circuit 30 is supplied to the frequency dividing circuit 351 and is frequency-divided by 1/24 to be a frequency-divided signal having a frequency of 600 kHz. It is supplied to the circuit 352. Further, the bit b1 of the country code is extracted from the register 361, and this bit b1 is supplied to the frequency dividing circuit 352 as a switching signal of the frequency dividing ratio, and the frequency dividing ratio of the frequency dividing circuit 352 is b.
When 1 = “0”, the frequency division is 1/5, and when b1 = “1”, the frequency division is 1/4.

Therefore, from the frequency dividing circuit 352, b1
When "0" (country codes b1 and b0 indicate the United States), a frequency-divided signal with a frequency of 120 kHz is extracted, and when b1 = "1" (country code b1,
When b0 indicates France or Spain), the divided signal having a frequency of 150 kHz is extracted.

Then, this frequency-divided signal is applied to the frequency-dividing circuit 353.
And is divided into ⅛ to be a frequency-divided signal having a frequency of 18.75 kHz or 15 kHz, and this signal is supplied to the selector circuit 356. The frequency-divided signal from the frequency-dividing circuit 352 is supplied to the frequency-dividing circuit 354 and is frequency-divided by 1/6 to be a frequency-divided signal having a frequency of 25 kHz or 20 kHz. This signal is supplied to the selector circuit 356. It is also supplied to the frequency dividing circuit 355, frequency-divided by 1/2 and the frequency is 12.5.
The frequency divided signal of kHz or 10 kHz is supplied to the selector circuit 356.

Also, from the register 361, the country code b
1 and b0 are taken out, and these codes b1 and b0 are supplied to the selector circuit 356 as its control signal. From the selector circuit 356, the frequency is divided into 10 kHz, 12.5 kHz or 25 kHz according to the country codes b1 and b0. Signal Sx,
Sy, that is, the frequency-divided signals Sx and Sy of the frequency (reference frequency) shown in FIG. 6 are extracted.

However, at this time, the data b6 to b2 of the channel number CHNO are read from the register 361 to the decoder circuit 35.
A signal which is supplied to 8 and becomes "1" when CHNO = 2 or 5 and becomes "0" at other times is extracted. Then, this signal is supplied to the selector circuit 356 as a control signal thereof, and when b1 = "0" and b0 = "0" (when the country code is the United States), the selector circuit 356.
A frequency-divided signal Sy having a frequency of 15 kHz is taken out from the signal (the signal Sx is 10 kHz).

The signals Sx and Sy from the selector circuit 356 are supplied to the switch circuit 357, and the voltage of the terminal T19 is supplied to the switch circuit 357 as its control voltage.

Thus, when the terminal T19 is at "0" level (when the IC1 is used in the slave unit), the divided signal Sx supplied to the switch circuit 357 is supplied to the comparison circuit 313 as a signal of the reference frequency. As well as
The divided signal Sy supplied to the switch circuit 357 is supplied to the comparison circuit 433 as a signal of the reference frequency.

Further, when the terminal T19 is at "1" level (when IC1 is used in the master unit), the frequency division signal Sx supplied to the switch circuit 357 is compared with the comparison circuit 43.
The frequency-divided signal Sy supplied to the switch circuit 357 is supplied to the comparison circuit 313 as a signal of the reference frequency.

Therefore, the comparison circuit 313 informs the signal S of the reference frequency corresponding to the country indicated by the country codes b1 and b0.
x and Sy are supplied. And in the case of America, the second
For channel and channel 5, the reference frequency for the transmit frequency of the handset is changed from 10 kHz to 15 kHz.

Thus, according to the frequency dividing circuit 35 and the setting circuit 36 described above, the required reference frequencies of the PLLs 31 and 43 can be obtained only by specifying the country and the channel number CHNO. Moreover, even if the reference frequency required for each channel is different as in the United States or the reference frequency required for each country is different, the greatest common divisor of the reference frequency required in all countries is Since it is not necessary to set the frequency, PLL3
Lockup characteristics of 1, 43, VCO 312, 432
The C / N and the like of the oscillation signals S31 and St output from the device do not deteriorate.

Furthermore, the country and channel number CHNO are set to 1
The frequency division ratios N31, N43 and the reference frequency of the variable frequency dividing circuits 311 and 431 can be set only by designating the number of times.
Each time the channel is changed, the channel number CHNO is converted into the actual frequency division ratios N31 and N43, the conversion value thereof is converted into a binary value, or each binary value is changed by the variable frequency dividing circuit 31.
It is not necessary to set them to 1 and 431, respectively. Also, PL
It is not necessary to set the reference frequencies of L31 and L43. Therefore, the load on the microcomputer for controlling the system can be reduced.

Moreover, the frequency division ratios of the PLLs 31 and 43 can be exchanged by simply pulling up or pulling down the terminal T19, and the IC1 can be used for both the slave unit and the master unit.

In the above description, the present invention is applied to a cordless telephone and its PLL.
The present invention can be applied to other telephone systems and transmission / reception systems.

[0072]

According to the present invention, the required PLL reference frequency can be obtained only by specifying the group and channel number. Moreover, even if the reference frequency required for each channel is different, or the reference frequency required for each group is different, the frequency must be the greatest common divisor of the reference frequency required for all groups. Therefore, the lockup characteristic of the PLL and the C / N of the oscillation signal of the VCO are not deteriorated.

Further, the frequency division ratio and the reference frequency of the variable frequency dividing circuit can be set only by designating the group and the channel number once, and the burden on the microcomputer for system control can be reduced.

[Brief description of drawings]

FIG. 1 is a system diagram showing a part of one embodiment of the present invention.

FIG. 2 is a system diagram showing one form of a continuation of FIG.

FIG. 3 is a frequency spectrum diagram for explaining the present invention.

FIG. 4 is a system diagram showing a part of one embodiment of the present invention.

FIG. 5 is a format diagram for explaining the present invention.

FIG. 6 is a diagram for explaining the present invention.

FIG. 7 is a table for explaining the present invention.

FIG. 8 is a table for explaining the present invention.

FIG. 9 is a table for explaining the present invention.

[Explanation of symbols]

 1 1-chip IC 4 Speaker (for handset) 5 Microphone (for transmitter) 6 Crystal oscillator 10 Receiving circuit 12, 22 First mixer circuit 14, 24 Second mixer circuit 18 Demodulating circuit 30 Oscillating circuit 31, 43 PLL 32, 34 phase shift circuit 33, 35 frequency divider circuit 36 setting circuit 40 transmission circuit 311, 431 variable frequency divider circuit 312, 432 VCO 313, 433 phase comparator circuit 351 to 355 frequency divider circuit 356 selector circuit 357, 364 switch circuit 358 decoder circuit 361 shift register 362, 363 conversion circuit

Claims (3)

[Claims] 1. A VCO, a variable frequency dividing circuit for dividing an oscillation signal of the VCO into a signal having a frequency of 1 / N (N is an integer of 2 or more), and a frequency dividing signal from the variable frequency dividing circuit. It has a phase comparison circuit for performing phase comparison with a signal of a reference frequency, and a low-pass filter for extracting a DC component from the comparison output of this phase comparison circuit, and the DC component from the low-pass filter is supplied to the VCO as its control voltage. The PLL is configured as described above, a register to which data for specifying a group and a channel is supplied, a divider circuit for dividing an oscillation signal of a predetermined frequency into a plurality of frequencies different from each other, and data supplied to the register. Of the plurality of frequencies, the frequency-divided signal of a predetermined frequency is selectively taken out, and the taken-out frequency-divided signal is taken out. A selector circuit for supplying the phase comparison circuit as a signal of the reference frequency, and a conversion circuit for converting the data specifying the channel out of the data supplied to the register into the data of the division ratio N. P which is configured to set the conversion result data of the conversion circuit as data of the division ratio N in the variable frequency division circuit.
LL control circuit. 2. The PLL control circuit according to claim 1, further comprising a decoder circuit for decoding data designating the channel among the data supplied to the register, wherein the selector circuit is provided in the register. According to the data designating the group of the supplied data and the output signal of the decoder circuit, a divided signal of a predetermined frequency among the plurality of frequencies is selectively extracted, and the extracted divided frequency signal is extracted. A signal is supplied to the phase comparison circuit as a signal of the reference frequency P
LL control circuit. 3. A local oscillator circuit of a receiving circuit is constituted by a VCO of a first PLL, and a circuit forming a carrier signal of a transmitting circuit is a second PLL.
Of the VCO, which is supplied with data for specifying a group and a channel, a divider circuit for dividing an oscillation signal of a predetermined frequency into a plurality of frequencies different from each other, and a register for the data supplied to the register. A divided signal of a predetermined frequency among the plurality of frequencies is selectively taken out according to the data designating the above group, and the taken divided signal is phase-compared between the first and second PLLs. The selector circuit which supplies the circuit as a signal of the reference frequency and the data which specifies the channel among the data supplied to the register are set to the frequency division ratios of the variable frequency dividing circuits of the first and second PLLs. A conversion circuit for converting into data, and sets the conversion result data of the conversion circuit in the variable frequency division circuit as the data of the frequency division ratio. Transmitting and receiving circuit which is adapted.