JPH0936875A - Asynchronous transmission device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale, to improve the transmission efficiency and to decrease the processing time by utilizing a multi-frame phase of an input STM signal so as to contain information by a frame period of the received STM signal into one cell. SOLUTION: Received STM signals by a cell conversion circuit 11 are signals of plural series having the same multi-frame structure whose multi-phases are coincident with each other, a cell conversion circuit 11, a cell overhead provision circuit 12, a cell synchronization circuit 14 and a cell inverse conversion circuit 15 are provided to each channel, and a multi-frame phase detection circuit 16 is provided to the system as a means detecting a multi-frame phase of plural series signals. Each cell conversion circuit 11 contains information of one or plural multiframes, based on a detected multi-frame phase as a unit. Thus, when multi-frame phase for all channels can be established simultaneously when cell synchronization is established.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal transmission in Asynchronous Transfer Mode (hereinafter referred to as "ATM"). In particular, the synchronous transfer mode (Sync
A circuit for converting a signal of a hronous transfer mode (hereinafter referred to as "STM") into an ATM signal, and a circuit for performing the reverse conversion, that is, a cell assembling / decellizing circuit (CLA).
D).

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional asynchronous transmission apparatus equipped with a cell assembling / decellizing circuit. Here, an example will be described in which a plurality of input terminals are provided, the STM signal input from each terminal has a one-channel multi-frame structure, and the multi-frame phases of the respective terminals match. The asynchronous transmission device includes a cell conversion circuit 21 and a cell overhead adding circuit 22 as a cell conversion circuit, and a cell synchronization circuit 2 via an ATM network 23.
4 and the cell reverse conversion circuit 25. The output of the cell inverse conversion circuit 25 is output via the multi-frame phase synchronization circuit 26. Cell conversion circuit 2
1, cell overhead adding circuit 22, cell synchronizing circuit 2
4, the cell inverse conversion circuit 25 and the multi-frame phase synchronization circuit 26 are provided for each channel, and a common timing generation circuit 27 is connected to the multi-frame phase synchronization circuit 26 for each channel.

The cell conversion circuit 21 decomposes a main information portion called a payload, which is obtained by removing frame synchronization information and other control information, from an input STM signal (hereinafter referred to as "input STM signal") into 48 bytes. The cell overhead adding circuit 22 adds a 5-byte header to each 48 bytes (this is called "cell overhead"), and 53
Let it be a byte cell. This signal block consisting of 53 bytes is called a "cell" and transmitted to the ATM network 23. FIG. 7 shows an example of cell conversion by the cell conversion circuit 21 and the cell overhead adding circuit 22. Input terminal #
1 to #n of the multi-frame (M
The F1-MF4) phases are not considered at all. In the figure, a specific multiframe phase point is represented by a black triangle so that the multiframe phase becomes clear.

The cell synchronization circuit 24 establishes cell synchronization, recognizes a 53-byte cell, decodes the overhead of each cell, and verifies whether or not the destination described therein is its own. If it is addressed to you, the cell reverse conversion circuit 2
5, the cell overhead of 5 bytes is deleted and frame information is added, and the same STM signal as the input signal is output. Cell synchronization circuit 24 and cell inverse conversion circuit 2
FIG. 8 shows an example of decellization by No. 5. At this point, the multiframe phase of the cell is not considered at all.

The output of the cell inverse conversion circuit 25 is input to the multi-frame synchronization circuit 26, and the STM signal is output according to the timing signal from the common timing generation circuit 27. That is, the multiframe synchronization circuit 26 detects the multiframe phases of all the channels, and multiframe phase synchronization is established. FIG. 9 shows an example of the operation of establishing multi-frame phase synchronization.

By converting the STM signal into the ATM signal and transmitting the ATM signal in this way, the A signal is unified regardless of the transmission parameters of the input signal such as the transmission speed and the frame synchronization method.
Transmission within the TM network becomes possible.

[0007]

Generally, cell fluctuations and cell loss occur in an ATM network.
Measures against these phenomena are required on the receiving side of the ATM network. When the input STM signal is composed of multiple channels with the same multi-frame phase, in addition to the buffer normally required on the receiving side of the network for cell fluctuations, the multi-frame phases of the multiple channels are matched. A multi-frame phase locked loop circuit is required for this purpose. In addition, in order to prevent cell loss, the cell conversion circuit and the cell inverse conversion circuit are provided with a cell conversion circuit and a cell inverse conversion circuit so as not to cause out-of-phase of multiframe phase in the STM signal after the cell inverse conversion (hereinafter referred to as “output STM signal”). A new function (for example, ATM adaptation layer, type 1: AAL type 1) for managing the sequence is required.

As described above, since the multiframe phase synchronization circuit is required for the cell fluctuation, the circuit scale and the processing time are increased. In addition, since the cell conversion circuit and the cell inverse conversion circuit are required to have a function of managing the sequence of cells against cell loss, this may increase the circuit scale, decrease the transmission efficiency, and increase the processing time. Was there.

The present invention solves the above problems, and when the input signal is composed of a plurality of channels having the same multi-frame phase, the asynchronous transfer is improved in circuit scale, transmission efficiency and processing time. The purpose is to provide a device.

[0010]

SUMMARY OF THE INVENTION The present invention is most important in that a cell is formed by utilizing a multi-frame phase of an input signal and a signal for one or a plurality of multi-frame periods is accommodated in one cell. Characterize. That is, the asynchronous transmission apparatus of the present invention comprises cell conversion means for converting a signal of the synchronous transfer mode into a cellized signal of the asynchronous transfer mode and outputting the cellized signal to the asynchronous transfer mode network, and a cell input from the asynchronous transfer mode network. In an asynchronous transmission device provided with a decellizing means for converting the converted signal into a signal of a synchronous transfer mode,
The input signals in the synchronous transfer mode are signals of a plurality of series having the same multiframe structure and having the same multiframe phase, and the cell forming means detects the multiframe phase of the signals of the plurality of series, and Means for accommodating one cell or a plurality of pieces of multi-frame information as a unit in one cell on the basis of the multi-frame phase, and the de-cellization means for detecting the cell phase of the cell-ized signal and the detection And a means for inversely converting into a signal of a synchronous transfer mode having a required multi-frame phase timing based on the selected cell phase.

A plurality of series of signals in the synchronous transfer mode are respectively inputted from different input terminals, and the accommodating means includes means for individually converting the signals inputted from the different input terminals into cells, and the means for inverse conversion is Means may be included for generating a plurality of series of signals with multi-frame phase matching from the separately cellized signals. Further, the signals of a plurality of sequences are signals in which a plurality of channels having the same multi-frame structure are time-division multiplexed, and the means for accommodating may include a means for converting the time-division multiplexed signals into cells without demultiplexing. it can. Furthermore, by combining these, a plurality of series of signals are input from a plurality of input terminals, and a plurality of channels each having the same multi-frame structure are time-division multiplexed signals, and the accommodating means is input from a plurality of input terminals. It is also possible to include means for individually cellifying the respective signals, and the means for inverse transforming can also include means for generating a plurality of series signals having the same multiframe phase from the separately cellized signals.

In the present invention, the multi-frame phase of the input STM signal is used to make m frames of n channels of the input STM signal in one cell (n and m are both integers of 1 or more).
Contain information on. Therefore, the multiframe phase of the channel can be obtained at the same time when the cell synchronization is established, and the multiframe phase synchronization of all channels can be established without using the multiframe phase synchronization circuit. Further, when cell loss occurs, information for m multiframes may be lost, so even if there is no function for managing the cell sequence, multiframe out-of-sync is not generated in the output STM signal. Therefore, it is possible to solve the problems of increased circuit scale, reduced transmission efficiency, and increased processing time.

[0013]

1 is a block diagram showing an asynchronous transmission apparatus according to an embodiment of the present invention. This device is STM
The signal is converted into a cellized ATM signal and the ATM network 13
The cell converting circuit 11 and the cell overhead adding circuit 12 are provided as the cell converting means for outputting to the cell, and the cell synchronizing circuit 14, the cell inverse converting circuit 15, A timing generator 17 is provided. The input STM signals input to the cell conversion circuit 11 are a plurality of series signals having the same multi-frame structure and having the same multi-frame phase. Corresponding to each of them, the cell conversion circuit 11, the cell overhead adding circuit 12, the cell synchronization circuit. A plurality of circuits 14 and cell inverse conversion circuits 15 are provided, and a multi-frame phase detection circuit 16 is provided as means for detecting multi-frame phases of signals of a plurality of series. The cell conversion circuit 11 stores information of one or a plurality of multiframes as a unit in one cell based on the detected multiframe phase,
The cell synchronization circuit 14 detects the cell phase of the ATM signal, and the cell inverse conversion circuit 15 inversely converts the cell phase of the ATM signal into a synchronous transfer mode signal having a required multi-frame phase timing.

FIG. 2 shows a cell conversion circuit 11, a cell overhead adding circuit 12 and a multi-frame phase detection circuit 16.
FIG. 6 is a diagram for explaining a cell formation operation by the above. The multiframe phase detection circuit 16 detects the multiframe phases of all STM signals input to the input terminals # 1 to #n. The cell conversion circuit 11 uses the multi-frame phase to convert the input STM signal into information for one multi-frame.
The cell overhead adding circuit 12 is divided into 8 bytes each.
Adds the cell overhead (shown as "OH" in the figure) to the 48-byte information and sends it to the ATM network 13.

FIG. 3 is a diagram for explaining the decelling operation by the cell synchronization circuit 14, the cell inverse conversion circuit 15 and the timing generation circuit 17. The cell synchronization circuit 14 recognizes the cell, and the cell inverse conversion circuit 15 removes the 5-byte overhead of the cell. It is possible to detect the multiframe phases of all channels at the output point of the cell inverse conversion circuit 15, and it is possible to establish multiframe phase synchronization. In addition, even if a cell drop occurs, the information for exactly one multiframe is lost, so even if there is no function for managing the sequence of cells, there is no loss of multiframe synchronization in the output STM signal.

In the above description, the case where an STM signal having a frame structure of one channel is input from each input terminal has been described. However, a plurality of channels having the same multi-frame structure are time-division multiplexed to each input terminal. The present invention can be implemented in the same manner when input is made by inputting. FIG. 4 shows an example of cell formation in such a case. Here, the input terminal #
i will be described as an example. In this example, four multiframes each composed of three frames are time-division multiplexed. Although these multiframes have time slot shifts, the multiframe phases are the same from the viewpoint of the unit of multiplexing. Even in such a case, in the cell conversion circuit 11 and the cell overhead adding circuit 12,
This time division multiplexed signal is made into cells without being separated. In the cell synchronization circuit 14 and the cell inverse conversion circuit 15,
A plurality of series of STM signals having the same multi-frame phase are generated from the ATM signals that are individually cellized for each input terminal. Similarly, in the case where there is only one input terminal, a plurality of channels having the same multi-frame structure are time-division multiplexed S.
The TM signal can be converted into an ATM signal and transmitted.

FIG. 5 is a diagram showing the flow of the entire operation.
On the transmission side, the multi-frame phase of the STM signal input from the input terminal is detected, and the multi-frame phase information is used to create m multi-frames of n channels (n and m are both 1 or more) in the same cell. It is converted into a cell containing information, cell overhead is added, and the cell is output to the ATM network. On the receiving side, the cell phase of the input ATM signal is detected,
Using the cell phase information, it is inversely converted into an STM signal having a required multi-frame phase timing.

When the information for m multi-frames of n channels is less than 48 bytes, an appropriate byte is inserted so as to be 48 bytes and is input to the cell conversion circuit 11, which is then inserted by the cell inverse conversion circuit 15. Delete the byte that was created.

With such a configuration, on the receiving side,
It is possible to establish multiframe phase synchronization for the channel without using a multiframe phase synchronization circuit. In addition, it is possible to prevent the occurrence of out-of-synchronization of multiframes without using the function of managing the sequence of cells. Therefore, the circuit scale can be reduced, the transmission efficiency can be improved, and the processing time can be shortened as compared with the conventional technique.

[0020]

As described above, the asynchronous transmission apparatus of the present invention utilizes the multi-frame phase of the input signal,
Information for m multiframes of n channels (n and m are both 1 or more) is accommodated in one cell. Therefore, on the receiving side, it is possible to establish multi-frame phase synchronization for all channels at the same time when cell synchronization is established, and a multi-frame phase synchronization circuit is unnecessary. Also,
Even when cell loss occurs, it is possible to prevent the occurrence of multi-frame desynchronization in the output STM signal without using the function of managing the cell sequence. Therefore, the circuit scale can be reduced, the transmission efficiency can be improved, and the processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an asynchronous transmission device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a cell formation operation.

FIG. 3 is a diagram illustrating a deceleration operation.

FIG. 4 is a diagram showing an example of cell formation when a plurality of channels having the same multi-frame structure are time-division multiplexed and input to individual input terminals.

FIG. 5 is a diagram showing the flow of the entire operation.

FIG. 6 is a block diagram showing a conventional asynchronous transmission device.

FIG. 7 is a diagram for explaining cell formation in a conventional example.

FIG. 8 is a diagram illustrating deceleration of a conventional example.

FIG. 9 is a diagram illustrating an operation of establishing multiframe phase synchronization in the conventional example.

[Explanation of symbols]

 11, 21 Cell conversion circuit 12, 22 Cell overhead adding circuit 13, 23 ATM network 14, 24 Cell synchronization circuit 15, 25 Cell inverse conversion circuit 16 Multi-frame phase detection circuit 17, 27 Timing generation circuit 26 Multi-frame phase synchronization circuit

Claims (4)

[Claims] 1. Cellizing means for converting a signal in the synchronous transfer mode into a cellized signal in the asynchronous transfer mode and outputting the cellized signal to the asynchronous transfer mode network, and a cellized signal input from the asynchronous transfer mode network. In the asynchronous transmission device provided with a de-cellizing means for converting into a signal of a synchronous transfer mode, the signal of the synchronous transfer mode is a signal of a plurality of series having the same multi-frame structure and multi-frame phase matching each other, the cell The conversion means includes means for detecting a multi-frame phase of the signals of the plurality of series, and means for accommodating one or a plurality of multi-frame information as a unit in one cell based on the detected multi-frame phase, The decellizing means detects the cell phase of the cellified signal and a required multi-frame based on the detected cell phase. Asynchronous transmission apparatus characterized by including means for inverse converting the signal of the synchronous transfer mode having a beam phase timing. 2. The plurality of series of signals are signals input from different input terminals respectively, and the accommodating means includes means for individually converting the signals input from the different input terminals into cells. 2. The asynchronous transmission apparatus according to claim 1, wherein the means for performing the inverse conversion includes means for generating a plurality of series of signals having the same multi-frame phase from the separately cellized signals. 3. The signals of the plurality of sequences are signals in which a plurality of channels having the same multi-frame structure are time-division multiplexed, and the accommodating means converts the time-division multiplexed signals into cells without separating them. The asynchronous transmission device according to claim 1, further comprising means. 4. The plurality of series of signals are signals input from a plurality of input terminals and time-division multiplexed of a plurality of channels each having the same multiframe structure, and the accommodating means receives the plurality of input terminals from the plurality of input terminals. 2. A means for individually converting the input signals into cells, and the inverse transforming means includes means for generating a plurality of series signals having the same multi-frame phase from the separately cellized signals.
Asynchronous transmission device described.