JPH0936930A - Communication control circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] A communication control circuit that transfers data by connecting different standard interfaces and enables high-speed processing with a relatively simple configuration. [Composition] A communication control circuit for transmitting and receiving data by converting one standard interface such as RS-232C to the other standard interface such as RS-422, and the voltage level between input and output signals, balanced-unbalanced, etc. Driver / receiver 2 that performs conversion of data, transmitter / receiver 4 that performs synchronization detection of transfer data, serial / parallel conversion, transfer mode selection, parity check, and the like, and sets mode parameters for this transmitter / receiver 4 and operates Command write, data write, command read,
It has a configuration including a control unit 3 which controls data reading within one system clock and random access memories 7 and 8 which temporarily store data for one block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control circuit for performing interface conversion between a device such as a data transmission device and a device such as a personal computer for connection.
When an external personal computer (personal computer) monitors or tests the data transmission device, the data transmission device includes, for example, an RS-422 interface,
Since a personal computer is generally provided with an RS-232C interface, for example, it is necessary to perform interface conversion before connection. There is a demand for more efficient communication control circuits that are connected by performing such interface conversion.

[0002]

2. Description of the Related Art FIG. 7 is an explanatory view of a conventional example, 51 is a personal computer, 52 is a data transmission device, 53 is a communication control circuit,
Reference numerals 54 and 55 are interface circuits (INF), and 56 is a unit. The data transmission device 52 is configured by a plurality of units 56, the interface circuit 55 and the inside have a configuration to which RS-422 of a standard interface is applied, and the interface circuit 54 of the personal computer 51.
Generally has a configuration to which the standard interface RS-232C is applied.

Therefore, the personal computer 51 and the data transmission device 5
Communication control circuit 5 for interface conversion between 2 and
3 is connected via the communication control circuit 53 to transmit commands and data from the personal computer 51 to monitor and test the data transmission device 52 and monitor and test the unit 56.
Will be done through.

The standard interface RS-232C is an unbalanced type interface, and the standard interface RS-422 is a balanced type interface. FIG.
FIG. 4 is an explanatory diagram of a balanced type and unbalanced type interface circuit, (A) shows a balanced type interface circuit, and (B).
Indicates an unbalanced interface circuit. Further, 61 is a driver, 62 is a receiver, 63 is a terminating resistor, A is a positive output terminal, B is a negative output terminal, and C is a ground terminal.

In the balanced type interface circuit shown in FIG. 8A, the positive and negative output terminals A and B of the triber 61 and the input terminal of the receiver 62 are connected to each other by a cable. Further, in the unbalanced interface circuit shown in FIG. 8B, the positive output terminal A and the ground terminal C of the driver 61 are connected to each other by a cable so as to be connected to the input terminal of the receiver 62. .

The above-mentioned standard interface RS-232
C is connected to each other by applying the configuration of the unbalanced interface circuit of FIG. 8B, and the signal level is "1" in the range of -5V to -15V and "0" in the range of "0". + 5V
It is specified to be in the range of + 15V. Further, the data transfer is serial data transfer to which either the synchronous system or the asynchronous system is applied. The standard interface R mentioned above
The S-422 is configured to be connected to each other by applying the configuration of the balanced interface circuit of FIG. 8A, and the signal level is "1" with respect to the positive output terminal A to the negative output terminal B. Negative, “0” means that the positive output terminal A is positive with respect to the negative output terminal B, and between the positive and negative output terminals A and B and the positive and negative output terminals A,
Output open circuit voltage between B and ground terminal is 6V or less, 50
Output voltage at Ω termination is 2V or more or output open voltage is 5
It is specified to be 0% or more. The standard interface RS-423 has almost the same contents as RS-422, but is applied to an unbalanced interface circuit.

The communication control circuit 53 in FIG. 7 is the standard interface RS-2 on the personal computer 51 side as described above.
The interface conversion between the 32C and the standard interface RS-422 on the data transmission device 52 side is performed, and the conversion process is performed by software.

FIG. 9 is a flow chart of a conventional example and shows an outline of the operation of the communication control circuit 53 in FIG. First, reset (A), then set the mode parameter (B), determine whether or not it is the synchronous mode (C), move to step (H) if it is not the synchronous mode, and if it is the synchronous mode, It is judged whether or not it is the double synchronization system (D), and if it is not the double synchronization system, the process proceeds to step (G), the synchronization character 1 is written, and the process proceeds to step (H). In the case of the double synchronization method, the synchronization character 1 is written (E), then the synchronization character 2 is written (F),
Go to step (H).

In step (H), the operation command is written, then the status is read, the operation command is written, the reception data is read, and the transmission data is written (I). Then, it is determined whether the status is a command or data (J), and if the status is the status, the status is read and the control terminal (CONT terminal) is set to "1" (K). In the case of data, transmission / reception data is written and read, and the control terminal (CONT terminal) is set to "0" (L). If it is a command, the operation command is written, the control terminal (CONT terminal) is set to "1" (M), it is judged whether or not it is a software reset (N), and if it is a reset, the process moves to step (B). If it is not reset, the process proceeds to step (J).

[0010]

As described above, the communication control circuit 53 of the conventional example has RS-232C, RS-422.
The conversion processing is performed by software between different standard interfaces such as the above, and the transmission / reception is controlled by software processing as shown in FIG. For example, in conversion processing by software, it takes about 80 steps to process 1 byte, and software also performs other processing, so data between devices having different standard interfaces It was not easy to control transfer at high speed. An object of the present invention is to enable high speed transfer of data between devices having different standard interfaces with a relatively simple structure.

[0011]

The communication control circuit of the present invention will be described with reference to FIG. 1 in which one type of standard interface such as RS-232C to another type of standard interface such as RS-422. In a communication control circuit that converts data into an interface and transmits / receives data, a driver / receiver 2 for converting one or both of a voltage level between input / output signals and balanced-unbalanced, and this driver / receiver 2 A transmitter / receiver 4 that is connected to the device and performs synchronization detection of data to be transferred, serial / parallel conversion, selection of transfer mode, data parity check, etc.
A mode parameter is initialized to the transmitter / receiver 4, and the transmitter / receiver 4 is repeatedly controlled in the operation command write, data write, command read, and data read operation modes at every cycle of the system clock signal. The control unit 3 is provided for performing conversion processing between the standard interface of one format and the standard interface of the other format.

Further, the timing between the transmitter / receiver and the device of the standard interface of one type or the standard interface of the other type is controlled by the control unit 3, and at least one block of data is temporarily stored. Random access memories 7 and 8 for accumulating can be provided.

Further, the random access memories 7 and 8 can be constituted by dual port random access memories.

Further, the control unit 3 has a setting unit 14 for setting a mode parameter manually or externally input, and a configuration for setting the mode parameter of the setting unit 14 in the mode register 15 of the transmitter / receiver 4 at the time of initial setting. Can be prepared.

[0015]

[Function] The standard interface for personal computers is RS-23
2C is a communication control circuit connected between a device 1 such as 2C and a standard interface such as a data transmission device and a device 11 such as RS-422, and in the driver / receiver 2, signal level conversion and balance- Unbalance conversion is performed, and according to the mode parameters set by the control unit 3 and timing control from the control unit 3, synchronous detection or serial / parallel conversion is performed depending on the operation mode of operation command write, data write, command read, and data read. And then
Transfer data by converting between different standard interfaces.

Also the transmitter / receiver 4 and the device 11
Random access memories 7 and 8 are arranged between and. The random access memories 7 and 8 temporarily store data with the device 11 under the timing control of the control unit 3 and serve as a buffer.

When the random access memories 7 and 8 are dual port random access memories, it is possible to read and write data simultaneously.
The control by the control unit 3 becomes easy.

The setting unit 14 of the control unit 3 is composed of a plurality of setting switches and the like, and sets mode parameters such as synchronous, asynchronous, baud rate, parity check presence / absence, and the like. The mode parameter set to (1) is set in the mode register 15 of the transmitter / receiver 4.

[0019]

1 is an explanatory view of an embodiment of the present invention, in which 1 is a standard interface of one type, for example RS-232.
C device (hereinafter referred to as a personal computer), 2 is a driver / receiver, 3 is a control unit, 4 is a transmitter / receiver,
5, 6 are transmission registers and reception registers, 7, 8 are random access memories, 9 is a receiver, 10 is a driver,
11 is a standard interface of the other type, for example RS-
422 device (hereinafter referred to as data transmission device), 12 is R
Interface circuit (IF) of S-232C, 13 is R
An interface circuit (IF) of S-422, 14 is a setting unit, and 15 is a mode command register.

The control unit 3 includes a setting unit 14 for setting a mode parameter and a transmission / reception clock signal, and a processor (not shown) for performing logic control, a clock generation unit, a distribution unit, and the like. Further, the driver / receiver 2 is composed of, for example, as shown in FIG. 8, a driver 61 having a positive / negative output terminal and a receiver 62 having a differential amplifier configuration, and the positive / negative output terminals A and B and the ground terminal C are provided. By selective connection, data transmission / reception by balanced-balanced, balanced-unbalanced, etc. is performed. Also personal computer 1
Since the standard interface of RS-232C is RS-232C, it becomes an unbalanced interface circuit with the driver / receiver 2.

The transmission register 5 and the reception register 6 are
It corresponds to a latch circuit when transferring 1-byte data in parallel with the transmitter / receiver 4. The random access memories 7 and 8 have a capacity capable of temporarily storing one block of data, and the control unit 3 controls reading and writing of data. It can also be a dual port random access memory.
Further, the receiver 9 and the driver 10 are the data transmission device 11
Data is transmitted / received to / from the interface circuit 13 according to the standard interface RS-422. That is, it becomes a balanced type interface circuit.

The transmitter / receiver 4 connected to the driver / receiver 2 has, for example, the configuration shown in FIG. In the figure, 20 is a control logic unit,
21 is a mode register, 22 is a command register, and 23.
Is a status register, 24 is a transmission data buffer register, 25 is a reception data buffer register, 26 is a synchronous character register, 27 is a transmission buffer / transmission unit, 2
8 is a reception buffer / reception unit, 29 is a modem control unit, 30
Indicates an internal bus and 31 indicates a data bus, which are integrated into a semiconductor integrated circuit (IC).

The control logic unit 20 is connected to the control unit 3 shown in FIG. 1 and controls each unit according to a clock signal from the control unit 3. Further, the mode register 21 is used by the control unit 3
The mode parameter set in the setting unit 14 is set at the time of initial setting such as power-on. Further, the command from the control unit 3 or the like is written in the command register 22. The status register 23 holds the status of the transmission data buffer register 24 and the reception data buffer register 25, the status of the signal line connected to the modem control unit 29, and status information such as error information.

The transmission data buffer register 24 holds transmission data added from the transmission register 5 (see FIG. 1) via the data bus 31 and transfers it to the transmission buffer / transmission unit 27. In addition, the reception data buffer register 25
Holds the data from the reception buffer / reception unit 28,
The received data is sent to the receiving register 6 (see FIG. 1) via the data bus 31. The sync character register 26 holds one or two sync characters next to the mode parameter in the sync mode. When data is received, this sync character is compared with the received character, and a comparison match is made. Sometimes synchronization is established.

Further, the transmission buffer / transmission unit 27 converts the parallel data transferred from the transmission data buffer register 24 into serial data and adds a start bit, a stop bit, a parity bit, etc. to the driver / driver.
It is sent to the receiver 2 (see FIG. 1). Also receive buffer
The reception unit 28 converts the serial reception data from the driver / receiver 2 (see FIG. 1) into parallel data, checks it according to the mode parameter, edits it, and transfers it to the reception data buffer register 25. In that case, the start bit and the stop bit are detected in the start-stop synchronization mode, the parity bit is checked, and the like, and the synchronization character is detected and the parity bit is checked in the synchronization mode. The modem control unit 29 is a control unit when a modem is connected.

FIG. 3 is an explanatory diagram of the setting of the mode parameters, in which a part of the setting unit 14 of the control unit 3 is provided with the switches SW1 to SW.
The case where it is configured by W8 is shown. Also switches SW1 to S
The data bit depending on ON (ON) and OFF (OFF) of W8 indicates a case where BIT7 to BIT0 correspond. The data bit baud rate is set by the switches SW1 and SW2, the character bit length is set by the switches SW3 and SW4, the presence or absence of parity check is set by the switches SW5 and SW6, and the switches SW7 and SW8.
The stop bit length can be set by.

Therefore, the setting state shown in the figure, that is, SW1 =
A baud rate of 2400 bps is set by OFF and SW2 = ON, a character bit length of 8 bits is set by SW3 = ON and SW4 = ON, and SW5 =
No parity check can be set by OFF and SW6 = OFF, and the stop bit length can be set to 1 bit by SW7 = ON and SW8 = OFF. Various small manual setting switches can be applied to the switches SW1 to SW8. It is also possible to configure the setting unit 14 with a memory and set the mode parameter from the personal computer 1.

FIG. 4 is an explanatory diagram of the setting of the transmission / reception clock, in which a part of the setting unit 14 of the control unit 3 is set by the setting devices TM1 and TM
2 shows the case of TM6. Setting device TM1
Shows the case where the contacts 2 and 3 are short-circuited, the setting device TM2 short-circuits the contacts 1 and 2, and the setting device TM6 shows the case where the contacts 2 and 3 are short-circuited, whereby the baud rate clock signal is The case of setting to 384 kHz is shown.

FIG. 5 is a timing explanatory diagram of the embodiment of the present invention. (R) shows a read timing signal, (W) shows a write timing signal, (CMDT) shows a command timing signal, and a read timing signal (R). The write timing signal (W) is synchronized with the system clock signal. In addition, one cycle of this system clock signal is 4
It is divided into (R) = "1", (W) = "0", (CMD
T) = “1” period, operation command write, (R) =
Data write during the period of "1", (W) = "0", (CMDT) = "0", (R) = "0", (W) = "1",
Command read during (CMDT) = "1" period, (R)
Data read is performed during a period of "0", (W) = "1", (CMDT) = "0".

Control unit 3 to transmitter / receiver 4
Of the read timing signal (R), the write timing signal (W), and the command timing signal (CMD) synchronized with the system clock signal.
T) is added, the control logic unit 20 controls each unit according to the periods of operation command write, data write, command read, and data read. For example, 1 byte of data is transmitted during the data write period, and 1 byte of data is received during the data read period. In this case, since it is easy to increase the speed of each timing signal, it is possible to increase the speed of transmission / reception data corresponding to the speed of each timing signal.

FIG. 6 is a diagram for explaining the operation of the embodiment of the present invention. Mode parameter set in advance in the setting unit 14 of the control unit 3 by power-on or system reset (1),
It is set in the mode register 15 of the transmitter / receiver 4 (2). Then, in accordance with the timing shown in FIG. 5, the operation command write (3), the data write (4),
Command read (5) and data read (6) operations are performed, and it is determined whether or not the processing is completed (7). If not completed, the process proceeds to step (3). When the operation is finished, the power is turned off, for example.

For example, from the personal computer 1 to the data transmission device 1
1, when 72 bytes of data is transmitted at a speed of 2400 bps by start-stop synchronization, the mode parameters shown in FIG. 3 are set in the mode register 15 of the transmitter / receiver 4, and the interface circuit 12 of the personal computer 1 drives the driver / receiver 2 In addition, RS of standard interface
It is transmitted as serial data according to -232C.

The transmitter / receiver 4 converts serial data into 8-bit parallel data by synchronous detection, latches 1-byte data in the reception register 6, and writes the 1-byte data in the random access memory 8. As described above, the random access memory 8 has a capacity capable of accommodating a predetermined byte as one block. Then, the data read from the random access memory 8 is transferred as serial data to the interface circuit 13 of the data transmission device 11 via the driver 10. In this case, the control unit 3 includes an address counter (not shown) and the like, generates write addresses and read addresses of 0 to 71 with respect to the random access memory 8, and controls writing and reading of data. .

Data from the data transmission device 11 to the personal computer 1 is transferred to the interface circuit 13, receiver 9,
The data is transferred through the path of the random access memory 7, the transmission register 5, the transmitter / receiver 4, and the driver / receiver 2. When the random access memories 7 and 8 are dual port random access memories, since both ports have address control lines, data can be read and written without switching between read and write, and control can be performed. It will be easy.

Further, the personal computer 1 can be configured to set or confirm the mode parameters and commands set in the mode register 15 and command register of the transmitter / receiver 4, for example, the contents of the mode register and the command register. Can be transferred in byte units.

In the above-described embodiment, the standard interface R
The case of data transfer by interface conversion between S-232C and RS-422 is shown, but the present invention can be applied to the case of using another standard interface such as RS-423 or V10, V11. It is also possible to omit the transmission register 5, the reception register 6 and the like. Further, the transmitter / receiver 4 can be configured to have processing functions other than the configuration shown in FIG.

[0037]

As described above, according to the present invention, when data is transferred by interface conversion between different standard interfaces, it is configured to be controlled by timing by hardware, and high speed processing is possible. For example, when a personal computer 1 having a standard interface of RS-232C monitors and tests the data transmission device 11 having a standard interface of RS-422, data transmission / reception can be performed with a relatively simple configuration and at high speed. There is an advantage that can be. Random access memory 7,
By interposing 8 between them, stable transmission / reception of data consisting of a plurality of bytes becomes possible.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a control unit according to the embodiment of this invention.

FIG. 3 is an explanatory diagram of setting mode parameters.

FIG. 4 is an explanatory diagram for setting a transmission / reception clock.

FIG. 5 is a timing explanatory diagram of the embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 7 is an explanatory diagram of a conventional example.

FIG. 8 is an explanatory diagram of a balanced type and unbalanced type interface circuit.

FIG. 9 is a flowchart of a conventional example.

[Explanation of symbols]

 1 personal computer 2 driver / receiver 3 control unit 4 transmitter / receiver 5 transmission register 6 reception register 7, 8 random access memory 9 receiver 10 driver 11 data transmission device 12, 13 interface circuit (IF) 14 setting unit 15 mode register

Claims (4)

[Claims] 1. A communication control circuit for converting a standard interface of one type into a standard interface of the other type for transmitting and receiving data, wherein one of a voltage level between input and output signals and balanced-unbalanced Or a driver / receiver for performing both conversions, and a transmitter / receiver connected to the driver / receiver for performing synchronization detection of data to be transferred, serial / parallel conversion, transfer mode selection, data parity check, and the like, A mode parameter is initialized in the transmitter / receiver, and the transmitter / receiver is repeatedly controlled in each of operation clock write, data write, command read, and data read operation modes at every cycle of the system clock signal. Format standard interface and the other format standard interface A communication control circuit, comprising: 2. The timing between the transmitter / receiver and the device of the standard interface of one type or the standard interface of the other type and the timing is controlled by the control unit, and at least one block of data is stored. The communication control circuit according to claim 1, further comprising a random access memory for temporarily storing the random access memory. 3. The communication control circuit according to claim 2, wherein the random access memory is a dual port random access memory. 4. The control unit comprises a setting unit for setting a mode parameter manually or externally input, and a configuration for setting the mode parameter of the setting unit in a mode register of the transmitter / receiver at the time of initial setting. The communication control circuit according to claim 1, wherein: