JPH0937288A - Digital correction circuit and method for correcting digital signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To configure the circuit economically by eliminating the need for a high speed CPU in the case of correcting an amplitude and a phase of an IQ signal. SOLUTION: I1, Q1 signals separated by a demodulation circuit 2 synchronously with a clock fs are selected alternately by selection circuits 3, 4 for each clock and outputted to multiplier circuits 5, 6, which multiply correction coefficients C1, C2 from a CPU 11 with the signals respectively and a sign of the signal from one multiplier circuit is inverted at an interval of one clock and the output signal and an output signal of the other multiplier circuit are synthesized and the synthesis signal is inverted at an interval of two clocks. As a result, a fixed value is adopted for the correction coefficient. Thus, it is not required for the CPU to provide an output of each correction coefficient synchronously with the clock of an input signal and the circuit is configured with a low speed and inexpensive CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital correction circuit and a digital signal correction method for correcting the amplitude and phase of an input digital signal.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the configuration of a conventional digital correction circuit of this type. In the figure, 2 is a demodulation circuit that divides an input signal input from the input terminal 1 into orthogonal I and Q signals, and 5 and 6 are output by multiplying the divided I and Q signals by correction coefficients. Multiplier circuit, 8
Is an adder circuit for adding the corrected I and Q signals, 9 is a sign inversion circuit that inverts the signals added by the adder circuit 8 every two clocks and outputs from the output terminal 10, 11 is each of the multiplier circuits 5, 6 Is a CPU that outputs a correction coefficient.

FIG. 4 is a timing chart showing the operation of each section of such a digital correction circuit. The operation of the digital correction circuit will be described based on this timing chart. In the demodulation circuit 2, the digital input signal input from the digital signal input terminal 1 is divided into orthogonal I1 and Q1 signals as shown in FIGS. 4 (b) and 4 (e) based on the clock fs shown in FIG. 4 (a). Multiplication circuits 5 and 6 respectively
Is output to In the multiplication circuit 5, when the I1 signal is input, the CPU 11 outputs the I1 signal.
The correction coefficients C1 and -C2 in (c) are multiplied and the signal shown in FIG. Further, in the multiplication circuit 6, when the Q1 signal is input, the CPU responds to this Q1 signal.
The signal shown in FIG. 4 (g) is output to the adder circuit 8 by multiplying the correction coefficients C1 and C2 of FIG.

I1, Q1 thus multiplied by the correction coefficient
The signals are added by the adder circuit 8 and the added signal as shown in FIG. And
This addition signal is sign-inverted by the sign inverting circuit 9 every two clocks shown in FIG. 4 (i), and is output from the digital signal output terminal 18 as a signal shown in FIG. 4 (j). As a result,
For the input signals I1 and Q1 signals, the following equation (1)
The matrix operation shown by is performed to obtain the output signals I2 signal and Q2 signal. Therefore, the correction coefficient C
The phase and amplitude of the input signal are corrected by 1, C2 or -C2, and the corrected I2 signal and Q2 signal are output.

[0005]

[Equation 1]

[0006]

In the conventional digital correction circuit, when the phase and amplitude of the input signal are corrected, the CP
As shown in FIGS. 4C and 4F, U switches the correction coefficient in synchronization with the clock of the input signal and supplies the switched correction coefficient to each multiplication circuit to correct the amplitude and phase of the IQ signal. I am trying. Therefore, a high-speed CPU that operates at the clock rate of the input signal is required, and the circuit becomes expensive. Therefore, an object of the present invention is to economically configure the circuit by eliminating the need for a high-speed CPU when correcting the amplitude and phase of the IQ signal.

[0007]

In order to solve the above problems, the present invention provides a demodulation circuit for separating an input signal into orthogonal IQ signals and a clock signal extracted from the input IQ signal. The sign of the signal from the selection circuit that outputs the selection circuit by alternately switching in synchronization with each other, the first and second multiplication circuits that multiply the output of the selection circuit by the correction coefficient, and the sign of the signal from the one multiplication circuit that multiplied the correction coefficient A first sign inverting circuit that inverts every 2 times the cycle, and an adder circuit that combines the output of the first sign inverting circuit and the output of the other multiplying circuit,
And a second code inversion circuit that inverts the code of the combined signal every four times the cycle of the clock signal.
As a result, the amplitude and phase of the IQ signal can be corrected by the fixed correction coefficient. Therefore, the CPU does not need to switch the correction coefficient at the clock rate and give it to the multiplication circuit, so that control can be performed by an inexpensive low-speed CPU. Therefore, the circuit can be economically constructed.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital correction circuit according to the present invention. In the figure, the demodulation circuit 2, the multiplication circuits 5 and 6, the addition circuit 8, and the sign inversion circuit 9 are the same circuits as the conventional digital correction circuit shown in FIG. In addition, in the present invention, the conventional circuits are provided with the selection circuits 3 and 4, the sign inversion circuit 7, and the like. FIG. 2 is a timing chart showing the operation of each part of this digital correction circuit. The main operation of the present invention will be described based on this timing chart and the block diagram of FIG.

In the demodulation circuit 2, the digital signal input to the digital signal input terminal 1 is the orthogonal I1 signal,
It is divided into Q1 signals. These I1, Q1 separated
The signals are alternately switched by the selection circuits 3 and 4 once every ½ of the frequency of the clock fs shown in FIG. 2A (that is, every period of twice the clock fs). It is output as a signal as shown in b) and (e).
That is, as described above, the I1 signal and the Q1 signal synchronized with the clock fs shown in FIGS. 4B and 4E are output from the demodulation circuit 2 to the selection circuit 3, but the selection circuit 3 Then, an I1 signal is output while the clock signal of 1/2 frequency of the clock fs shown in FIG. 2 (h) is at "H" level, and a Q1 signal is output while this clock signal is at "L" level. To work. Further, the selection circuit 4 which inputs this clock signal through the inverter 12 performs an operation opposite to that of the selection circuit 3 when the I1 signal and the Q1 signal are inputted. That is, while the clock signal shown in FIG. 2 (h) is at "H" level, the Q1 signal is output and this clock signal is at "L".
The I1 signal is output during the level.

Here, the signal output from the selection circuit 3 is multiplied by the correction coefficient C1 of FIG. 2 (c) output from the CPU 11 by the multiplication circuit 5 to obtain a signal shown in FIG. 2 (d). It is output to the adder circuit 8. Further, the signal output from the selection circuit 4 is multiplied by the correction coefficient C2 of FIG. 2 (f) output from the CPU 11 by the multiplication circuit 6, and the sign inversion circuit 7 outputs the signal shown in FIG. 2 (g).
Is output to In this case, the sign inversion circuit 7 inverts the sign of the signal output from the multiplication circuit 6 for each clock signal shown in FIG. 2 (h) (that is, twice the cycle of the clock fs), and FIG. As the sign inversion signal shown in FIG.
Output to That is, the sign inversion circuit 7 inverts the sign only while the clock signal of FIG. 2 (h) obtained by dividing the clock fs shown in FIG. 2 (a) by 2 is "L" level, and when it is at "H" level. No sign inversion.

The adding circuit 8 adds the output signal of the sign inverting circuit 7 and the output signal of the multiplying circuit 5, and shows the same addition signal of FIG. 4 (h) as shown in FIG. 2 (j). The addition signal is output to the sign inverting circuit 9. In the sign inverting circuit 9, 1 / the frequency of the clock fs as shown in FIG.
The input signal is sign-inverted every 4 (that is, four times the cycle of the clock fs), and the correction signal shown in FIG. 2 (l) similar to the correction signal of FIG. 4 (j) already described is output to the digital signal output terminal. Output from 10. That is, the sign inverting circuit 9 is
The sign is inverted only while the clock fs shown in (a) is divided by 4 and the clock of FIG.
Do not invert the sign between levels.

In this way, in the digital correction circuit,
The I1 signal and the Q1 signal separated in synchronization with the clock fs in the demodulation circuit 2 are alternately selected by the selection circuits 3 and 4 every one clock and output to the multiplication circuits 5 and 6, respectively. Then, while multiplying these signals by the correction coefficients C1 and C2 from the CPU 11, respectively, the sign of the signal from one of the multiplying circuits is inverted every other clock, and this output signal and the output of the other multiplying circuit are output. The signal is combined with the signal and the combined signal is inverted every two clocks. As a result, the correction coefficients C1 and C2 output from the CPU 11 can be fixed values as shown in FIGS. 2 (c) and 2 (f). Therefore, even if the CPU 11 does not switch and output each of these correction coefficients in synchronization with the clock of the input signal, this correction circuit performs the matrix calculation shown in the equation (1) already described in real time to obtain the input signal. The phase and amplitude can be accurately corrected.

As described above, the I signal and the Q signal obtained separately from the input signal are switched in synchronization with the clock of the input signal to realize the correction calculation of the phase and amplitude of the input signal. , It becomes unnecessary to switch the correction coefficient output from the CPU 11 for each clock rate,
Therefore, a circuit having the same performance as the conventional circuit can be constructed by using a low-speed and inexpensive CPU. As a result,
The digital correction circuit can be economically constructed.

[0014]

As described above, according to the present invention, an input digital signal is synchronized with a clock signal to be separated into orthogonal I and Q signals, and the separated I and Q signals are synchronized with the clock signal. Then, the I signal and the Q signal which have been switched are respectively multiplied by the correction coefficient, and the sign of one of the signals multiplied by the correction coefficient is inverted every double period of the clock signal. Since the output and the other signal which is multiplied by the correction coefficient and whose sign is not inverted are combined and the sign of the combined signal is inverted every four times the cycle of the clock signal, the fixed correction coefficient of the IQ signal is used. Since the amplitude and phase can be corrected, it is not necessary for the CPU that gives the correction coefficient to switch the correction coefficient at the clock rate, and as a result, an inexpensive low-speed CPU can be provided. Since the control is enabled Ri, economically constitute a circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital correction circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the digital correction circuit.

FIG. 3 is a diagram showing a configuration of a conventional circuit.

FIG. 4 is a timing chart showing the operation of a conventional circuit.

[Explanation of symbols]

2 ... Demodulation circuit, 3, 4 ... Selection circuit, 5, 6 ... Multiplication circuit,
7, 9 ... Sign inversion circuit, 8 ... Addition circuit, 11 ... CPU.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] April 5, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction contents]

FIG. 4 is a timing chart showing the operation of each section of such a digital correction circuit. The operation of the digital correction circuit will be described based on this timing chart. The digital input signal input from the digital signal input terminal 1 is divided in the demodulation circuit 2 into orthogonal I1 and Q1 signals as shown in FIGS. 4B and 4E based on the clock fs shown in FIG. Multiplication circuits 5 and 6 respectively
Is output to In the multiplying circuit 5, when the I1 signal is input, the CPU I1 outputs the I1 signal as shown in FIG.
The correction coefficients C 1 and C 2 shown in (c) are multiplied and the signal shown in FIG. Further, in the multiplication circuit 6,
When the Q1 signal is input, the CPU 11 responds to this Q1 signal.
Figure 4 correction factor C1 in (f) which is output from, - C2 to multiply outputs a signal shown in FIG. 4 (g) to the addition circuit 8.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005]

[Equation 1]

[Procedure 3]

[Document name to be amended] Drawing

[Correction target item name] Figure 2

[Correction method] Change

[Correction contents]

[Fig. 2]

[Procedure amendment 4]

[Document name to be amended] Drawing

[Correction target item name] Fig. 4

[Correction method] Change

[Correction contents]

FIG. 4

Claims (2)

[Claims] 1. A digital correction circuit for correcting the phase and amplitude of an input digital signal, comprising: a demodulation circuit for separating the input digital signal into orthogonal I and Q signals in synchronization with a clock signal; A selection circuit for alternately switching and outputting the I signal and the Q signal in synchronization with the clock signal, and first and second multiplication circuits for multiplying the I signal and the Q signal switched by the selection circuit by a correction coefficient, respectively. A first sign inversion circuit that inverts and outputs the sign of one of the signals multiplied by the correction coefficient for each cycle of twice the clock signal, the output of the first sign inversion circuit, and the sign that is multiplied by the correction coefficient and has the sign An addition circuit for synthesizing the other signal which is not inverted, and a second code inverting circuit for inverting and outputting the code of the synthesized signal every four times the cycle of the clock signal. That digital correction circuit. 2. A digital correction circuit for correcting the phase and amplitude of an input digital signal, separating the input digital signal into orthogonal I and Q signals in synchronization with a clock signal, and separating the separated I and Q signals. The signals are alternately output in synchronization with the clock signal, and the I and Q signals that have been switched are each multiplied by a correction coefficient, while the sign of one of the signals multiplied by the correction coefficient is twice as long as the clock signal. Each output is inverted, and this output is combined with the other signal which is multiplied by the correction coefficient and whose sign is not inverted, and the sign of the combined signal is inverted every four times the cycle of the clock signal. Digital signal correction method.