JPH0945593A - Semiconductor chip - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor chip capable of giving an effective clue to wafer process management. In a semiconductor chip obtained by dividing a semiconductor wafer in which a plurality of integrated circuits are arranged and formed into a matrix into individual integrated circuit units, for example, aluminum wirings 2 patterned on the elements of the integrated circuit by a photo process. And an identification symbol (address number 3) formed of the same material as the thin film, the identification symbol representing position data of the semiconductor chip on the semiconductor wafer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip (hereinafter abbreviated as a chip) manufactured by using a semiconductor wafer, and more particularly to a semiconductor chip capable of providing effective clues for wafer process management.

[0002]

2. Description of the Related Art Conventionally, each chip obtained by dividing a semiconductor wafer has a uniform structure and pattern. The glass mask for determining the pattern of the chip is manufactured by a photo process using a pattern generator and a photo repeater, or by a photo process using an electron beam exposure apparatus. The former transfers several patterns of one chip formed on the reticle onto a chrome mask blank in a matrix, and the latter repeatedly reads back the pattern data of one chip magnetically recorded, and repeatedly draws the pattern data. A number of chips are transferred in rows and columns on a chrome mask blank. As a result, a large number of common patterns are uniformly arranged in a matrix on the glass mask.

[0003]

In the manufacturing process of a semiconductor device, the electrical characteristics of each chip are tested after completion of the wafer process, and only chips satisfying a certain condition with respect to a predetermined reference value are passed and assembled. ing. However, even semiconductor devices that incorporate chips that have passed the above tests still have problems such as characteristic changes during the assembly stage and the occurrence of defects during the assembly process, so the test is performed again in the final process. Is the actual situation. However,
If the test fails after the assembly is complete, and there is a suspicion that the cause is due to the wafer process, the failed chip is after being divided from the semiconductor wafer. The position of the tip is unknown. Therefore, there is a problem in that the clues for the cause investigation can be obtained only for each lot of wafers, and feedback can be made to the investigation of variations in chip characteristics within the wafer surface and the investigation of defects caused by masks.

[0004]

In order to solve the above problems, the present invention provides a semiconductor chip obtained by dividing a semiconductor wafer having a plurality of integrated circuits arranged in a matrix into individual integrated circuit units. It has an identification mark formed of the same material as any one of the thin films patterned by the photo process on the element of the integrated circuit, and the identification mark represents position data of the semiconductor chip on the semiconductor wafer. The patterned thin film may be a metal wiring, and the identification mark may be formed by being deposited on the interlayer insulating film on which the metal wiring is deposited. Further, the identification number may be an address number in which a character representing a row and a character representing a column are combined.

[0005]

With this configuration, the identification mark can be visually recognized, and even after the semiconductor wafer is divided into individual chips, it is possible to know where each chip was in the semiconductor wafer by referring to the identification mark. You can

[0006]

1 is a diagram schematically showing an embodiment of the present invention, in which 1 is a chip, 2 is an aluminum wiring, and 3 is an address number. In the chip 1 of this example, a bipolar transistor circuit is formed. Address number 3 consists of a combination of letters that represent rows and numbers that represent columns.
It is formed in the same layer as the aluminum wiring 2 and can be seen through the surface protective film. Further, the address number 3 is arranged apart from the aluminum wiring 2, and in this example, it is formed on the region where the element at one corner of the chip is not formed. Since the address number is aluminum, which is the same as the wiring material, it is important to carefully consider the layout so that parasitic elements such as stray capacitance do not occur.

FIG. 2 is a diagram schematically showing a wafer before the embodiment of FIG. 1 is divided. In this figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding ones, and 4 indicates Silicon wafer, 5 shows a scribe line. As shown in the figure, the chip formed on the silicon wafer 4 has unique address data 3 formed for each chip. FIG. 3 is a diagram schematically showing an example of a glass mask for an aluminum wiring process, in which a pattern 3a corresponding to the address number 3 in FIG. 2, a pattern 5a corresponding to the scribe line 5, and an aluminum wiring pattern not shown are formed. Has been done. The glass mask shown in this figure is a full-scale mask and is made for contact or proximity exposure. When manufacturing this glass mask, use an electron beam mask manufacturing device so that the data of the wiring pattern of each chip to be input and the data of the pattern corresponding to the address number of each chip will be entered and all chip data will be input. If so, the electron beam resist can be patterned by one-time drawing and development.

The address data forming process according to this embodiment will be briefly described below. An oxide film is formed on a silicon wafer on which elements are formed, a contact hole is opened by a photo process, then an aluminum thin film is deposited on one surface by sputtering, and a photoresist is spin-coated on it and prebaked. Here, it is exposed through the glass mask shown in FIG. 3 and then developed. The photoresist thus patterned remains on the silicon wafer, and after post-baking, the aluminum thin film is selectively etched by RIE using this as a mask to form an aluminum wiring pattern and at the same time, an address number is formed. Then
A surface protective film such as a PSG (phosphosilicate glass) film is deposited on the entire surface of the silicon wafer to obtain the silicon wafer 4 having the address numbers shown in FIG. Then, the silicon wafer 4 is divided into each chip through a scribing process, and the embodiment of the present invention shown in FIG. 1 is obtained.

Since this embodiment has such a structure, the address number 3 can be formed on the chip at the same time when the aluminum wiring pattern is patterned on the silicon wafer 4. Further, as described above, since the address number that combines the symbols representing the row and the column is used as the identification symbol, it is easy to confirm, and the address number of the chip and the target chip position can be collated without using a comparison table or the like. Can be done easily. Although the embodiment has been described above, the present invention is not limited to this, and various modifications can be made. For example, in the above embodiment, the address number is adopted as the identification symbol,
It may be a figure in which the serial number or position is embodied. Further, although the chip of the above embodiment is formed with the bipolar transistor circuit, it may be another monolithic circuit such as a MOS transistor circuit. Further, in the above-mentioned embodiment, the identification code is formed of the same aluminum as the aluminum wiring, but it can be formed in the same step as the same material as the element formed by another photo process. For example, when a multi-layer metal film is used for electrodes and the like, one metal used for the multi-layer metal may be used. Similarly,
You may use one of the interlayer insulation films in case a multilayer wiring is given.

[0010]

As described above, since the chip position on the semiconductor wafer can be clarified, even after the semiconductor wafer is divided into individual chips, the in-plane variation inspection and the mask-induced defect inspection can be performed. Further, the address number can be written in the current process, and there is no need to add a new process or increase the management man-hour.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a state of a wafer before being divided in the embodiment of FIG.

FIG. 3 is a diagram showing an example of a glass mask used for manufacturing the embodiment of FIG.

[Explanation of symbols]

 1 chip 2 aluminum wiring 3 address number 4 silicon 5 scribe line 6 glass mask

Claims (1)

[Claims] 1. A semiconductor chip obtained by dividing a semiconductor wafer in which a plurality of integrated circuits are arranged and formed into a matrix into individual integrated circuit units, and a thin film patterned on the elements of the integrated circuit by a photo process. A semiconductor chip having an identification mark formed of the same material as any one of them, wherein the identification mark represents position data of the semiconductor chip on the semiconductor wafer.