JPH0945706A - Semiconductor device - Google Patents

Abstract

Kind Code: A1 In a semiconductor device having a PHS, stress during assembly is reduced and curvature of a semiconductor substrate after assembly is reduced without impairing reliability. In the boundary region of the unit cell 3 of the FET chip, G
Divide the aAs substrate. With such a structure, it is possible to reduce the curvature of the GaAs substrate due to the difference in coefficient of thermal expansion between the GaAs substrate and PHS when heated during assembly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a PHS (plated heat sink) FE.
The present invention relates to a field effect transistor provided in a T chip.

[0002]

2. Description of the Related Art Such a field effect transistor (FE)
A high-power GaAs FET will be described as an example of T).

FIG. 8 is a plan view of a conventional high-power GaAs FET provided with a PHS (plated heat sink) made of a gold plating layer on the back surface of a conventional GaAs substrate, and FIG. 9 is a sectional view taken along line XX of FIG. is there. Here, four unit cells 3 (enclosed by a two-dot chain line) are arranged in parallel to constitute an FET chip. The unit cell 3 has a gate electrode, a drain electrode, and a source electrode. These electrodes are formed on a surface of the active region 2 formed by ion implantation or the like.
f, a comb-like shape having a finger-like source electrode Ff. Two adjacent unit cells are connected by their respective source electrodes S being connected.

A similar structure can be realized by a multi-chip device constructed by collecting a plurality of chips each corresponding to one unit cell. In this case, a positional deviation between the chips or a bonding wire for connecting the chips is required. There are many factors that deteriorate the high-frequency characteristics such as the phase difference of the signal between chips (cells) due to the difference in shape, and it is not practical due to the increased cost in the assembly process.

In order to reduce the thermal resistance, the thickness of the GaAs substrate 1 constituting the FET chip needs to be about 30 to 50 μm, and in order to maintain the strength of the chip, the thickness of the gold-plated PHS 5 needs to be 10 to 30 μm. .

As shown in FIG. 10, when such an FET chip is incorporated into a package 200, the FET chip is heated to a temperature not lower than the melting point of the solder 100.
Since there is a difference in the coefficient of thermal expansion between the PHS5 and the PHS5, the cooled and fixed FET chip is bent by the stress due to the thermal expansion, so that the frequency of occurrence of bonding failure and the like increases, and the assemblability of the FET deteriorates.

To solve such a problem, Japanese Patent Laid-Open Publication No.
Japanese Patent Application Laid-Open No. 3-131555 proposes a structure shown in FIGS. That is, a plurality of PHSs are formed by slits 7-1, 7-2,.
5-1, 5-2,... By adopting such a structure, deformation due to a coefficient of thermal expansion at the time of assembling into a package is suppressed, and assemblability is improved.

[0008]

By the way, if the PHS is simply separated by the slit as described above, the FET chip can be packaged as shown in FIG.
When it is incorporated in 00, it has a wavy shape. A portion without a slit has a two-layer structure of the GaAs substrate 1 and the PHS, and a local curvature occurs due to a difference in thermal expansion coefficient. However, assuming that the electrode portion on the surface is thin and negligible, the slit portion has a single-layer structure of only the GaAs substrate 1, and such a curvature due to a difference in thermal expansion coefficient does not occur. In addition, since this part has no PHS and has low mechanical strength, the chip as a whole does not bend due to the force to press down the chip mechanically or the surface tension due to the molten solder. The GaAs substrate is curved with a very small radius of curvature in the opposite direction as compared to the portion without the slit. In general, the stress on the surface of a thin film when the thin film is deformed is inversely proportional to the radius of curvature and proportional to the film thickness. Therefore, a very large stress is locally concentrated on the GaAs substrate. Specifically, when the thickness of the GaAs substrate is 30 μm, the thickness of the PHS is 15 μm, and the width of the slit is about 1/10 of the slit pitch, a stress of about 500 MPa is generated.

On the other hand, when a stress of about 300 MPa is applied to the GaAs substrate, it is known that a slip transition occurs due to a rise in temperature during the operation of the FET and the GaAs substrate moves. This transition, together with the multiplication due to the ion collision phenomenon during the operation of the FET, causes a reduction in the output of the FET, which causes a problem of lowering the reliability of the FET.

Therefore, it is an object of the present invention to provide a semiconductor device capable of preventing the deterioration of reliability due to stress.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
A pair of finger-shaped gate electrodes that selectively cover the active region of one main surface of the semiconductor substrate, and finger-shaped source electrodes and finger-shaped drain electrodes that selectively cover the active regions with the finger-shaped gate electrodes interposed therebetween. A unit cell having a plurality of finger-shaped source electrodes and finger-shaped drain electrodes that are adjacent to each other in parallel and arranged in common, and the plurality of unit cells are finger-shaped sources of the unit cells adjacent to each other in parallel. A semiconductor device provided with a plated heat sink (PHS) formed on a back surface of the semiconductor substrate opposite to the one main surface, the semiconductor substrate being provided with a source electrode connection portion for connecting electrodes. Is separated for each unit cell.

In this case, the PHS can be connected to the source electrode connecting portion at the separating portion.

An insulating resin film may be provided to cover the finger-shaped gate electrode, the finger-shaped source electrode and the finger-shaped drain electrode.

Furthermore, the PHS can be separated for each unit cell.

Since the semiconductor substrate is separated for each unit cell, the curvature due to the difference in the coefficient of thermal expansion between the semiconductor substrate and the PHS is small.

[0016]

FIG. 1 is a plan view of an FET chip showing a first embodiment of the present invention, and FIG. 2 is a sectional view taken along line XX of FIG.

In this embodiment, a finger-like gate electrode Gf for selectively covering the active region 2 on one main surface of the GaAs substrate, and the active region 2 with the finger-like gate electrode Gf interposed therebetween.
Source electrodes Sf for selectively covering
And a unit cell 3 in which six sets of finger-like drain electrodes Df are arranged in parallel to share the adjacent finger-like source electrode Sf and finger-like drain electrode Df, and four unit cells 3 are arranged in parallel. A semiconductor comprising a source electrode connecting portion Sc for connecting finger-like source electrodes Sf of the unit cells adjacent to each other and provided with a PHS formed on the back surface of the GaAs substrate opposed to the one main surface. In the device, the GaAs substrate is separated for each unit cell 3. GaAs substrate is 3
It is separated into four portions 1-1, 1-2, 1-3, and 1-4 by the slits 7A-1, 7A-2, and 7A-3.

The gate electrode includes six finger-shaped gate electrodes Gf for each unit cell and a gate bar Gb connecting these finger electrodes.
And a gate pad Gp connected to the gate bar. The gate pad of each unit cell is connected to an external gate terminal of the package by a bonding wire (not shown). Similarly, the drain electrode includes three finger-like drain electrodes Df for each unit cell, a drain bar Db connecting these, and a drain pad Dp connecting to the drain bar. The drain pad of each unit cell is connected to an external drain terminal of the package by a bonding wire (not shown).

The source electrode has four finger-like source electrodes Sf for each unit cell (one or two of them also serve as a source electrode connecting part Sc together with the finger-like source electrodes of the adjacent unit cells). Source pads S
p and a source bar Sb.

The active region 2 is surrounded by an insulating region formed by an ion implantation method or the like. Some surfaces of the insulating region and the active region are covered with the SiO ₂ film 4. Finger-like source electrode Sf and finger-like drain region Df
Is a contact hole (not shown) provided in the SiO ₂ film 4 and is in contact with the active area.

The source electrode connection Sc is connected to the PHS 5A through a contact hole C provided in the SiO ₂ film.
The source pad Sp is connected to the PHS5 by the via hole 6.
A is connected.

Next, the manufacturing method of the present embodiment will be described.

FIGS. 3A to 3F are schematic sectional views arranged in the order of steps for explaining this manufacturing method.

As shown in FIG. 3A, the wafer-like G
After a gate electrode, a source electrode, a drain electrode, and the like are formed on the main surface of the aAs substrate 1a, a cover insulating film (not shown) is formed, and an opening is provided on each pad.
As shown in FIG. 3, the glass plate 8 is attached with wax 9. Next, as shown in FIG. 3C, the thickness is 30 to 50 μm.
The GaAs substrate 1b of m is polished. Next, the GaAs substrate 1b is etched by using a lithography technique, and as shown in FIG. 3 (d), slits 7A-1, 7A-2, 7A-3 having a width of about 100 μm are formed (FIG. 3 (d)). As a representative, only 7A-1 is shown.) Via holes and scribe grooves 10 are formed. Next, a Ti film and an Au film are respectively formed by a sputtering method to provide a power supply film for plating, and then, as shown in FIG. 3D, the scribe groove 10 is filled with a photoresist film 11 and then Au plating is performed. Then, PHS5A having a thickness of about 50 μm is formed. 3 μm × 1 by removing the photoresist film 11, milling the power supply film for plating in the scribe groove, and removing the wax 9.
The FET chip 12 having a squared angle of about μm is obtained. Reference numeral 13 denotes wastes obtained by the singulation process.

In this way, the FET chip can be divided into unit cells, but at the time of division, it is attached to the glass substrate in a wafer state, and after being divided into pieces, the source electrode, the cover film and the PHS are used. Being integrated, the distance between the unit cells hardly changes and does not have the above-mentioned drawbacks of the multi-chip device.

As shown in FIG. 4, the FET chip is fixed in a package 200 with solder 100, and the GaAs substrate 1 and P
The portion of the HS5A having the two-layer structure is curved due to the difference in the coefficient of thermal expansion as in the conventional example. However, since the GaAs substrate is divided, if the electrode layer on the surface (Sp, etc., thickness is around 1 μm) is thin and can be ignored in the portion without the GaAs substrate, a single-layer structure with only PHS is used, and such a heat No bending occurs due to the difference in expansion coefficient.

Further, since this portion does not have a GaAs substrate and has a low mechanical strength, it is in a direction opposite to that of the GaAs substrate due to a force for mechanically pressing down the chip or a surface tension due to molten solder. In addition, it bends with a very small radius of localization. That is, locally
Very large stress concentrates on HS. That is, stress concentration occurs in the PHS, and no stress concentration occurs in the GaAs substrate. Accordingly, the occurrence and growth of slip transition due to stress are suppressed, and a decrease in reliability is prevented.

FIG. 5 is a plan view of an FET chip for explaining the second embodiment of the present invention, and FIG. 6 is the X of FIG.
-It is an X-ray sectional view. The electrode pattern of the FET chip is the same as that of the first embodiment.

Here, the GaAs substrate is divided into four portions 1-1 to 1-4 by slits 7A-1 to 7A-3 on the boundaries of the unit cells by selective gold plating. Similarly, the PHS is divided into four parts 5-1 to 5-4. For this reason, an insulating resin film 14 such as polyimide is provided on the surface for reinforcing the strength.

An opening 15 for bonding is provided in the insulating resin film 14 and a cover film (not shown) thereunder. The FET chip is integrated with the source electrode, the cover film, and the insulating resin.

In the manufacturing method of the present embodiment, a gate electrode and the like are formed, an insulating resin film 14 is formed, an opening 15 is formed, and the resultant structure is pasted on a glass plate. To form PHS 5-1 to 5-4 and to form an Au film or the like in the opening,
Etching is performed using S5-1 to 5-4 as a mask to form slits 7A-1 to 7A-3 and scribe grooves, thereby performing individualization into FET chips.

As shown in FIG. 7, the FET chip is fixed in the package 200 with the solder 100 and is assembled.
The portion forming the layer structure is curved due to the difference in the coefficient of thermal expansion as in the conventional example. However, since the GaAs substrate and the PHS are divided, if the electrode layer (about 1 μm) on the surface is thin and negligible in a portion where the GaAs substrate and the PHS layer are not provided, the structure becomes only the insulating resin film 14, and such heat No curvature occurs due to the difference in expansion coefficients.

Further, since this portion does not have a GaAs substrate and PHS and has a low mechanical strength, it has a lower mechanical strength than a portion having a GaAs substrate due to a force for mechanically pressing down a chip or a surface tension due to molten solder. It bends in the opposite direction with a very small radius of curvature. That is, a very large stress is locally concentrated on the insulating resin film.
That is, stress concentration occurs in the insulating resin film, and the GaAs
No stress concentration occurs on the substrate. Accordingly, the occurrence and growth of slip transition due to stress are suppressed, and a decrease in reliability is prevented.

In the first embodiment, the source electrode and the PHS
In the case where PHS is formed at the same time as filling the via holes connecting the layers, if the gold plating layer is thickened or the filling property is improved by a method such as pulse plating, the PHS layer almost fills the divided portion of the GaAs substrate. At that time, the PHS layer is not necessarily weak in mechanical strength, and the stress may be dispersed to the GaAs side. However, in the second embodiment, such a problem does not occur because the GaAs substrate and the PHS are both divided.

The insulating resin film is not limited to polyimide, but may be an epoxy resin used as a sealing material for a resin-sealed semiconductor device.

In the present invention, the semiconductor substrate is not limited to a GaAs substrate, and a compound semiconductor such as InP can be used.

[0037]

As described above, according to the present invention, since the FET chip is separated for each unit cell, deformation of the semiconductor substrate and concentration of stress at the time of assembling can be avoided to prevent a decrease in the reliability of the FET. This has the effect.

[Brief description of drawings]

FIG. 1 is a plan view of an FET chip showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line XX of FIG.

FIGS. 3A to 3F are cross-sectional views for explaining a manufacturing method according to the first embodiment; FIGS.

FIG. 4 is a cross-sectional view for describing the first embodiment.

FIG. 5 is a plan view of an FET chip showing a second embodiment of the present invention.

FIG. 6 is a plan view taken along line XX of FIG. 5;

FIG. 7 is a cross-sectional view for explaining a second embodiment.

FIG. 8 is a plan view of an FET chip showing a first conventional example.

FIG. 9 is a sectional view taken along line XX of FIG. 8;

FIG. 10 is a cross-sectional view for explaining a first conventional example.

FIG. 11 is a plan view of an FET chip showing a second conventional example.

12 is a cross-sectional view taken along line XX of FIG.

FIG. 13 is a cross-sectional view for describing a second conventional example.

[Explanation of symbols]

1,1a, 1b, 1-1,1-2,1-3,1-4
GaAs substrate 2 Active area 3 Unit cell 4 SiO ₂ film 5,5A, 5-1,5-2,5-3,5-4 PHS
(Plated heat sink) 6 Via hole 7-1, 7A-1, 7-2, 7A-2, 7-3, 7A-
3 Slit 8 Glass Substrate 9 Wax 10 Scribe Groove 11 Photoresist Film 12 FET Chip 13 Scrap 14 Insulating Resin Film 15 Opening 100 Solder 200 Package C Opening Db Drain Bar Df Finger-like Drain Electrode Dp Drain Pad Gb Gate Bar Gf Finger-like Gate Electrode Gp gate pad Sb source bar Sc source electrode connecting portion Sf finger-shaped source electrode Sp source pad

Claims (5)

[Claims] 1. A finger-shaped gate electrode for selectively covering an active region of a main surface of a semiconductor substrate, a finger-shaped source electrode and a finger for selectively covering the active region with the finger-shaped gate electrode interposed therebetween. A unit cell in which a plurality of pairs of drain electrodes are arranged in parallel so as to share the finger source electrode and the finger drain electrode, and the plurality of unit cells are adjacent to each other in parallel. A semiconductor device provided with a plated heat sink formed on a back surface of the semiconductor substrate, the back surface facing the one main surface of the semiconductor substrate, wherein the plated heat sink is provided. A semiconductor device, wherein a semiconductor substrate is separated for each unit cell. 2. The semiconductor device according to claim 1, wherein the plated heat sink is connected to the source electrode connecting portion at the separation portion. 3. The semiconductor device according to claim 1, wherein an insulating resin film is provided to cover the finger-shaped gate electrode, the finger-shaped source electrode and the finger-shaped drain electrode. 4. The semiconductor device according to claim 3, wherein the plated heat sink is separated for each unit cell. 5. The semiconductor device according to claim 1, wherein the semiconductor substrate is a GaAs substrate.