JPH0946207A - Semiconductor memory device - Google Patents

Abstract

(57) Abstract: Power consumption of an input buffer circuit of a semiconductor memory device is reduced. An input buffer circuit 11 and an output buffer circuit 2 are connected to an input / output pad 1, and an output buffer circuit 2 is provided.
Outputs the output data Dout to the input / output pad 1 based on the activation signal OE output from the control circuit 3, and the input buffer circuit 11 outputs the input data Din input to the input / output pad 1 to the internal circuit 5. To do. Input buffer circuit 11
Is the activation signal OE input to the output buffer circuit 2.
Is input and the input buffer circuit 11 is inactivated when the output buffer circuit 2 is activated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer circuit for inputting write data to a semiconductor memory device.

In recent years, semiconductor memory devices have become more highly integrated and have a larger capacity, and the power supply has been reduced in voltage and power consumption. In addition, as the storage capacity increases, the number of input / output bits increases, and along with this, the number of input / output pins and the number of input buffer circuits connected to the input / output pins also tends to increase. . Therefore, it is necessary to reduce the power consumption of each input buffer circuit.

[0003]

2. Description of the Related Art FIG. 5 shows a structure of a buffer circuit connected to an input / output pad of a conventional synchronous DRAM.

The output buffer circuit 2 connected to the input / output pad 1 is activated based on the output control signal OE output from the output control circuit 3 in the read mode of the semiconductor memory device, and is read from the selected memory cell. The read data RD that is output is used as the output data Dout, and the input / output pad 1
Output to

The input buffer circuit 4 connected to the input / output pad 1 outputs the input data Din externally input to the input / output pad 1 to the write amplifier 5 as write data WD. Then, the write data WD amplified by the write amplifier 5 is written in the selected memory cell.

A power down signal EN is input to the input buffer circuit 4 in the power down mode of the synchronous DRAM, and it is deactivated based on the input of the power down signal EN.

A concrete structure of the input buffer circuit 4 is shown in FIG. The input data Din is input to the gate of the N-channel MOS transistor Tr1 and is supplied to the transistor Tr1.
Is connected to the power source Vcc through the P-channel MOS transistor Tr2.

The reference voltage Vref is input to the gate of the N-channel MOS transistor Tr3, and the same transistor Tr3 is supplied.
Has a drain connected to the power supply Vcc through the P-channel MOS transistor Tr4. The reference voltage Vref is 1 /
It is 2 Vcc.

The sources of the transistors Tr1 and Tr3 are
It is connected to the drain of the N-channel MOS transistor Tr5, the source of the transistor Tr5 is connected to the power supply Vss, and the power down signal EN is input to the gate.

A P channel MO is provided to the transistor Tr2.
The S transistor Tr6 is connected in parallel, and the power down signal EN is input to the gate of the transistor Tr6. A P-channel MOS transistor Tr7 is connected in parallel to the transistor Tr4, and the power down signal EN is input to the gate of the transistor Tr7.

The drain of the transistor Tr4 is connected to the gate of the transistor Tr4 via an N-channel MOS transistor Tr8. The transistor Tr8
Has its gate connected to the power supply Vcc and is always turned on.

Therefore, the transistors Tr1 to Tr5 and Tr8 form a current mirror circuit. Such a current mirror type input buffer circuit consumes a large amount of power, but has a feature that it operates at high speed and stably with respect to an input signal of a small amplitude.
Often used in.

The drain of the transistor Tr1 is connected to the input terminal of a three-stage inverter circuit 6 connected in series, and the inverter circuit 6 outputs write data WD.

The input buffer circuit 4 thus configured
Then, when the power down signal EN becomes L level in the power down mode, the transistor Tr5 is turned off and the transistors Tr6 and Tr7 are turned on.

Then, the drain potentials of the transistors Tr1 and Tr3 both become H level regardless of the input data Din, and the write data WD is fixed at L level. Therefore, the input buffer circuit 4 becomes inactive.

On the other hand, in the write mode, read mode and standby mode other than the power down mode,
When the power down signal EN becomes H level, the transistor Tr5 is turned on and the transistors Tr6 and Tr7 are also turned on.
Is turned off.

Then, when the input data Din becomes lower than the reference voltage Vref due to the operation of the current mirror circuit,
The drain potential of the transistor Tr1 rises and the write data WD becomes L level.

When the input data Din becomes higher than the reference voltage Vref, the drain potential of the transistor Tr1 lowers and the write data WD becomes H level. Note that unnecessary writing is not performed even when the write amplifier 5 is deactivated and the output signal WD is output from the input buffer circuit 4 except in the write mode.

[0019]

The input buffer circuit 4 as described above is activated based on the H-level power down signal EN except in the power down mode.
As shown in FIG. 7, in the standby mode, when the output data Dout of the output buffer circuit 2 is in the high impedance state, the output signal WD becomes H level or L level.

From this state, the mode is changed to the read mode, the output control signal OE becomes L level, the output buffer circuit 2 is activated, and, for example, when the output data Dout becomes H level, the input signal of the input buffer circuit 4 is inputted. Din also becomes H level. Then, the input buffer circuit 4 outputs the H-level output signal WD.

When the output data Dout becomes L level, the input signal Din of the input buffer circuit 4 also becomes L level. Then, the input buffer circuit 4 outputs the L-level output signal WD.

Therefore, the output signal W of the input buffer circuit 4
Even in the write mode that does not require D, the input buffer circuit 4 operates based on the output data Dout output from the output buffer circuit 2 and consumes power.

In particular, in a semiconductor memory device having a large number of input / output bits, the input buffer circuit provided for each of a large number of input / output pads operates as described above, resulting in an increase in power consumption. There is a point.

An object of the present invention is to reduce the power consumption of the input buffer circuit of the semiconductor memory device.

[0025]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the input buffer circuit 11 and the output buffer circuit 2 are connected to the input / output pad 1, and the output buffer circuit 2 outputs the output data Dout to the input / output pad 1 based on the activation signal OE output from the control circuit 3.
The input buffer circuit 11 outputs the input data Din input to the input / output pad 1 to the internal circuit 5. The activation signal OE input to the output buffer circuit 2 is input to the input buffer circuit 11, and the input buffer circuit 11 is deactivated when the output buffer circuit 2 is activated.

In claim 2, the input buffer circuit is
It is composed of a current mirror circuit, and when the activation signal is input, the current mirror circuit is inactivated.
In the present invention, the input buffer circuit is inactivated when at least one of the power down signal and the activation signal is input.

(Operation) In the first aspect, when the output data is output from the output buffer circuit to the input / output pad, the input buffer circuit is inactivated.

According to the present invention, when the output data is output from the output buffer circuit to the input / output pad, the input buffer circuit composed of the current mirror circuit is inactivated. According to the third aspect, when the output data is output from the output buffer circuit to the input / output pad or when the power down signal is input, the input buffer circuit is inactivated.

[0029]

FIG. 2 shows the structure of a buffer circuit according to an embodiment of the present invention. The input / output pad 1, the output buffer circuit 2, the output control circuit 3, and the write amplifier 5 have the same configuration as the conventional example.

The input buffer circuit 11 outputs the output control signal O
E and the input data Din are input, and the output signal WD is output to the write amplifier 5. A specific configuration of the input buffer circuit 11 is shown in FIG. This input buffer circuit 11 is
The conventional input buffer circuit includes a transfer gate 12, an inverter circuit 13, and an N-channel MOS transistor Tr9.
Will be added, and the same components as those of the conventional example will be described with the same reference numerals.

The power down signal EN is transferred to the transfer gate 12
Is input to the gates of the transistors Tr5, Tr6, Tr7 via. The output control signal OE is input to the N-channel side gate of the transfer gate 12, and the output control signal OE is inverted by the inverter circuit 13 and input to the P-channel side gate.

The gates of the transistors Tr5, Tr6, Tr7 are connected to the power supply Vss via the transistor Tr9, and the output signal of the inverter circuit 13 is input to the gate of the transistor Tr9.

The input buffer circuit 1 thus configured
In No. 1, in the write mode, since the H level output control signal OE is input, the transfer gate is turned on and the transistor Tr9 is turned off. Therefore, the configuration is substantially the same as that of the conventional example, and the same operation is performed.

When the L level output control signal OE is input in the read mode, the transfer gate 12 is turned off and the transistor Tr9 is turned on. Then, the transistor T
As r5 is turned off and the transistors Tr6 and Tr7 are turned on, as shown in FIG. 4, the output signal WD of the input buffer circuit 11 is fixed to the L level regardless of the input data Din and the power down signal EN. It

Therefore, in the read mode, the input buffer circuit 11 is inactivated regardless of the power down signal EN, and power consumption based on the output data Dout can be prevented.

Particularly, in a semiconductor memory device having a multi-bit structure in which a large number of such input buffer circuits are used, the effect of reducing power consumption is great. The technical ideas other than the claims that can be understood from the above embodiments will be described below along with their effects. (1) An input buffer circuit and an output buffer circuit are respectively connected to a large number of input / output pads, and each output buffer circuit outputs output data to each input / output pad based on an activation signal output from a control circuit. Each of the input buffer circuits is a semiconductor memory device that outputs input data input to each input / output pad to an internal circuit, and each input buffer circuit has an active input to each output buffer circuit. When the output buffer circuits are activated by inputting the activation signal, the input buffer circuits are inactivated.
It is possible to reduce power consumption in a semiconductor memory device having a multi-bit configuration in which many input buffer circuits are used.

[0037]

As described above in detail, the present invention can reduce the power consumption of the input buffer circuit of the semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing an embodiment.

FIG. 3 is a circuit diagram showing an input buffer circuit according to an embodiment.

FIG. 4 is a waveform chart showing the operation of the embodiment.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a circuit diagram showing a conventional input buffer circuit.

FIG. 7 is a waveform chart showing the operation of the conventional example.

[Explanation of symbols]

 1 Input / Output Pad 2 Output Buffer Circuit 3 Control Circuit 5 Internal Circuit 11 Input Buffer Circuit OE Activation Signal Dout Output Data Din Input Data

Claims (3)

[Claims] 1. An input buffer circuit and an output buffer circuit are connected to an input / output pad, and the output buffer circuit outputs output data to the input / output pad based on an activation signal output from a control circuit, The input buffer circuit is a semiconductor memory device that outputs input data input to an input / output pad to an internal circuit, and the input buffer circuit inputs an activation signal input to the output buffer circuit, A semiconductor memory device, wherein the input buffer circuit is inactivated when the output buffer circuit is activated. 2. The semiconductor memory device according to claim 1, wherein the input buffer circuit is composed of a current mirror circuit, and deactivates the current mirror circuit when the activation signal is input. . 3. The semiconductor memory device according to claim 1, wherein the input buffer circuit is inactivated when at least one of a power down signal and the activation signal is input.