JPH0946229A - Clock phase detector - Google Patents

Abstract

(57) [Abstract] [Purpose] To detect the phase shift between the data and the sampling clock when A / D converting the reproduced signal or the received signal. [Structure] A waveform equalizer 102 converts an input analog signal
To convert it to an equalized signal. This signal is given to the A / D converter 104 and converted into digital data. This digital data is input to the provisional determiner 105, and the value of the input data is provisionally determined to be one of three values. And the pattern extractor 106
Detects whether or not a specific pattern has been input, based on this signal. When this pattern is detected, the phase shift direction predictor 107 checks the amplitude difference between the current signal and the delayed signal, and predicts the phase shift from the positive or negative of the value. The detection result here is given to the phase shift detector 108 to perform cumulative addition. The phase shift of the clock is detected from this added value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to analog signals
The present invention relates to a clock phase detection device that detects a phase shift between an input analog signal and a sampling clock when performing D / D conversion.

[0002]

2. Description of the Related Art An analog signal (input signal) reproduced or received by a digital signal reproducing device or a digital signal receiving device.
Is decoded to digital binary data, it is possible to use bit-by-bit decoding by amplitude discrimination of the analog signal, or to maximize the time-series information contained in the analog signal. Viterbi decoding, which is a type of In particular, by using Viterbi decoding, a better error rate can be obtained than with a bit-by-bit decoding method.

Since Viterbi decoding is usually performed by digital signal processing, it is necessary to A / D convert the reproduced or received analog signal. When performing A / D conversion, it is desirable that the phase of the clock for sampling the input signal is at the optimum point. If the clock phase deviates from the optimum point, the error rate after decoding will deteriorate significantly. This tendency is particularly remarkable in the case of Viterbi decoding. This does not make sense to introduce Viterbi decoding in order to improve the error rate.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and extracts a specific pattern from the phase shift between the input analog signal and the sampling clock. Therefore, it is an object of the present invention to realize a clock phase detection device that can reliably detect and output information that can accurately correct the phase shift.

[0005]

The invention according to claim 1 of the present application is a clock phase detecting apparatus for detecting a phase shift of a sampling clock when an input analog signal is converted into a digital signal by an A / D converter. Then, the provisional determination unit that provisionally determines the output signal of the A / D converter to be a discrete value by the set threshold value, and the provisional determination result of the provisional determination unit extracts an array of specific discrete values as a specific pattern. Pattern extraction means, and when a specific pattern is extracted from the pattern extraction means, among the output signals of the A / D converter,
Phase shift direction predicting means for comparing the amplitudes of the respective clocks and numerically predicting the shift direction of the clock phase and the shift direction numerical values predicted by the phase shift direction predicting means are cumulatively added and subtracted, and the cumulative value is When the specified value is reached,
And a phase shift detection means for generating a clock phase shift detection signal.

According to a second aspect of the present invention, there is provided a clock phase detecting device for detecting a phase shift of a sampling clock when an analog input signal is converted into a digital signal by an A / D converter. A tentative determination means for tentatively determining the output signal of the converter to a discrete value by a set threshold value; a pattern extraction means for extracting an array of specific discrete values from the tentative determination result of the tentative determination means as a specific pattern; When a specific pattern is extracted from the pattern extraction means, phase shift direction prediction means for comparing the amplitudes of respective clocks in the output signal of the A / D converter and numerically predicting the clock phase shift direction And a phase shift direction accumulating means for cumulatively adding and subtracting a numerical value in the shift direction predicted by the phase shift direction predicting means, and a cumulative value of the phase shift direction accumulating means reaches a specified value. When the, is characterized in that it comprises a phase shift detection signal generating means for generating a clock phase shift detection signal.

According to a third aspect of the present invention, there is provided a clock phase detection device for detecting a phase shift of a sampling clock when an input analog signal is converted into a digital signal by an A / D converter. A tentative determination means for tentatively determining the output signal of the converter to a discrete value by a set threshold value; a pattern extraction means for extracting an array of specific discrete values from the tentative determination result of the tentative determination means as a specific pattern; When a specific pattern is extracted from the pattern extraction means, phase shift direction prediction means for comparing the amplitudes of respective clocks in the output signal of the A / D converter and numerically predicting the clock phase shift direction Based on the sign of the accumulated value of the phase deviation direction accumulating means, and the phase deviation direction accumulating means for accumulating and subtracting the numerical value of the deviation direction predicted by the phase deviation direction predicting means. And it is characterized by comprising: a phase shift detection signal generating means for generating a clock phase shift detection signal at a constant period.

According to a fourth aspect of the present invention, there is provided a clock phase detecting device for detecting a phase shift of a sampling clock when an input analog signal is converted into a digital signal by an A / D converter. A tentative determination means for tentatively determining the output signal of the converter to a discrete value by a set threshold value; a pattern extraction means for extracting an array of specific discrete values from the tentative determination result of the tentative determination means as a specific pattern; When a specific pattern is extracted from the pattern extraction means, phase shift direction prediction means for comparing the amplitudes of respective clocks in the output signal of the A / D converter and numerically predicting the clock phase shift direction And a phase shift direction accumulating means for cumulatively adding and subtracting a numerical value of the shift direction predicted by the phase shift direction predicting means, and a cumulative value of the phase shift direction accumulating means. It is characterized in that it comprises a phase error detection signal generating means for generating a clock phase shift detection signal in a cycle.

According to a fifth aspect of the present invention, there is provided a clock phase detecting device for detecting a phase shift of a sampling clock when an input analog signal is converted into a digital signal by an A / D converter. A tentative determination means for tentatively determining the output signal of the converter to a discrete value by a set threshold value; a pattern extraction means for extracting an array of specific discrete values from the tentative determination result of the tentative determination means as a specific pattern; When the specific pattern is extracted from the pattern extracting means, the phase shift direction and phase for predicting the clock phase shift direction and the shift amount by comparing the amplitudes of the respective clocks in the output signal of the A / D converter Shift amount predicting means, phase shift amount accumulating means for cumulatively adding and subtracting the phase shift predicted amount obtained by the phase shift direction and phase shift amount predicting means, and the phase shift amount accumulating When the accumulated value of the stage reaches a prescribed value,
And a phase shift detection signal generating means for generating a clock phase shift detection signal.

According to a sixth aspect of the present invention, there is provided a clock phase detecting device for detecting a phase shift of a sampling clock when an analog input signal is converted into a digital signal by an A / D converter. A tentative determination means for tentatively determining the output signal of the converter to a discrete value by a set threshold value; a pattern extraction means for extracting an array of specific discrete values from the tentative determination result of the tentative determination means as a specific pattern; When the specific pattern is extracted from the pattern extracting means, the phase shift direction and phase for predicting the clock phase shift direction and the shift amount by comparing the amplitudes of the respective clocks in the output signal of the A / D converter Shift amount predicting means, phase shift amount accumulating means for cumulatively adding and subtracting the phase shift predicted amount obtained by the phase shift direction and phase shift amount predicting means, and the phase shift amount accumulating Based on the sign of the stages of the cumulative value, it is characterized in that it comprises a phase error detection signal generating means for generating a clock phase shift detection signal at a constant period.

According to a seventh aspect of the present invention, there is provided a clock phase detecting device for detecting a phase shift of a sampling clock when an analog input signal is converted into a digital signal by an A / D converter. A tentative determination means for tentatively determining the output signal of the converter to a discrete value by a set threshold value; a pattern extraction means for extracting an array of specific discrete values from the tentative determination result of the tentative determination means as a specific pattern; When the specific pattern is extracted from the pattern extracting means, the phase shift direction and phase for predicting the clock phase shift direction and the shift amount by comparing the amplitudes of the respective clocks in the output signal of the A / D converter Shift amount predicting means, phase shift amount accumulating means for cumulatively adding and subtracting the phase shift predicted amount obtained by the phase shift direction and phase shift amount predicting means, and the phase shift amount accumulating Based on the cumulative value of the stage and is characterized by comprising: a phase shift detection signal generating means for generating a clock phase shift detection signal at a constant period.

FIG. 1 is a block diagram showing the concept of the clock phase detecting device of the present invention. In FIG. 1, an analog signal reproduced from a recording medium or an analog signal transmitted from a transmission unit is input via a reproduction signal input terminal 101. These input signals are equalized into a predetermined waveform by the waveform equalizer 102. This equalized signal is input to the PLL 103, and a clock synchronized with the equalized signal is generated. The equalized signal of the waveform equalizer 102 is also input to the A / D converter 104, sampled by the clock generated by the PLL 103, and converted into digital data.

This digital data is input to the temporary discriminator 105 and discriminated as one of the three values {-1, 0, 1}. The three-valued signal is input to the pattern extractor 106, where a pattern (specific pattern) convenient for detecting the clock phase shift is extracted. Then, the pattern extractor 106 sends the information to the phase shift direction predictor 107 when the specific pattern is extracted.

The specific pattern extracted by the pattern extractor 106 is, for example, (1,1) or (-1, -1). The phase shift direction predictor 107 is the pattern extractor 1
When the pattern extraction is performed in 06, the direction of the phase shift of the clock is predicted based on the digital data from the A / D converter 104 corresponding to the specific pattern. The direction predicted here is sent to the phase shift detector 108 to detect the clock phase shift.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION A clock phase detecting apparatus in a first embodiment for realizing such a method will be described with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the clock phase detecting device of the first embodiment. In the figure, an input signal is applied to a waveform equalizer 202 via a reproduction signal input terminal 201. The signal equalized by the waveform equalizer 202 is given to the PLL 203 and the A / D converter 204 as in the case of FIG.

A ternary discriminator 205 and a threshold value setter 206 are provided as the temporary discriminator 105 of FIG. When the three-value discriminator 205 is provided with digital data from the A / D converter 204, the value of the data is 3 of {-1, 0, 1}
This is a circuit that determines which of the values the data belongs to. The threshold value setter 206 is a circuit that sets a threshold value for discrimination in the ternary discriminator 205.

The pattern discriminator 207 is a ternary discriminator 205.
Is a circuit for determining the input of a specific pattern by taking in the output value of (1) over a plurality of sampling periods. FIG. 3 shows the pattern discriminator 2 connected to the ternary discriminator 301 (205).
It is a block diagram which shows the structural example of 07. As shown in the figure, the pattern discriminator 207 includes a D flip-flop (D.
FF) 302, D / FF 303, EX / NOR circuit 30
4, a logical product (AND) circuit 305, an AND 306, and the like.

The absolute value calculator 208 and the D / FF 20 shown in FIG.
9, the comparator 210 is the phase shift direction predictor 107 of FIG.
(Phase shift direction prediction means). The absolute value calculator 208 is a circuit for converting the output data of the A / D converter 204 into an absolute value. The D / FF 209 is an absolute value calculator 208.
Is a flip-flop which delays one clock cycle by latching this signal as the current signal n.
The output of the D / FF 209 is given to the comparator 210 as the delayed signal m together with the current signal n. When the pattern discriminator 207 detects a specific pattern, the comparator 210 compares the amplitudes of the current signal n and the delayed signal m, and when m> n, 1
Is output, and -1 is output when m <n.

The cumulative adder 211, the comparator 212, the bias threshold setting device 213, and the cumulative adder 214 constitute the phase shift detector 108 (phase shift detection means) in FIG. The cumulative adder 211 is a phase shift direction cumulative means that cumulatively adds the outputs of the comparator 210 based on the control signal of the comparator 212. The cumulative value of the cumulative adder 211 is sequentially calculated by the comparator 21.
2 given. The comparator 212 is a circuit that compares the absolute value of the cumulative value with the bias threshold set by the bias threshold setting unit 213, and outputs 1 or -1 based on the sign of the cumulative value when the comparison results match. Circuit. Cumulative adder 2
Reference numeral 14 is a phase shift detection signal generating means for cumulatively adding input values and generating an output signal whose value changes according to the delay or advance of the clock.

The operation of the clock phase detecting apparatus of the first embodiment thus constructed will be described. The analog signal input to the reproduction signal input terminal 201 of FIG. 2 is shaped into a predetermined waveform by the waveform equalizer 202. This equalized signal is input to the PLL 203, and a clock synchronized with the equalized signal is generated. The equalized signal is also input to the A / D converter 204, sampled by the clock generated by the PLL 203, and converted into digital data.

The digital data output from the A / D converter 204 is input to the ternary discriminator 205, and the threshold value setter 2
Based on the threshold of 06, the input value is {-1, 0, 1} 3
Judge as one of the values. For example, assuming that the threshold value is a, the input value is b, and the output value is c, when b ≦ −a, c = −1,
When -a <b <a, it is determined that c = 0, and when a ≦ b, it is determined that c = 1.

The pattern discriminator 207 discriminates a predetermined specific pattern from several continuous three-valued data. For example, a pattern of (1, 1) or (-1, -1) is defined as the specific pattern. As shown in FIG.
The case where the pattern of (1, 1) or (-1, -1) is discriminated is shown.

It is discriminated by the ternary discriminator 301 in FIG. 3 and 2-bit data corresponding to the ternary value is output. When the input value is represented by [output upper bit x, output lower bit y],
For example, -1 becomes [1,1], 0 becomes [0,0], and 1 becomes [0,1]. When 1 or -1 is continuous, 1 is continuous in the low-order bits y, 0 is continuous when the high-order bits x is 1, and 1 is continuous when the high-order bits x are -1. In other words, AN that inputs the lower two consecutive bits
The D circuit 305 detects that two consecutive data are non-zero. In the EX / NOR circuit 304, consecutive 2 data is -1
It is detected that it is continuous or non-continuous. Therefore, the AND circuit 306 detects the continuation of 1 or the continuation of -1. In this way, (1,1), (-1, -1,)
Pattern can be identified.

The output data of the A / D converter 204 is also input to the absolute value calculator 208, and the absolute value thereof is calculated. This absolute value is delayed by one clock in the D / FF 209 to become a delayed signal m, and the comparator 210 together with the current signal n.
Is input to The comparator 210 has a delay signal m and a current signal n.
Compare the amplitudes of. This comparison is made by the pattern discriminator 207.
Is executed only when a pattern of (1, 1) or (-1, -1) is discriminated. That is, which of the absolute values of the original two data determined to be the pattern of (1, 1) or (-1, -1) is larger is compared.

FIG. 4 is a waveform diagram showing the relationship between the output signal of the waveform equalizer 202 and the sampling clock. Here, the timing of the sampling clock is shown by vertical lines. Also, the waveforms in this figure are (1,
1) or a pattern (m, n) that yields (-1, -1)
Is shown. If the absolute value of two data is (m, n), this figure shows the case of m> n, and it can be said that the phase of the clock is advanced.

The comparison result of the comparator 210 is the cumulative adder 21.
1 is added, and when m> n (clock advance), 1 is added, and when m <n (clock advance), -1 is added. Note that the cumulative value of the cumulative adder 211 is reset to 0 when the power is turned on or when the reproduction is started. The cumulative value of the cumulative adder 211 is sequentially sent to the comparator 212,
Bias threshold value setter 21 whose absolute value is preset
The threshold value from 3 is compared, and if they match, the cumulative adder 214 performs addition based on the sign of the cumulative value. In this case, the added value is 1 when the cumulative value is positive and -1 when the cumulative value is negative. At the same time, the cumulative value of the cumulative adder 211 is reset to 0.

In this way, the cumulative value of the cumulative adder 214 becomes smaller when the clock is delayed and becomes larger when the clock is advanced. Further, the cumulative speed becomes faster as the shift amount becomes larger. This accumulated value becomes the clock phase shift detection signal.

In this embodiment, the pattern to be discriminated by the pattern discriminator 207 is (1, 1) or (-
1, -1), but other patterns are possible. For example, (0,1,1,0) or (0, -1, -1, -1,
0), (-1,1,1, -1) or (1, -1, -1,)
1) and so on.

Next, a clock phase detecting device according to the second embodiment will be described with reference to the drawings. FIG. 5 is a block diagram showing the configuration of the clock phase detecting apparatus of the second embodiment. The same parts as those in the first embodiment are given the same names and their explanations are omitted. As shown in the figure, in the clock phase detecting device of the first embodiment, a reproduction signal input terminal 501, a waveform equalizer 502, a PLL 503, an A / D converter 504,
A three-value discriminator 505, a threshold value setter 506, a pattern discriminator 507, an absolute value calculator 508, a D / FF 509, and a comparator 510 are provided.

The counter 512 is a circuit which receives a clock generated by the PLL 503 and counts this clock to generate a reset pulse in a cycle M. The cumulative adder 511 cumulatively adds the outputs of the comparator 510, and the cycle M
The phase shift direction accumulating means resets the accumulated value to 0. The cumulative adder 513 is a phase shift detection signal generating means for cumulatively adding the output of the cumulative adder 511.

The operation of the clock phase detecting device configured as described above will be described. Note that the blocks 501 to 510 are the same as the operation of the first embodiment, so the description of those operations will be omitted.

The comparison result of the comparator 510 is the cumulative adder 51.
1 is added when m> n (clock advance), and -1 is added when m <n (clock delay). The cumulative adder 511 is reset to 0 when the power is turned on or when reproduction is started. The counter 512 is PLL5
03 clocks are counted, and a predetermined cycle M
Then, a reset pulse is output to the cumulative adder 511. When this reset pulse is input, the cumulative adder 511 outputs the sign information of the cumulative value at that time to the cumulative adder 513 and resets its own cumulative value to 0. The cumulative adder 513 adds 1 to the cumulative value when the sent sign is positive, and adds -1 to the cumulative value when the sign is negative.

In this way, the cumulative value of the cumulative adder 513 becomes small when the clock is delayed and becomes large when the clock is advanced. The cumulative speed is
The larger the amount of phase shift, the faster the speed.

Next, the clock phase detecting device in the third embodiment will be explained. Since the configuration of the third embodiment is almost the same as that shown in FIG. 5, the block diagram is omitted.
Description will be given with reference to FIG. The operations of 501 to 510 and 512 in FIG. 5 are the same as those of the second embodiment, so the description thereof will be omitted. The cumulative addition method of the cumulative adder 511 is also the same as in the second embodiment.

When the cumulative adder 511 receives the reset pulse from the counter 512, the cumulative value at that time is sent to the cumulative adder 513, and the original cumulative value is reset to 0. The cumulative adder 513 cumulatively adds the values.

In this way, the cumulative value of the cumulative adder 513 becomes small when the clock is delayed and becomes large when the clock is advanced. The cumulative speed is
The larger the amount of phase shift, the faster the speed.

Next, a clock phase detecting device in the fourth embodiment will be described with reference to the drawings. FIG. 6 is a block diagram showing the configuration of the clock phase detecting device of the fourth embodiment. The same parts as those in the first to third embodiments are given the same names,
Their description is omitted. As shown in the figure, in the clock phase detecting apparatus of the fourth embodiment, a reproduction signal input terminal 60
1, waveform equalizer 602, PLL 603, A / D converter 6
04, a three-value discriminator 605, a threshold value setter 606, a pattern discriminator 607, an absolute value calculator 608, and a D / FF 609 are provided.

The subtractor 610 subtracts the current signal n output from the absolute value calculator 608 from the delay signal m output from the D / FF 609, and outputs the value to the cumulative adder 611. It is a predictor. Comparator 61
2, a bias threshold setting unit 613 and a cumulative adder 614 are further provided as in the first embodiment shown in FIG.

Regarding the operation of the clock phase detecting apparatus of the fourth embodiment thus constructed, only the parts different from those of the previous embodiments will be explained. The output of the absolute value calculator 608 is delayed by one clock in the D / FF 609 and input to the subtractor 610 as the delay signal m. Subtractor 610
Subtracts the current signal n from the delayed signal m. This subtraction is executed only when the pattern discriminator 607 discriminates a specific pattern.

The subtraction result of the subtractor 610 is sent to a cumulative adder 611 as a phase shift amount accumulating means, and cumulative addition is performed. The cumulative value of the cumulative adder 611 is reset to 0 when the power is turned on or when the reproduction is started. The cumulative value of the cumulative adder 611 is sequentially sent to the comparator 612. The comparator 612 compares the absolute value with a preset threshold value of the bias threshold value setting unit 613, and when the absolute value is larger than the threshold value, outputs the cumulative value to the cumulative adder 614 based on the sign of the cumulative value. In that case, the added value is 1 when the cumulative value is positive and − when the cumulative value is negative.
It becomes 1. At the same time, the cumulative value of the cumulative adder 611 is reset to 0.

In this way, the cumulative value of the cumulative adder 614 as the phase shift detection signal generating means becomes small when the clock is delayed and becomes large when the clock is advanced. Further, the cumulative speed becomes faster as the amount of phase shift becomes larger.

Next, a clock phase detecting device in the fifth embodiment will be described with reference to the drawings. FIG. 7 is a block diagram showing the configuration of the clock phase detecting apparatus of the fifth embodiment. The same parts as those in the fourth embodiment are given the same names and their explanations are omitted. As shown in the figure, the clock phase detection apparatus of the fifth embodiment includes a reproduction signal input terminal 701, a waveform equalizer 702, a PLL 703, an A / D converter 704,
As in the fourth embodiment, a three-value discriminator 705, a threshold value setter 706, a pattern discriminator 707, an absolute value calculator 708, a D / FF 709, and a subtractor 710 are provided. Further, a cumulative adder 711, a counter 712, and a cumulative adder 713 are provided as in the second embodiment shown in FIG.

The operation of the clock phase detecting apparatus of the fifth embodiment thus constructed will be described. Since the blocks 701 to 710 in FIG. 7 are the same as the operation of the fourth embodiment, the description of those operations will be omitted. The subtraction result of the subtractor 710 as the phase shift direction and phase shift amount predicting means is sent to the cumulative adder 711 to be cumulatively added. The cumulative value of the cumulative adder 711 as the phase shift amount cumulative means is reset to 0 when the power is turned on or when the reproduction is started.

The counter 712 counts the clock of the PLL 703, and the cumulative adder 7 counts at a predetermined cycle.
A reset pulse is output to 11. Upon receiving the reset pulse, the cumulative adder 711 sends the sign information of the cumulative value at that time to the cumulative adder 713 and resets its own cumulative value to 0. The cumulative adder 713 cumulatively adds 1 when the sent sign is positive and adds -1 when the sign is negative, and outputs it.

In this way, the cumulative value of the cumulative adder 713 as the phase shift detection signal generating means becomes small when the clock is delayed and becomes large when the clock is advanced. Further, the cumulative speed becomes faster as the amount of phase shift increases.

Next, the clock phase detecting device in the sixth embodiment will be explained. Since the configuration of the sixth embodiment is almost the same as that shown in FIG. 7, the block diagram is omitted.
Description will be given based on FIG. 7. The operations of 701 to 710 and 712 in FIG. 7 are the same as those of the fifth embodiment, so the description thereof will be omitted. The cumulative addition method of the cumulative adder 711 is also the same as in the fifth embodiment.

When the reset pulse is input from the counter 712, the cumulative adder 711 sends the cumulative value at that time to the cumulative adder 713 and resets the cumulative value to 0. The cumulative adder 713 cumulatively adds the values and outputs it.

In this way, the cumulative value of the cumulative adder 713 becomes small when the clock is delayed and becomes large when the clock is advanced. The cumulative speed is
The larger the amount of phase shift, the faster the speed.

When each of the above embodiments is constructed as an actual circuit, it is necessary to arrange a D flip-flop or the like in each section so that the signal timing is adjusted.

[0050]

As described above, according to the present invention, it is possible to reliably detect the phase shift of the sampling clock with respect to the input analog signal. If the phase shift of the sampling clock is corrected using this detection signal, when the signal after waveform equalization is decoded using the Viterbi code,
A signal with a significantly reduced error rate is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the concept of a clock phase detection device of the present invention.

FIG. 2 is a block diagram showing a configuration of a clock phase detection device of the first embodiment.

FIG. 3 is a block diagram showing a configuration example of a pattern discriminator used in the clock phase detection device of each embodiment.

FIG. 4 is a waveform diagram showing a phase shift between an input waveform and a sampling clock.

FIG. 5 is a block diagram showing a configuration of a clock phase detecting device according to second and third embodiments.

FIG. 6 is a block diagram showing a configuration of a clock phase detection device of a fourth embodiment.

FIG. 7 is a block diagram showing a configuration of a clock phase detection device of fifth and sixth embodiments.

[Explanation of symbols]

101, 201, 501, 601, 701 Reproduction signal input terminal 102, 202, 502, 602, 702 Waveform equalizer 103, 203, 503, 603, 703 PLL 104, 204, 504, 604, 704 A / D converter 105 temporary discriminator 106 pattern extractor 107 phase shift predictor 108 phase shift detector 109 phase shift detection signal output terminal 205, 505, 605, 705 three-value discriminator 206, 506, 606, 706 threshold setting unit 207, 507, 607,707 Pattern detector 208,508,608,709 Absolute value calculator 209,302,303,509,609,709 D
Flip-flop 210,212,510,610,612 Comparator 211,214,511,513,611,614,7
11,713 Cumulative adder 213,613 Bias threshold setting device 304 EX / NOR circuit 305,306 AND circuit 512,712 Counter

Claims (10)

[Claims] 1. A clock phase detection device for detecting a phase shift of a sampling clock when an input analog signal is converted into a digital signal by an A / D converter, wherein an output signal of the A / D converter is set. Provisional determination means to temporarily determine a discrete value by the threshold value, a pattern extraction means for extracting an array of specific discrete values as a specific pattern from the temporary determination result of the temporary determination means, and a specific pattern from the pattern extraction means When extracted, phase shift direction prediction means for comparing the amplitudes of respective clocks in the output signal of the A / D converter and numerically predicting the clock phase shift direction, and the phase shift direction prediction Phase shift detection means for cumulatively adding and subtracting the numerical values in the shift direction predicted by the means, and generating a clock phase shift detection signal when the cumulative value reaches a specified value,
A clock phase detection device comprising: 2. A clock phase detecting device for detecting a phase shift of a sampling clock when an input analog signal is converted into a digital signal by an A / D converter, wherein an output signal of the A / D converter is set. Provisional determination means to temporarily determine a discrete value by the threshold value, a pattern extraction means for extracting an array of specific discrete values as a specific pattern from the temporary determination result of the temporary determination means, and a specific pattern from the pattern extraction means When extracted, phase shift direction prediction means for comparing the amplitudes of respective clocks in the output signal of the A / D converter and numerically predicting the clock phase shift direction, and the phase shift direction prediction Phase shift direction accumulating means for cumulatively adding and subtracting the numerical value of the shift direction predicted by the means, and a clock position when the cumulative value of the phase shift direction accumulating means reaches a specified value. Clock phase detecting apparatus characterized by comprising the phase shift detection signal generating means for generating a displacement detection signal. 3. A clock phase detection device for detecting a phase shift of a sampling clock when converting an input analog signal into a digital signal by an A / D converter, wherein an output signal of the A / D converter is set. Provisional determination means to temporarily determine a discrete value by the threshold value, a pattern extraction means for extracting an array of specific discrete values as a specific pattern from the temporary determination result of the temporary determination means, and a specific pattern from the pattern extraction means When extracted, phase shift direction prediction means for comparing the amplitudes of respective clocks in the output signal of the A / D converter and numerically predicting the clock phase shift direction, and the phase shift direction prediction Based on the sign of the accumulated value of the phase deviation direction accumulating means and the phase deviation direction accumulating means for accumulating and subtracting the numerical value of the deviation direction predicted by the means. Clock phase detecting apparatus characterized by comprising the phase shift detection signal generating means for generating a phase shift detection signal. 4. A clock phase detection device for detecting a phase shift of a sampling clock when converting an input analog signal into a digital signal by an A / D converter, wherein an output signal of the A / D converter is set. Provisional determination means to temporarily determine a discrete value by the threshold value, a pattern extraction means for extracting an array of specific discrete values as a specific pattern from the temporary determination result of the temporary determination means, and a specific pattern from the pattern extraction means When extracted, phase shift direction prediction means for comparing the amplitudes of respective clocks in the output signal of the A / D converter and numerically predicting the clock phase shift direction, and the phase shift direction prediction Phase shift direction accumulating means for cumulatively adding and subtracting the numerical value of the shift direction predicted by the means, and the clock phase at a constant cycle based on the cumulative value of the phase shift direction accumulating means. Clock phase detecting apparatus characterized by comprising the phase shift detection signal generating means, a that is to generate a detection signal. 5. A clock phase detecting device for detecting a phase shift of a sampling clock when converting an input analog signal into a digital signal by an A / D converter, wherein an output signal of the A / D converter is set. Provisional determination means to temporarily determine a discrete value by the threshold value, a pattern extraction means for extracting an array of specific discrete values as a specific pattern from the temporary determination result of the temporary determination means, and a specific pattern from the pattern extraction means A phase shift direction and a phase shift amount predicting unit that predicts the shift direction and the shift amount of the clock phase by comparing the amplitudes of the respective clocks in the output signal of the A / D converter when extracted. Phase shift amount accumulating means for cumulatively adding and subtracting the phase shift predicted amount obtained by the phase shift direction and phase shift amount predicting means, and a cumulative value of the phase shift amount accumulating means is a prescribed value. On reaching the clock phase detection device, characterized by comprising: a phase shift detection signal generating means for generating a clock phase shift detection signal. 6. A clock phase detection device for detecting a phase shift of a sampling clock when converting an input analog signal into a digital signal by an A / D converter, wherein an output signal of the A / D converter is set. Provisional determination means to temporarily determine a discrete value by the threshold value, a pattern extraction means for extracting an array of specific discrete values as a specific pattern from the temporary determination result of the temporary determination means, and a specific pattern from the pattern extraction means A phase shift direction and a phase shift amount predicting unit that predicts the shift direction and the shift amount of the clock phase by comparing the amplitudes of the respective clocks in the output signal of the A / D converter when extracted. Phase shift amount accumulating means for cumulatively adding and subtracting the phase shift predicted amount obtained by the phase shift direction and phase shift amount predicting means, and a sign of the cumulative value of the phase shift amount accumulating means. Hazuki, clock phase detecting apparatus characterized by comprising: a phase shift detection signal generating means for generating a clock phase shift detection signal at a constant period. 7. A clock phase detection device for detecting a phase shift of a sampling clock when an input analog signal is converted into a digital signal by an A / D converter, wherein an output signal of the A / D converter is set. Provisional determination means to temporarily determine a discrete value by the threshold value, a pattern extraction means for extracting an array of specific discrete values as a specific pattern from the temporary determination result of the temporary determination means, and a specific pattern from the pattern extraction means A phase shift direction and a phase shift amount predicting unit that predicts the shift direction and the shift amount of the clock phase by comparing the amplitudes of the respective clocks in the output signal of the A / D converter when extracted. A phase shift amount accumulating means for cumulatively adding and subtracting the phase shift predicted amount obtained by the phase shift direction and the phase shift amount predicting means; Clock phase detecting apparatus characterized by comprising: a phase shift detection signal generating means for generating a clock phase shift detection signal at a constant period. 8. The clock according to claim 1, wherein the pattern extracting means extracts a pattern of (1,1) or (-1, -1). Phase detector. 9. The pattern extracting means extracts a pattern of (0, 1, 1, 0) or (0, -1, -1, 0).
7. The clock phase detecting device according to any one of 7 above. 10. The pattern extracting means extracts a pattern of (-1, 1, 1, -1) or (1, -1, -1, 1). 7. The clock phase detecting device according to any one of items 1 to 7.