JPH0946232A - Decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a decoding device having a wide operation range which hardly increases a real area on a semiconductor element. SOLUTION: A dummy decoding circuit 19 and a latch clock generation circuit 5 receiving the output of the dummy decoding circuit and controlling a real decoder 15 are provided. The output of the real decoder 15 decoding an input address 18 is latched by a latch clock 17 decided by a clock CLK1 (3) and the output of the dummy decoding circuit 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device, and more particularly to a decoding device that is less likely to malfunction due to changes in operating environment.

[0002]

2. Description of the Related Art The structure of a conventional decoding device will be described with reference to the drawings. FIG. 4 is a schematic configuration diagram of a decoding device incorporated in a microcomputer (hereinafter, abbreviated as a microcomputer) including a semiconductor integrated circuit.

Referring to FIG. 4, this decoding device is
Central processor unit of the microcomputer (hereinafter CP
(Hereinafter abbreviated as U) A latch clock generation circuit 31 that receives a clock 19 for synchronizing with an operation and generates a latch clock 30 having a constant clock width regardless of the length of the cycle of CLK1 (19), and an instruction before decoding. And n-bit data. A decoder 27 that is a dynamic decoding circuit that receives the address 29 and decodes the input address 29, and a latch 23 that uses the latch clock 30 as an input clock and the output of the decoder 27 as input data
With.

Next, the operation of the conventional decoding device will be described with reference to FIGS. 4 and 5. First, the operation of the latch clock generation circuit 31 shown in FIG. 4 will be described. Delay circuit 20
Is a delay circuit using, for example, a capacitance component and a resistance component of a MOSFET (insulated gate field effect transistor). As shown in FIG. 5, when the clock CLK1 (19) is input to the latch clock generation circuit 31 at a certain period, the latch clock 30 having a clock width corresponding to the delay time of the delay circuit 20 is formed. Since the period during which the latch clock 30 is at the high level corresponds to the delay time of the delay circuit 20, even if the cycle of the clock CLK (19) input to the latch clock generation circuit 31 changes, the high level of the latch clock 30. The level range is not affected and remains constant.

Further, in a decoding device which performs a dynamic operation, when the sampling clock width depends on the CPU clock, when the CPU operates at a low speed, the sampling clock width also extends and the precharged level cannot be held. The width needs to be constant without depending on the CPU clock.

Next, the structure of the decoder 27 will be described. FIG. 6 is a block diagram of the decoder 27. Although various configurations of the decoder have been devised, what is shown in FIG. 6 is a so-called dynamic PLA type decoder of a precharge / sampling system. The p-type transistor 26 is a precharging transistor, and the n-type transistor 28 is a sampling transistor, and each is controlled by a latch clock 30. Further, an n-type transistor 40, which is turned on / off according to address information, is connected in series to form one decode line, thereby realizing an AND circuit. Further, an OR circuit is realized by directly connecting a plurality of decode lines at the node 41. The PLA type decoder has various merits such as a relatively small area because it can easily realize a desired logic function and has an array configuration. In addition, the dynamic type of the precharge / sampling method can further reduce the circuit scale and is widely used.

Next, the operation of the entire decoding device will be described.
FIG. 5 is a timing chart showing the operation of the decoder shown in FIG. In this decoder, the latch clock 30
Is low, the precharge p-type transistor 26 is turned on to become a precharge period, and the latch clock 30 is high, the sampling n-type transistor 28 is turned on to be a sampling period.

First, the outputs of all the decoders are precharged to a high level (power supply potential), and the latch clock 30 becomes a high level at the same time when CLK (19) rises, and the sampling period starts. Address 2 during this period
Only the decoder selected by 9 discharges the electric charge stored in the decode line, and the output of the decoder becomes low level. On the other hand, the output of the non-selected decoder dynamically holds the high level.

After the time set by the delay circuit 20 has elapsed, the latch clock 30 becomes low, the sampled data is latched, and at the same time the precharge period starts, and the outputs of all the decoders are precharged to the high level again. Thereafter, the above operation is repeated.

FIG. 5 shows an example in which the decoder 27 is selected when the value of the address 29 is n.

[0011]

However, the conventional decoding device described above has the following problems.

That is, the high level width of the latch clock 30 is determined by the delay time generated by the delay circuit 20, but the delay circuit 20 is constructed by utilizing the resistance component and the capacitance component of the MOSFET. The resistance component of the MOSFET strongly depends on each of the power supply voltage, the temperature, and the threshold voltage. Due to these conditions, the delay time, that is, the high level width of the latch clock 30 is shown in FIGS. ) Changes as shown in each.

In order to perform normal precharge and sampling, the high level width of the latch clock 30 must be within a certain allowable range. In other words, the decoding device, particularly the delay circuit 20. This determines the operable range of the entire system with respect to the power supply voltage and temperature. Therefore, it is not possible to construct a system having a wider operable area.

In order to solve this problem, a delay circuit is provided with M
Although it is technically possible to use only a resistance element and a capacitance element without using the OSFET, there is a problem that the area occupied by the semiconductor chip is considerably increased.

[0015]

Therefore, a decoding device according to the present invention includes a plurality of decoders that perform a logical operation in synchronization with a first control signal and a plurality of decoders in synchronization with a second control signal. In a decoding device having a plurality of latch circuits for storing outputs, a logic circuit that starts operation at the same timing as the decoder and operates slower than the delay time of the decoder, and when the output of this logic circuit changes, It is a configuration including a control signal generation circuit that changes the output and generates the second control signal.

The decoder, the decoder, the latch circuit, the logic circuit, and the control signal generating circuit of the decoding device of the present invention may be formed on the same semiconductor substrate.

Furthermore, the control signal generating circuit of the decoding device of the present invention may be constituted by a latch circuit for receiving the first control signal and a latch circuit for receiving the second control signal.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a decoding device of the present invention. Referring to FIG. 1, a decoding device according to an embodiment of the present invention is controlled by non-overlapping two-phase clocks CLK1 and CLK2 for synchronizing with a CPU (not shown) operation and clocks a clock CLK1 (3). A latch 5 for receiving, a latch 2 for receiving the clock CLK2 (4), a real decoder 15, and a dummy decode circuit 19 including a dummy decoder 8 and having a delay time of the decoder output time which is the latest as compared with the real decoder are provided.

Next, the operation of the decoder device of this embodiment will be described. FIG. 2 is a timing chart showing the operation of the present decoder device. The operation will be described with reference to FIGS. 1 and 2.

First, the dummy decoder 8 in this embodiment will be described with reference to the drawings. FIG. 3 shows an example of a configuration diagram of the dummy decoder. The dummy decoder 8 does not have an address input, and the gate potential of the n-type transistor, which is a constituent element, is fixed at a high level (power supply potential), so that it is always selected regardless of the input address. The difference from the real decoder 15 is that the output of the decoder 15 is always arranged to be later than the outputs of other decoders, and the delay time thereof is larger than that of the real decoder 15. For this reason, the dummy decoder 8 has the same configuration as the slowest decoder among the real decoders 15, and the delay of the sampling clock input to the n-type transistor 7 for discharging the precharged level is maximized. For example, the wiring is arranged in a place where the wiring becomes the longest in the arrangement on the chip. As a specific example, FIG. 3 shows an example of the configuration of the dummy decoder. Referring to FIG. 3, the dummy decoder 8 is configured to take a wired OR of a plurality of decoders in which n-type transistors are vertically stacked, like other decoders. Now, let us assume that the input address is n bits, and the decoder 15 shown in FIG. 3 is an example of the slowest output. This decoder has a wired OR structure of m decoders. The larger the number of wired decoders, the more charges are precharged, and the slower the output of the decoder becomes. As a result, the number of decoders of the dummy decoder is also set to m. If the maximum number of n-type transistors to be stacked vertically on the decoder is n in the actual decoder, the number of transistors to be stacked vertically on one decoder of the dummy decoder is set to n.

Further, it takes the longest time to discharge the charged charges and the decoder outputs the low level because one of the decoders is conductive, and the other decoders are in the ON state except for one transistor. That is, the path through which the precharged electric charges to the transistor portion in the off state escape is longest.

With this structure, the dummy decoder 8 has the same structure as the decoder having the slowest output time among the real decoders 15. Therefore, when the output of the dummy decoder 8 is fixed, the real decoder 15 always outputs. Has been completed.

Next, the overall operation of the present decoder device will be described. If the latch clock 17 is at a low level, the n-type transistor 7 is in an off state and the p-type transistor 9 is in an on state as in the conventional decoding device, and the dummy decoder 8 and each real decoder are at a high level. Precharged. When the clock CLK1 (3) changes from low level to high level, the output of the set / reset flip-flop 5 also changes from low level to high level, so that the latch clock 17 also changes to high level. Since the latch clock 6 changes to the high level, the latch with reset 11 starts sampling of the output of the dummy decoder 8 and the latch 13 starts sampling of the real decoder 15.

At this time, the output of the real decoder 15 outputs a low level if the output of the decode selected by the input address 18 is received, and a high level if it is not selected, as in the conventional decoding device. are doing. As described above, the dummy decoder 8 of this embodiment is always selected regardless of the input address, and the charge precharged by the p-type transistor 9 is the n-type transistor 7.
When is turned on, it is discharged and outputs a low level. Since the output of the dummy decoder 8 is the slowest as compared with the output of other decoders as described above, when the output of the dummy decoder is determined, the output of the other main decoder is already determined. . The output of the dummy decoder 8 is input to the latch with reset 11, and the latch 11 also outputs a high level. Since the output 12 of the dummy decoder and the latch clock 6 which are input to the logical AND gate 1 are both at the high level, the output of the logical AND gate 1 changes to the high level. This is input to the set / reset flip-flop 2 and the output changes to high level. When this is input to the reset of the set / reset flip-flop 5, this output changes to low level, and the latch clock 6 becomes low level. That is, while the latch clock is at the high level (high level width of the latch clock), the clock CLK
It starts when 1 (3) changes to high level, and is determined when the output (12) of the dummy decoder changes to high level. When the latch clock 6 changes to the low level, the latches 11 and 13 with reset latch the outputs from the logic gates 10 and 16 as in the conventional decoding device, the n-type transistor 7 is turned off, and the p-type transistor is turned off. 9 is turned on and starts precharging again. When the clock CLK1 (3) changes to low level, the set / reset flip-flop 5
Keeps the output data, and then the clock CL
When K2 (4) changes to the high level, the set / reset flip-flop 2 is reset and outputs the low level, but the output of the set / reset flip-flop 5 is still held. Further, when the clock CLK2 (4) becomes high level, the latch with reset 11 is also reset and the output changes to low level. After that, this operation is repeated.

[0025]

The effects obtained by the present invention will be described below.

That is, the present invention is provided with a dummy decoder, and the latch clock 1 is generated by the output signal of the dummy decoder.
7 is generated, the power supply voltage and temperature dependence of the high level width of the latch clock completely reflects that of the real decoder. Therefore, it is possible to provide a decoding device having a wider operating area than the conventional decoding device. Furthermore, since the resistive element and the capacitive element are not used at all, the actual area is hardly increased, and
There is no hindrance to the reduction in area due to the progress of fine processing technology.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a decoding device according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing an operation of the decoding device of the present embodiment shown in FIG.

FIG. 3 is a circuit diagram of a dummy decoder of the decoding device of the present embodiment.

FIG. 4 is a configuration diagram of a conventional decoding device.

FIG. 5 is a timing diagram showing the operation of the conventional decoding device.

6 is a decoding circuit diagram of the conventional decoding device shown in FIG. 4;

7A and 7B are diagrams showing environment dependence of a high-level width of a latch clock of a conventional decoding device, FIG. 7A shows dependence on a power supply voltage, and FIG. 7B shows dependence on temperature. It is a figure.

[Explanation of symbols]

 1,2,22 Logic gates 2,5 set reset flip-flops 3,4,19 clocks 7,28,40 n-type transistors 8 dummy decoders 9,26 p-type transistors 11 latches with reset 12 11 outputs 13 23 latches 14 Output 15, 27 Decoder 17 Latch clock 18, 29 Input address 19 Dummy decode circuit 20 Delay circuit 24 23 output 30 latch clock 31 Latch clock generation circuit 41 Decoder contact

Claims (3)

[Claims] 1. A decoding device comprising a plurality of decoders which perform a logical operation in synchronization with a first control signal and a plurality of latch circuits which store respective outputs of the decoder in synchronization with a second control signal. , A logic circuit that starts operation at the same timing as the decoder and operates at a slower speed than the delay time of the decoder, and when the output of this logic circuit changes, the output changes and the second control signal is generated. A decoding device comprising a control signal generating circuit. 2. The decoding device according to claim 1, wherein the decoder, the latch circuit, the logic circuit, and the control signal generating circuit are formed on the same semiconductor substrate. 3. The decoding device according to claim 1, wherein the control signal generating circuit includes a latch circuit that receives the first control signal and a latch circuit that receives the second control signal.